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  1. /*
  2. * Copyright 2004, 2007 Freescale Semiconductor.
  3. * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
  24. *
  25. *
  26. * The processor starts at 0xfff00100 and the code is executed
  27. * from flash. The code is organized to be at an other address
  28. * in memory, but as long we don't jump around before relocating.
  29. * board_init lies at a quite high address and when the cpu has
  30. * jumped there, everything is ok.
  31. */
  32. #include <config.h>
  33. #include <mpc86xx.h>
  34. #include <version.h>
  35. #include <ppc_asm.tmpl>
  36. #include <ppc_defs.h>
  37. #include <asm/cache.h>
  38. #include <asm/mmu.h>
  39. #ifndef CONFIG_IDENT_STRING
  40. #define CONFIG_IDENT_STRING ""
  41. #endif
  42. /*
  43. * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
  44. */
  45. /*
  46. * Set up GOT: Global Offset Table
  47. *
  48. * Use r14 to access the GOT
  49. */
  50. START_GOT
  51. GOT_ENTRY(_GOT2_TABLE_)
  52. GOT_ENTRY(_FIXUP_TABLE_)
  53. GOT_ENTRY(_start)
  54. GOT_ENTRY(_start_of_vectors)
  55. GOT_ENTRY(_end_of_vectors)
  56. GOT_ENTRY(transfer_to_handler)
  57. GOT_ENTRY(__init_end)
  58. GOT_ENTRY(_end)
  59. GOT_ENTRY(__bss_start)
  60. END_GOT
  61. /*
  62. * r3 - 1st arg to board_init(): IMMP pointer
  63. * r4 - 2nd arg to board_init(): boot flag
  64. */
  65. .text
  66. .long 0x27051956 /* U-Boot Magic Number */
  67. .globl version_string
  68. version_string:
  69. .ascii U_BOOT_VERSION
  70. .ascii " (", __DATE__, " - ", __TIME__, ")"
  71. .ascii CONFIG_IDENT_STRING, "\0"
  72. . = EXC_OFF_SYS_RESET
  73. .globl _start
  74. _start:
  75. li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
  76. b boot_cold
  77. sync
  78. . = EXC_OFF_SYS_RESET + 0x10
  79. .globl _start_warm
  80. _start_warm:
  81. li r21, BOOTFLAG_WARM /* Software reboot */
  82. b boot_warm
  83. sync
  84. /* the boot code is located below the exception table */
  85. .globl _start_of_vectors
  86. _start_of_vectors:
  87. /* Machine check */
  88. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  89. /* Data Storage exception. */
  90. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  91. /* Instruction Storage exception. */
  92. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  93. /* External Interrupt exception. */
  94. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  95. /* Alignment exception. */
  96. . = 0x600
  97. Alignment:
  98. EXCEPTION_PROLOG(SRR0, SRR1)
  99. mfspr r4,DAR
  100. stw r4,_DAR(r21)
  101. mfspr r5,DSISR
  102. stw r5,_DSISR(r21)
  103. addi r3,r1,STACK_FRAME_OVERHEAD
  104. li r20,MSR_KERNEL
  105. rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
  106. lwz r6,GOT(transfer_to_handler)
  107. mtlr r6
  108. blrl
  109. .L_Alignment:
  110. .long AlignmentException - _start + EXC_OFF_SYS_RESET
  111. .long int_return - _start + EXC_OFF_SYS_RESET
  112. /* Program check exception */
  113. . = 0x700
  114. ProgramCheck:
  115. EXCEPTION_PROLOG(SRR0, SRR1)
  116. addi r3,r1,STACK_FRAME_OVERHEAD
  117. li r20,MSR_KERNEL
  118. rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
  119. lwz r6,GOT(transfer_to_handler)
  120. mtlr r6
  121. blrl
  122. .L_ProgramCheck:
  123. .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
  124. .long int_return - _start + EXC_OFF_SYS_RESET
  125. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  126. /* I guess we could implement decrementer, and may have
  127. * to someday for timekeeping.
  128. */
  129. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  130. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  131. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  132. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  133. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  134. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  135. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  136. STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
  137. STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
  138. STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
  139. STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
  140. STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
  141. STD_EXCEPTION(0x1500, Reserved5, UnknownException)
  142. STD_EXCEPTION(0x1600, Reserved6, UnknownException)
  143. STD_EXCEPTION(0x1700, Reserved7, UnknownException)
  144. STD_EXCEPTION(0x1800, Reserved8, UnknownException)
  145. STD_EXCEPTION(0x1900, Reserved9, UnknownException)
  146. STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
  147. STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
  148. STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
  149. STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
  150. STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
  151. STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
  152. .globl _end_of_vectors
  153. _end_of_vectors:
  154. . = 0x2000
  155. boot_cold:
  156. boot_warm:
  157. /*
  158. * NOTE: Only Cpu 0 will ever come here. Other cores go to an
  159. * address specified by the BPTR
  160. */
  161. 1:
  162. #ifdef CONFIG_SYS_RAMBOOT
  163. /* disable everything */
  164. li r0, 0
  165. mtspr HID0, r0
  166. sync
  167. mtmsr 0
  168. #endif
  169. /* Invalidate BATs */
  170. bl invalidate_bats
  171. sync
  172. /* Invalidate all of TLB before MMU turn on */
  173. bl clear_tlbs
  174. sync
  175. #ifdef CONFIG_SYS_L2
  176. /* init the L2 cache */
  177. lis r3, L2_INIT@h
  178. ori r3, r3, L2_INIT@l
  179. mtspr l2cr, r3
  180. /* invalidate the L2 cache */
  181. bl l2cache_invalidate
  182. sync
  183. #endif
  184. /*
  185. * Calculate absolute address in FLASH and jump there
  186. *------------------------------------------------------*/
  187. lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
  188. ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
  189. addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
  190. mtlr r3
  191. blr
  192. in_flash:
  193. /* let the C-code set up the rest */
  194. /* */
  195. /* Be careful to keep code relocatable ! */
  196. /*------------------------------------------------------*/
  197. /* perform low-level init */
  198. /* enable extended addressing */
  199. bl enable_ext_addr
  200. /* setup the bats */
  201. bl early_bats
  202. /*
  203. * Cache must be enabled here for stack-in-cache trick.
  204. * This means we need to enable the BATS.
  205. * Cache should be turned on after BATs, since by default
  206. * everything is write-through.
  207. */
  208. /* enable address translation */
  209. mfmsr r5
  210. ori r5, r5, (MSR_IR | MSR_DR)
  211. lis r3,addr_trans_enabled@h
  212. ori r3, r3, addr_trans_enabled@l
  213. mtspr SPRN_SRR0,r3
  214. mtspr SPRN_SRR1,r5
  215. rfi
  216. addr_trans_enabled:
  217. /* enable and invalidate the data cache */
  218. /* bl l1dcache_enable */
  219. bl dcache_enable
  220. sync
  221. #if 1
  222. bl icache_enable
  223. #endif
  224. #ifdef CONFIG_SYS_INIT_RAM_LOCK
  225. bl lock_ram_in_cache
  226. sync
  227. #endif
  228. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  229. bl setup_ccsrbar
  230. #endif
  231. /* set up the stack pointer in our newly created
  232. * cache-ram (r1) */
  233. lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
  234. ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
  235. li r0, 0 /* Make room for stack frame header and */
  236. stwu r0, -4(r1) /* clear final stack frame so that */
  237. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  238. GET_GOT /* initialize GOT access */
  239. /* run low-level CPU init code (from Flash) */
  240. bl cpu_init_f
  241. sync
  242. #ifdef RUN_DIAG
  243. /* Load PX_AUX register address in r4 */
  244. lis r4, PIXIS_BASE@h
  245. ori r4, r4, 0x6
  246. /* Load contents of PX_AUX in r3 bits 24 to 31*/
  247. lbz r3, 0(r4)
  248. /* Mask and obtain the bit in r3 */
  249. rlwinm. r3, r3, 0, 24, 24
  250. /* If not zero, jump and continue with u-boot */
  251. bne diag_done
  252. /* Load back contents of PX_AUX in r3 bits 24 to 31 */
  253. lbz r3, 0(r4)
  254. /* Set the MSB of the register value */
  255. ori r3, r3, 0x80
  256. /* Write value in r3 back to PX_AUX */
  257. stb r3, 0(r4)
  258. /* Get the address to jump to in r3*/
  259. lis r3, CONFIG_SYS_DIAG_ADDR@h
  260. ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
  261. /* Load the LR with the branch address */
  262. mtlr r3
  263. /* Branch to diagnostic */
  264. blr
  265. diag_done:
  266. #endif
  267. /* bl l2cache_enable */
  268. mr r3, r21
  269. /* r3: BOOTFLAG */
  270. /* run 1st part of board init code (from Flash) */
  271. bl board_init_f
  272. sync
  273. /* NOTREACHED */
  274. .globl invalidate_bats
  275. invalidate_bats:
  276. li r0, 0
  277. /* invalidate BATs */
  278. mtspr IBAT0U, r0
  279. mtspr IBAT1U, r0
  280. mtspr IBAT2U, r0
  281. mtspr IBAT3U, r0
  282. mtspr IBAT4U, r0
  283. mtspr IBAT5U, r0
  284. mtspr IBAT6U, r0
  285. mtspr IBAT7U, r0
  286. isync
  287. mtspr DBAT0U, r0
  288. mtspr DBAT1U, r0
  289. mtspr DBAT2U, r0
  290. mtspr DBAT3U, r0
  291. mtspr DBAT4U, r0
  292. mtspr DBAT5U, r0
  293. mtspr DBAT6U, r0
  294. mtspr DBAT7U, r0
  295. isync
  296. sync
  297. blr
  298. /*
  299. * early_bats:
  300. *
  301. * Set up bats needed early on - this is usually the BAT for the
  302. * stack-in-cache, the Flash, and CCSR space
  303. */
  304. .globl early_bats
  305. early_bats:
  306. /* IBAT 3 */
  307. lis r4, CONFIG_SYS_IBAT3L@h
  308. ori r4, r4, CONFIG_SYS_IBAT3L@l
  309. lis r3, CONFIG_SYS_IBAT3U@h
  310. ori r3, r3, CONFIG_SYS_IBAT3U@l
  311. mtspr IBAT3L, r4
  312. mtspr IBAT3U, r3
  313. isync
  314. /* DBAT 3 */
  315. lis r4, CONFIG_SYS_DBAT3L@h
  316. ori r4, r4, CONFIG_SYS_DBAT3L@l
  317. lis r3, CONFIG_SYS_DBAT3U@h
  318. ori r3, r3, CONFIG_SYS_DBAT3U@l
  319. mtspr DBAT3L, r4
  320. mtspr DBAT3U, r3
  321. isync
  322. /* IBAT 5 */
  323. lis r4, CONFIG_SYS_IBAT5L@h
  324. ori r4, r4, CONFIG_SYS_IBAT5L@l
  325. lis r3, CONFIG_SYS_IBAT5U@h
  326. ori r3, r3, CONFIG_SYS_IBAT5U@l
  327. mtspr IBAT5L, r4
  328. mtspr IBAT5U, r3
  329. isync
  330. /* DBAT 5 */
  331. lis r4, CONFIG_SYS_DBAT5L@h
  332. ori r4, r4, CONFIG_SYS_DBAT5L@l
  333. lis r3, CONFIG_SYS_DBAT5U@h
  334. ori r3, r3, CONFIG_SYS_DBAT5U@l
  335. mtspr DBAT5L, r4
  336. mtspr DBAT5U, r3
  337. isync
  338. /* IBAT 6 */
  339. lis r4, CONFIG_SYS_IBAT6L_EARLY@h
  340. ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
  341. lis r3, CONFIG_SYS_IBAT6U_EARLY@h
  342. ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
  343. mtspr IBAT6L, r4
  344. mtspr IBAT6U, r3
  345. isync
  346. /* DBAT 6 */
  347. lis r4, CONFIG_SYS_DBAT6L_EARLY@h
  348. ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
  349. lis r3, CONFIG_SYS_DBAT6U_EARLY@h
  350. ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
  351. mtspr DBAT6L, r4
  352. mtspr DBAT6U, r3
  353. isync
  354. #if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  355. /* IBAT 7 */
  356. lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
  357. ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
  358. lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
  359. ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
  360. mtspr IBAT7L, r4
  361. mtspr IBAT7U, r3
  362. isync
  363. /* DBAT 7 */
  364. lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
  365. ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
  366. lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
  367. ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
  368. mtspr DBAT7L, r4
  369. mtspr DBAT7U, r3
  370. isync
  371. #endif
  372. blr
  373. .globl clear_tlbs
  374. clear_tlbs:
  375. addis r3, 0, 0x0000
  376. addis r5, 0, 0x4
  377. isync
  378. tlblp:
  379. tlbie r3
  380. sync
  381. addi r3, r3, 0x1000
  382. cmp 0, 0, r3, r5
  383. blt tlblp
  384. blr
  385. .globl disable_addr_trans
  386. disable_addr_trans:
  387. /* disable address translation */
  388. mflr r4
  389. mfmsr r3
  390. andi. r0, r3, (MSR_IR | MSR_DR)
  391. beqlr
  392. andc r3, r3, r0
  393. mtspr SRR0, r4
  394. mtspr SRR1, r3
  395. rfi
  396. /*
  397. * This code finishes saving the registers to the exception frame
  398. * and jumps to the appropriate handler for the exception.
  399. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  400. */
  401. .globl transfer_to_handler
  402. transfer_to_handler:
  403. stw r22,_NIP(r21)
  404. lis r22,MSR_POW@h
  405. andc r23,r23,r22
  406. stw r23,_MSR(r21)
  407. SAVE_GPR(7, r21)
  408. SAVE_4GPRS(8, r21)
  409. SAVE_8GPRS(12, r21)
  410. SAVE_8GPRS(24, r21)
  411. mflr r23
  412. andi. r24,r23,0x3f00 /* get vector offset */
  413. stw r24,TRAP(r21)
  414. li r22,0
  415. stw r22,RESULT(r21)
  416. mtspr SPRG2,r22 /* r1 is now kernel sp */
  417. lwz r24,0(r23) /* virtual address of handler */
  418. lwz r23,4(r23) /* where to go when done */
  419. mtspr SRR0,r24
  420. mtspr SRR1,r20
  421. mtlr r23
  422. SYNC
  423. rfi /* jump to handler, enable MMU */
  424. int_return:
  425. mfmsr r28 /* Disable interrupts */
  426. li r4,0
  427. ori r4,r4,MSR_EE
  428. andc r28,r28,r4
  429. SYNC /* Some chip revs need this... */
  430. mtmsr r28
  431. SYNC
  432. lwz r2,_CTR(r1)
  433. lwz r0,_LINK(r1)
  434. mtctr r2
  435. mtlr r0
  436. lwz r2,_XER(r1)
  437. lwz r0,_CCR(r1)
  438. mtspr XER,r2
  439. mtcrf 0xFF,r0
  440. REST_10GPRS(3, r1)
  441. REST_10GPRS(13, r1)
  442. REST_8GPRS(23, r1)
  443. REST_GPR(31, r1)
  444. lwz r2,_NIP(r1) /* Restore environment */
  445. lwz r0,_MSR(r1)
  446. mtspr SRR0,r2
  447. mtspr SRR1,r0
  448. lwz r0,GPR0(r1)
  449. lwz r2,GPR2(r1)
  450. lwz r1,GPR1(r1)
  451. SYNC
  452. rfi
  453. .globl dc_read
  454. dc_read:
  455. blr
  456. .globl get_pvr
  457. get_pvr:
  458. mfspr r3, PVR
  459. blr
  460. .globl get_svr
  461. get_svr:
  462. mfspr r3, SVR
  463. blr
  464. /*
  465. * Function: in8
  466. * Description: Input 8 bits
  467. */
  468. .globl in8
  469. in8:
  470. lbz r3,0x0000(r3)
  471. blr
  472. /*
  473. * Function: out8
  474. * Description: Output 8 bits
  475. */
  476. .globl out8
  477. out8:
  478. stb r4,0x0000(r3)
  479. blr
  480. /*
  481. * Function: out16
  482. * Description: Output 16 bits
  483. */
  484. .globl out16
  485. out16:
  486. sth r4,0x0000(r3)
  487. blr
  488. /*
  489. * Function: out16r
  490. * Description: Byte reverse and output 16 bits
  491. */
  492. .globl out16r
  493. out16r:
  494. sthbrx r4,r0,r3
  495. blr
  496. /*
  497. * Function: out32
  498. * Description: Output 32 bits
  499. */
  500. .globl out32
  501. out32:
  502. stw r4,0x0000(r3)
  503. blr
  504. /*
  505. * Function: out32r
  506. * Description: Byte reverse and output 32 bits
  507. */
  508. .globl out32r
  509. out32r:
  510. stwbrx r4,r0,r3
  511. blr
  512. /*
  513. * Function: in16
  514. * Description: Input 16 bits
  515. */
  516. .globl in16
  517. in16:
  518. lhz r3,0x0000(r3)
  519. blr
  520. /*
  521. * Function: in16r
  522. * Description: Input 16 bits and byte reverse
  523. */
  524. .globl in16r
  525. in16r:
  526. lhbrx r3,r0,r3
  527. blr
  528. /*
  529. * Function: in32
  530. * Description: Input 32 bits
  531. */
  532. .globl in32
  533. in32:
  534. lwz 3,0x0000(3)
  535. blr
  536. /*
  537. * Function: in32r
  538. * Description: Input 32 bits and byte reverse
  539. */
  540. .globl in32r
  541. in32r:
  542. lwbrx r3,r0,r3
  543. blr
  544. /*
  545. * void relocate_code (addr_sp, gd, addr_moni)
  546. *
  547. * This "function" does not return, instead it continues in RAM
  548. * after relocating the monitor code.
  549. *
  550. * r3 = dest
  551. * r4 = src
  552. * r5 = length in bytes
  553. * r6 = cachelinesize
  554. */
  555. .globl relocate_code
  556. relocate_code:
  557. mr r1, r3 /* Set new stack pointer */
  558. mr r9, r4 /* Save copy of Global Data pointer */
  559. mr r10, r5 /* Save copy of Destination Address */
  560. mr r3, r5 /* Destination Address */
  561. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  562. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  563. lwz r5, GOT(__init_end)
  564. sub r5, r5, r4
  565. li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  566. /*
  567. * Fix GOT pointer:
  568. *
  569. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  570. *
  571. * Offset:
  572. */
  573. sub r15, r10, r4
  574. /* First our own GOT */
  575. add r14, r14, r15
  576. /* then the one used by the C code */
  577. add r30, r30, r15
  578. /*
  579. * Now relocate code
  580. */
  581. cmplw cr1,r3,r4
  582. addi r0,r5,3
  583. srwi. r0,r0,2
  584. beq cr1,4f /* In place copy is not necessary */
  585. beq 7f /* Protect against 0 count */
  586. mtctr r0
  587. bge cr1,2f
  588. la r8,-4(r4)
  589. la r7,-4(r3)
  590. 1: lwzu r0,4(r8)
  591. stwu r0,4(r7)
  592. bdnz 1b
  593. b 4f
  594. 2: slwi r0,r0,2
  595. add r8,r4,r0
  596. add r7,r3,r0
  597. 3: lwzu r0,-4(r8)
  598. stwu r0,-4(r7)
  599. bdnz 3b
  600. /*
  601. * Now flush the cache: note that we must start from a cache aligned
  602. * address. Otherwise we might miss one cache line.
  603. */
  604. 4: cmpwi r6,0
  605. add r5,r3,r5
  606. beq 7f /* Always flush prefetch queue in any case */
  607. subi r0,r6,1
  608. andc r3,r3,r0
  609. mr r4,r3
  610. 5: dcbst 0,r4
  611. add r4,r4,r6
  612. cmplw r4,r5
  613. blt 5b
  614. sync /* Wait for all dcbst to complete on bus */
  615. mr r4,r3
  616. 6: icbi 0,r4
  617. add r4,r4,r6
  618. cmplw r4,r5
  619. blt 6b
  620. 7: sync /* Wait for all icbi to complete on bus */
  621. isync
  622. /*
  623. * We are done. Do not return, instead branch to second part of board
  624. * initialization, now running from RAM.
  625. */
  626. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  627. mtlr r0
  628. blr
  629. in_ram:
  630. /*
  631. * Relocation Function, r14 point to got2+0x8000
  632. *
  633. * Adjust got2 pointers, no need to check for 0, this code
  634. * already puts a few entries in the table.
  635. */
  636. li r0,__got2_entries@sectoff@l
  637. la r3,GOT(_GOT2_TABLE_)
  638. lwz r11,GOT(_GOT2_TABLE_)
  639. mtctr r0
  640. sub r11,r3,r11
  641. addi r3,r3,-4
  642. 1: lwzu r0,4(r3)
  643. add r0,r0,r11
  644. stw r0,0(r3)
  645. bdnz 1b
  646. /*
  647. * Now adjust the fixups and the pointers to the fixups
  648. * in case we need to move ourselves again.
  649. */
  650. 2: li r0,__fixup_entries@sectoff@l
  651. lwz r3,GOT(_FIXUP_TABLE_)
  652. cmpwi r0,0
  653. mtctr r0
  654. addi r3,r3,-4
  655. beq 4f
  656. 3: lwzu r4,4(r3)
  657. lwzux r0,r4,r11
  658. add r0,r0,r11
  659. stw r10,0(r3)
  660. stw r0,0(r4)
  661. bdnz 3b
  662. 4:
  663. /* clear_bss: */
  664. /*
  665. * Now clear BSS segment
  666. */
  667. lwz r3,GOT(__bss_start)
  668. lwz r4,GOT(_end)
  669. cmplw 0, r3, r4
  670. beq 6f
  671. li r0, 0
  672. 5:
  673. stw r0, 0(r3)
  674. addi r3, r3, 4
  675. cmplw 0, r3, r4
  676. bne 5b
  677. 6:
  678. mr r3, r9 /* Init Date pointer */
  679. mr r4, r10 /* Destination Address */
  680. bl board_init_r
  681. /* not reached - end relocate_code */
  682. /*-----------------------------------------------------------------------*/
  683. /*
  684. * Copy exception vector code to low memory
  685. *
  686. * r3: dest_addr
  687. * r7: source address, r8: end address, r9: target address
  688. */
  689. .globl trap_init
  690. trap_init:
  691. lwz r7, GOT(_start)
  692. lwz r8, GOT(_end_of_vectors)
  693. li r9, 0x100 /* reset vector always at 0x100 */
  694. cmplw 0, r7, r8
  695. bgelr /* return if r7>=r8 - just in case */
  696. mflr r4 /* save link register */
  697. 1:
  698. lwz r0, 0(r7)
  699. stw r0, 0(r9)
  700. addi r7, r7, 4
  701. addi r9, r9, 4
  702. cmplw 0, r7, r8
  703. bne 1b
  704. /*
  705. * relocate `hdlr' and `int_return' entries
  706. */
  707. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  708. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  709. 2:
  710. bl trap_reloc
  711. addi r7, r7, 0x100 /* next exception vector */
  712. cmplw 0, r7, r8
  713. blt 2b
  714. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  715. bl trap_reloc
  716. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  717. bl trap_reloc
  718. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  719. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  720. 3:
  721. bl trap_reloc
  722. addi r7, r7, 0x100 /* next exception vector */
  723. cmplw 0, r7, r8
  724. blt 3b
  725. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  726. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  727. 4:
  728. bl trap_reloc
  729. addi r7, r7, 0x100 /* next exception vector */
  730. cmplw 0, r7, r8
  731. blt 4b
  732. /* enable execptions from RAM vectors */
  733. mfmsr r7
  734. li r8,MSR_IP
  735. andc r7,r7,r8
  736. ori r7,r7,MSR_ME /* Enable Machine Check */
  737. mtmsr r7
  738. mtlr r4 /* restore link register */
  739. blr
  740. /*
  741. * Function: relocate entries for one exception vector
  742. */
  743. trap_reloc:
  744. lwz r0, 0(r7) /* hdlr ... */
  745. add r0, r0, r3 /* ... += dest_addr */
  746. stw r0, 0(r7)
  747. lwz r0, 4(r7) /* int_return ... */
  748. add r0, r0, r3 /* ... += dest_addr */
  749. stw r0, 4(r7)
  750. sync
  751. isync
  752. blr
  753. .globl enable_ext_addr
  754. enable_ext_addr:
  755. mfspr r0, HID0
  756. lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
  757. ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
  758. mtspr HID0, r0
  759. sync
  760. isync
  761. blr
  762. #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
  763. .globl setup_ccsrbar
  764. setup_ccsrbar:
  765. /* Special sequence needed to update CCSRBAR itself */
  766. lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
  767. ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
  768. lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
  769. ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
  770. srwi r5,r5,12
  771. li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
  772. rlwimi r5,r6,20,8,11
  773. stw r5, 0(r4) /* Store physical value of CCSR */
  774. isync
  775. lis r5, TEXT_BASE@h
  776. ori r5,r5,TEXT_BASE@l
  777. lwz r5, 0(r5)
  778. isync
  779. /* Use VA of CCSR to do read */
  780. lis r3, CONFIG_SYS_CCSRBAR@h
  781. lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
  782. isync
  783. blr
  784. #endif
  785. #ifdef CONFIG_SYS_INIT_RAM_LOCK
  786. lock_ram_in_cache:
  787. /* Allocate Initial RAM in data cache.
  788. */
  789. lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
  790. ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
  791. li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
  792. (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
  793. mtctr r4
  794. 1:
  795. dcbz r0, r3
  796. addi r3, r3, 32
  797. bdnz 1b
  798. #if 1
  799. /* Lock the data cache */
  800. mfspr r0, HID0
  801. ori r0, r0, 0x1000
  802. sync
  803. mtspr HID0, r0
  804. sync
  805. blr
  806. #endif
  807. #if 0
  808. /* Lock the first way of the data cache */
  809. mfspr r0, LDSTCR
  810. ori r0, r0, 0x0080
  811. #if defined(CONFIG_ALTIVEC)
  812. dssall
  813. #endif
  814. sync
  815. mtspr LDSTCR, r0
  816. sync
  817. isync
  818. blr
  819. #endif
  820. .globl unlock_ram_in_cache
  821. unlock_ram_in_cache:
  822. /* invalidate the INIT_RAM section */
  823. lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
  824. ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
  825. li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
  826. (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
  827. mtctr r4
  828. 1: icbi r0, r3
  829. addi r3, r3, 32
  830. bdnz 1b
  831. sync /* Wait for all icbi to complete on bus */
  832. isync
  833. #if 1
  834. /* Unlock the data cache and invalidate it */
  835. mfspr r0, HID0
  836. li r3,0x1000
  837. andc r0,r0,r3
  838. li r3,0x0400
  839. or r0,r0,r3
  840. sync
  841. mtspr HID0, r0
  842. sync
  843. blr
  844. #endif
  845. #if 0
  846. /* Unlock the first way of the data cache */
  847. mfspr r0, LDSTCR
  848. li r3,0x0080
  849. andc r0,r0,r3
  850. #ifdef CONFIG_ALTIVEC
  851. dssall
  852. #endif
  853. sync
  854. mtspr LDSTCR, r0
  855. sync
  856. isync
  857. li r3,0x0400
  858. or r0,r0,r3
  859. sync
  860. mtspr HID0, r0
  861. sync
  862. blr
  863. #endif
  864. #endif