P1022DS.h 14 KB

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  1. /*
  2. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  3. * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  4. * Timur Tabi <timur@freescale.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the Free
  8. * Software Foundation; either version 2 of the License, or (at your option)
  9. * any later version.
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. #include "../board/freescale/common/ics307_clk.h"
  14. /* High Level Configuration Options */
  15. #define CONFIG_BOOKE /* BOOKE */
  16. #define CONFIG_E500 /* BOOKE e500 family */
  17. #define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
  18. #define CONFIG_P1022
  19. #define CONFIG_P1022DS
  20. #define CONFIG_MP /* support multiple processors */
  21. #ifndef CONFIG_SYS_TEXT_BASE
  22. #define CONFIG_SYS_TEXT_BASE 0xeff80000
  23. #endif
  24. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  25. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  26. #endif
  27. #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
  28. #define CONFIG_PCI /* Enable PCI/PCIE */
  29. #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
  30. #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
  31. #define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
  32. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  33. #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  34. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  35. #define CONFIG_PHYS_64BIT
  36. #define CONFIG_ENABLE_36BIT_PHYS
  37. #define CONFIG_ADDR_MAP
  38. #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
  39. #define CONFIG_FSL_LAW /* Use common FSL init code */
  40. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  41. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  42. #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
  43. /*
  44. * These can be toggled for performance analysis, otherwise use default.
  45. */
  46. #define CONFIG_L2_CACHE
  47. #define CONFIG_BTB
  48. #define CONFIG_SYS_MEMTEST_START 0x00000000
  49. #define CONFIG_SYS_MEMTEST_END 0x7fffffff
  50. /*
  51. * Base addresses -- Note these are effective addresses where the
  52. * actual resources get mapped (not physical addresses)
  53. */
  54. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  55. #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
  56. #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
  57. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
  58. /* DDR Setup */
  59. #define CONFIG_DDR_SPD
  60. #define CONFIG_VERY_BIG_RAM
  61. #define CONFIG_FSL_DDR3
  62. #ifdef CONFIG_DDR_ECC
  63. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  64. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  65. #endif
  66. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  67. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  68. #define CONFIG_NUM_DDR_CONTROLLERS 1
  69. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  70. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  71. /* I2C addresses of SPD EEPROMs */
  72. #define CONFIG_SYS_SPD_BUS_NUM 1
  73. #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
  74. /*
  75. * Memory map
  76. *
  77. * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
  78. * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
  79. * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
  80. *
  81. * Localbus cacheable (TBD)
  82. * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
  83. *
  84. * Localbus non-cacheable
  85. * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
  86. * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
  87. * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
  88. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
  89. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  90. */
  91. /*
  92. * Local Bus Definitions
  93. */
  94. #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
  95. #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
  96. #define CONFIG_FLASH_BR_PRELIM \
  97. (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
  98. #define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
  99. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  100. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  101. #define CONFIG_SYS_BR1_PRELIM \
  102. (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
  103. #define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
  104. #define CONFIG_SYS_FLASH_BANKS_LIST \
  105. {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  106. #define CONFIG_SYS_FLASH_QUIET_TEST
  107. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  108. #define CONFIG_SYS_MAX_FLASH_BANKS 2
  109. #define CONFIG_SYS_MAX_FLASH_SECT 1024
  110. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  111. #define CONFIG_FLASH_CFI_DRIVER
  112. #define CONFIG_SYS_FLASH_CFI
  113. #define CONFIG_SYS_FLASH_EMPTY_INFO
  114. #define CONFIG_BOARD_EARLY_INIT_F
  115. #define CONFIG_BOARD_EARLY_INIT_R
  116. #define CONFIG_MISC_INIT_R
  117. #define CONFIG_HWCONFIG
  118. #define CONFIG_FSL_NGPIXIS
  119. #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
  120. #define PIXIS_BASE_PHYS 0xfffdf0000ull
  121. #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
  122. #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
  123. #define PIXIS_LBMAP_SWITCH 7
  124. #define PIXIS_LBMAP_MASK 0xF0
  125. #define PIXIS_LBMAP_ALTBANK 0x20
  126. #define CONFIG_SYS_INIT_RAM_LOCK
  127. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
  128. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  129. #define CONFIG_SYS_GBL_DATA_OFFSET \
  130. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  131. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  132. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  133. #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
  134. /*
  135. * Serial Port
  136. */
  137. #define CONFIG_CONS_INDEX 1
  138. #define CONFIG_SYS_NS16550
  139. #define CONFIG_SYS_NS16550_SERIAL
  140. #define CONFIG_SYS_NS16550_REG_SIZE 1
  141. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  142. #define CONFIG_SYS_BAUDRATE_TABLE \
  143. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  144. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  145. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  146. /* Use the HUSH parser */
  147. #define CONFIG_SYS_HUSH_PARSER
  148. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  149. /* Video */
  150. #undef CONFIG_FSL_DIU_FB
  151. #ifdef CONFIG_FSL_DIU_FB
  152. #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
  153. #define CONFIG_VIDEO
  154. #define CONFIG_CMD_BMP
  155. #define CONFIG_CFB_CONSOLE
  156. #define CONFIG_VGA_AS_SINGLE_DEVICE
  157. #define CONFIG_VIDEO_LOGO
  158. #define CONFIG_VIDEO_BMP_LOGO
  159. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  160. /*
  161. * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  162. * disable empty flash sector detection, which is I/O-intensive.
  163. */
  164. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  165. #endif
  166. /*
  167. * Pass open firmware flat tree
  168. */
  169. #define CONFIG_OF_LIBFDT
  170. #define CONFIG_OF_BOARD_SETUP
  171. #define CONFIG_OF_STDOUT_VIA_ALIAS
  172. /* new uImage format support */
  173. #define CONFIG_FIT
  174. #define CONFIG_FIT_VERBOSE
  175. /* I2C */
  176. #define CONFIG_FSL_I2C
  177. #define CONFIG_HARD_I2C
  178. #define CONFIG_I2C_MULTI_BUS
  179. #define CONFIG_SYS_I2C_SPEED 400000
  180. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  181. #define CONFIG_SYS_I2C_SLAVE 0x7F
  182. #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
  183. #define CONFIG_SYS_I2C_OFFSET 0x3000
  184. #define CONFIG_SYS_I2C2_OFFSET 0x3100
  185. /*
  186. * I2C2 EEPROM
  187. */
  188. #define CONFIG_ID_EEPROM
  189. #define CONFIG_SYS_I2C_EEPROM_NXID
  190. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  191. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  192. #define CONFIG_SYS_EEPROM_BUS_NUM 1
  193. /*
  194. * General PCI
  195. * Memory space is mapped 1-1, but I/O space must start from 0.
  196. */
  197. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  198. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
  199. #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  200. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
  201. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  202. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
  203. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  204. #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
  205. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  206. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  207. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  208. #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  209. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  210. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  211. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  212. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  213. #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
  214. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  215. /* controller 3, Slot 1, tgtid 3, Base address b000 */
  216. #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
  217. #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  218. #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
  219. #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  220. #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
  221. #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  222. #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
  223. #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  224. #ifdef CONFIG_PCI
  225. #define CONFIG_NET_MULTI
  226. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  227. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  228. #define CONFIG_E1000 /* Define e1000 pci Ethernet card */
  229. #endif
  230. /* SATA */
  231. #define CONFIG_LIBATA
  232. #define CONFIG_FSL_SATA
  233. #define CONFIG_FSL_SATA_V2
  234. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  235. #define CONFIG_SATA1
  236. #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  237. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  238. #define CONFIG_SATA2
  239. #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  240. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  241. #ifdef CONFIG_FSL_SATA
  242. #define CONFIG_LBA48
  243. #define CONFIG_CMD_SATA
  244. #define CONFIG_DOS_PARTITION
  245. #define CONFIG_CMD_EXT2
  246. #endif
  247. #define CONFIG_MMC
  248. #ifdef CONFIG_MMC
  249. #define CONFIG_CMD_MMC
  250. #define CONFIG_FSL_ESDHC
  251. #define CONFIG_GENERIC_MMC
  252. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  253. #endif
  254. #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
  255. #define CONFIG_CMD_EXT2
  256. #define CONFIG_CMD_FAT
  257. #define CONFIG_DOS_PARTITION
  258. #endif
  259. #define CONFIG_TSEC_ENET
  260. #ifdef CONFIG_TSEC_ENET
  261. #define CONFIG_TSECV2
  262. #define CONFIG_NET_MULTI
  263. #define CONFIG_MII /* MII PHY management */
  264. #define CONFIG_TSEC1 1
  265. #define CONFIG_TSEC1_NAME "eTSEC1"
  266. #define CONFIG_TSEC2 1
  267. #define CONFIG_TSEC2_NAME "eTSEC2"
  268. #define TSEC1_PHY_ADDR 1
  269. #define TSEC2_PHY_ADDR 2
  270. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  271. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  272. #define TSEC1_PHYIDX 0
  273. #define TSEC2_PHYIDX 0
  274. #define CONFIG_ETHPRIME "eTSEC1"
  275. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  276. #endif
  277. /*
  278. * Environment
  279. */
  280. #define CONFIG_ENV_IS_IN_FLASH
  281. #define CONFIG_ENV_OVERWRITE
  282. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  283. #define CONFIG_ENV_SIZE 0x2000
  284. #define CONFIG_ENV_SECT_SIZE 0x20000
  285. #define CONFIG_LOADS_ECHO
  286. #define CONFIG_SYS_LOADS_BAUD_CHANGE
  287. /*
  288. * Command line configuration.
  289. */
  290. #include <config_cmd_default.h>
  291. #define CONFIG_CMD_ELF
  292. #define CONFIG_CMD_ERRATA
  293. #define CONFIG_CMD_IRQ
  294. #define CONFIG_CMD_I2C
  295. #define CONFIG_CMD_MII
  296. #define CONFIG_CMD_PING
  297. #define CONFIG_CMD_SETEXPR
  298. #define CONFIG_CMD_REGINFO
  299. #ifdef CONFIG_PCI
  300. #define CONFIG_CMD_PCI
  301. #define CONFIG_CMD_NET
  302. #endif
  303. /*
  304. * USB
  305. */
  306. #define CONFIG_USB_EHCI
  307. #ifdef CONFIG_USB_EHCI
  308. #define CONFIG_CMD_USB
  309. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  310. #define CONFIG_USB_EHCI_FSL
  311. #define CONFIG_USB_STORAGE
  312. #define CONFIG_CMD_FAT
  313. #endif
  314. /*
  315. * Miscellaneous configurable options
  316. */
  317. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  318. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  319. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  320. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  321. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  322. #ifdef CONFIG_CMD_KGDB
  323. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  324. #else
  325. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  326. #endif
  327. /* Print Buffer Size */
  328. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  329. #define CONFIG_SYS_MAXARGS 16
  330. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  331. #define CONFIG_SYS_HZ 1000
  332. /*
  333. * For booting Linux, the board info and command line data
  334. * have to be in the first 16 MB of memory, since this is
  335. * the maximum mapped by the Linux kernel during initialization.
  336. */
  337. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  338. #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
  339. #ifdef CONFIG_CMD_KGDB
  340. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  341. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  342. #endif
  343. /*
  344. * Environment Configuration
  345. */
  346. #define CONFIG_HOSTNAME p1022ds
  347. #define CONFIG_ROOTPATH /opt/nfsroot
  348. #define CONFIG_BOOTFILE uImage
  349. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  350. #define CONFIG_LOADADDR 1000000
  351. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  352. #define CONFIG_BOOTARGS
  353. #define CONFIG_BAUDRATE 115200
  354. #define CONFIG_EXTRA_ENV_SETTINGS \
  355. "perf_mode=stable\0" \
  356. "memctl_intlv_ctl=2\0" \
  357. "netdev=eth0\0" \
  358. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  359. "tftpflash=tftpboot $loadaddr $uboot; " \
  360. "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  361. "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  362. "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
  363. "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
  364. "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
  365. "consoledev=ttyS0\0" \
  366. "ramdiskaddr=2000000\0" \
  367. "ramdiskfile=uramdisk\0" \
  368. "fdtaddr=c00000\0" \
  369. "fdtfile=p1022ds.dtb\0" \
  370. "bdev=sda3\0" \
  371. "diuregs=md e002c000 1d\0" \
  372. "dium=mw e002c01c\0" \
  373. "diuerr=md e002c014 1\0" \
  374. "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
  375. "monitor=0-DVI\0"
  376. #define CONFIG_HDBOOT \
  377. "setenv bootargs root=/dev/$bdev rw " \
  378. "console=$consoledev,$baudrate $othbootargs;" \
  379. "tftp $loadaddr $bootfile;" \
  380. "tftp $fdtaddr $fdtfile;" \
  381. "bootm $loadaddr - $fdtaddr"
  382. #define CONFIG_NFSBOOTCOMMAND \
  383. "setenv bootargs root=/dev/nfs rw " \
  384. "nfsroot=$serverip:$rootpath " \
  385. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  386. "console=$consoledev,$baudrate $othbootargs;" \
  387. "tftp $loadaddr $bootfile;" \
  388. "tftp $fdtaddr $fdtfile;" \
  389. "bootm $loadaddr - $fdtaddr"
  390. #define CONFIG_RAMBOOTCOMMAND \
  391. "setenv bootargs root=/dev/ram rw " \
  392. "console=$consoledev,$baudrate $othbootargs;" \
  393. "tftp $ramdiskaddr $ramdiskfile;" \
  394. "tftp $loadaddr $bootfile;" \
  395. "tftp $fdtaddr $fdtfile;" \
  396. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  397. #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
  398. #endif