skxmac2.c 114 KB

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  1. /******************************************************************************
  2. *
  3. * Name: skxmac2.c
  4. * Project: GEnesis, PCI Gigabit Ethernet Adapter
  5. * Version: $Revision: 1.91 $
  6. * Date: $Date: 2003/02/05 15:09:34 $
  7. * Purpose: Contains functions to initialize the MACs and PHYs
  8. *
  9. ******************************************************************************/
  10. /******************************************************************************
  11. *
  12. * (C)Copyright 1998-2003 SysKonnect GmbH.
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * The information in this file is provided "AS IS" without warranty.
  20. *
  21. ******************************************************************************/
  22. /******************************************************************************
  23. *
  24. * History:
  25. *
  26. * $Log: skxmac2.c,v $
  27. * Revision 1.91 2003/02/05 15:09:34 rschmidt
  28. * Removed setting of 'Collision Test'-bit in SkGmInitPhyMarv().
  29. * Disabled auto-update for speed, duplex and flow-control when
  30. * auto-negotiation is not enabled (Bug Id #10766).
  31. * Editorial changes.
  32. *
  33. * Revision 1.90 2003/01/29 13:35:19 rschmidt
  34. * Increment Rx FIFO Overflow counter only in DEBUG-mode.
  35. * Corrected define for blinking active LED.
  36. *
  37. * Revision 1.89 2003/01/28 16:37:45 rschmidt
  38. * Changed init for blinking active LED
  39. *
  40. * Revision 1.88 2003/01/28 10:09:38 rschmidt
  41. * Added debug outputs in SkGmInitMac().
  42. * Added customized init of LED registers in SkGmInitPhyMarv(),
  43. * for blinking active LED (#ifdef ACT_LED_BLINK) and
  44. * for normal duplex LED (#ifdef DUP_LED_NORMAL).
  45. * Editorial changes.
  46. *
  47. * Revision 1.87 2002/12/10 14:39:05 rschmidt
  48. * Improved initialization of GPHY in SkGmInitPhyMarv().
  49. * Editorial changes.
  50. *
  51. * Revision 1.86 2002/12/09 15:01:12 rschmidt
  52. * Added setup of Ext. PHY Specific Ctrl Reg (downshift feature).
  53. *
  54. * Revision 1.85 2002/12/05 14:09:16 rschmidt
  55. * Improved avoiding endless loop in SkGmPhyWrite(), SkGmPhyWrite().
  56. * Added additional advertising for 10Base-T when 100Base-T is selected.
  57. * Added case SK_PHY_MARV_FIBER for YUKON Fiber adapter.
  58. * Editorial changes.
  59. *
  60. * Revision 1.84 2002/11/15 12:50:09 rschmidt
  61. * Changed SkGmCableDiagStatus() when getting results.
  62. *
  63. * Revision 1.83 2002/11/13 10:28:29 rschmidt
  64. * Added some typecasts to avoid compiler warnings.
  65. *
  66. * Revision 1.82 2002/11/13 09:20:46 rschmidt
  67. * Replaced for(..) with do {} while (...) in SkXmUpdateStats().
  68. * Replaced 2 macros GM_IN16() with 1 GM_IN32() in SkGmMacStatistic().
  69. * Added SkGmCableDiagStatus() for Virtual Cable Test (VCT).
  70. * Editorial changes.
  71. *
  72. * Revision 1.81 2002/10/28 14:28:08 rschmidt
  73. * Changed MAC address setup for GMAC in SkGmInitMac().
  74. * Optimized handling of counter overflow IRQ in SkGmOverflowStatus().
  75. * Editorial changes.
  76. *
  77. * Revision 1.80 2002/10/14 15:29:44 rschmidt
  78. * Corrected disabling of all PHY IRQs.
  79. * Added WA for deviation #16 (address used for pause packets).
  80. * Set Pause Mode in SkMacRxTxEnable() only for Genesis.
  81. * Added IRQ and counter for Receive FIFO Overflow in DEBUG-mode.
  82. * SkXmTimeStamp() replaced by SkMacTimeStamp().
  83. * Added clearing of GMAC Tx FIFO Underrun IRQ in SkGmIrq().
  84. * Editorial changes.
  85. *
  86. * Revision 1.79 2002/10/10 15:55:36 mkarl
  87. * changes for PLinkSpeedUsed
  88. *
  89. * Revision 1.78 2002/09/12 09:39:51 rwahl
  90. * Removed deactivate code for SIRQ overflow event separate for TX/RX.
  91. *
  92. * Revision 1.77 2002/09/09 12:26:37 mkarl
  93. * added handling for Yukon to SkXmTimeStamp
  94. *
  95. * Revision 1.76 2002/08/21 16:41:16 rschmidt
  96. * Added bit GPC_ENA_XC (Enable MDI crossover) in HWCFG_MODE.
  97. * Added forced speed settings in SkGmInitPhyMarv().
  98. * Added settings of full/half duplex capabilities for YUKON Fiber.
  99. * Editorial changes.
  100. *
  101. * Revision 1.75 2002/08/16 15:12:01 rschmidt
  102. * Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis.
  103. * Added function SkMacHashing() for ADDR-Module.
  104. * Removed functions SkXmClrSrcCheck(), SkXmClrHashAddr() (calls replaced
  105. * with macros).
  106. * Removed functions SkGmGetMuxConfig().
  107. * Added HWCFG_MODE init for YUKON Fiber.
  108. * Changed initialization of GPHY in SkGmInitPhyMarv().
  109. * Changed check of parameter in SkXmMacStatistic().
  110. * Editorial changes.
  111. *
  112. * Revision 1.74 2002/08/12 14:00:17 rschmidt
  113. * Replaced usage of Broadcom PHY Ids with defines.
  114. * Corrected error messages in SkGmMacStatistic().
  115. * Made SkMacPromiscMode() public for ADDR-Modul.
  116. * Editorial changes.
  117. *
  118. * Revision 1.73 2002/08/08 16:26:24 rschmidt
  119. * Improved reset sequence for YUKON in SkGmHardRst() and SkGmInitMac().
  120. * Replaced XMAC Rx High Watermark init value with SK_XM_RX_HI_WM.
  121. * Editorial changes.
  122. *
  123. * Revision 1.72 2002/07/24 15:11:19 rschmidt
  124. * Fixed wrong placement of parenthesis.
  125. * Editorial changes.
  126. *
  127. * Revision 1.71 2002/07/23 16:05:18 rschmidt
  128. * Added global functions for PHY: SkGePhyRead(), SkGePhyWrite().
  129. * Fixed Tx Counter Overflow IRQ (Bug ID #10730).
  130. * Editorial changes.
  131. *
  132. * Revision 1.70 2002/07/18 14:27:27 rwahl
  133. * Fixed syntax error.
  134. *
  135. * Revision 1.69 2002/07/17 17:08:47 rwahl
  136. * Fixed check in SkXmMacStatistic().
  137. *
  138. * Revision 1.68 2002/07/16 07:35:24 rwahl
  139. * Removed check for cleared mib counter in SkGmResetCounter().
  140. *
  141. * Revision 1.67 2002/07/15 18:35:56 rwahl
  142. * Added SkXmUpdateStats(), SkGmUpdateStats(), SkXmMacStatistic(),
  143. * SkGmMacStatistic(), SkXmResetCounter(), SkGmResetCounter(),
  144. * SkXmOverflowStatus(), SkGmOverflowStatus().
  145. * Changes to SkXmIrq() & SkGmIrq(): Combined SIRQ Overflow for both
  146. * RX & TX.
  147. * Changes to SkGmInitMac(): call to SkGmResetCounter().
  148. * Editorial changes.
  149. *
  150. * Revision 1.66 2002/07/15 15:59:30 rschmidt
  151. * Added PHY Address in SkXmPhyRead(), SkXmPhyWrite().
  152. * Added MIB Clear Counter in SkGmInitMac().
  153. * Added Duplex and Flow-Control settings.
  154. * Reset all Multicast filtering Hash reg. in SkGmInitMac().
  155. * Added new function: SkGmGetMuxConfig().
  156. * Editorial changes.
  157. *
  158. * Revision 1.65 2002/06/10 09:35:39 rschmidt
  159. * Replaced C++ comments (//).
  160. * Added #define VCPU around VCPUwaitTime.
  161. * Editorial changes.
  162. *
  163. * Revision 1.64 2002/06/05 08:41:10 rschmidt
  164. * Added function for XMAC2: SkXmTimeStamp().
  165. * Added function for YUKON: SkGmSetRxCmd().
  166. * Changed SkGmInitMac() resp. SkGmHardRst().
  167. * Fixed wrong variable in SkXmAutoNegLipaXmac() (debug mode).
  168. * SkXmRxTxEnable() replaced by SkMacRxTxEnable().
  169. * Editorial changes.
  170. *
  171. * Revision 1.63 2002/04/25 13:04:44 rschmidt
  172. * Changes for handling YUKON.
  173. * Use of #ifdef OTHER_PHY to eliminate code for unused Phy types.
  174. * Macros for XMAC PHY access PHY_READ(), PHY_WRITE() replaced
  175. * by functions SkXmPhyRead(), SkXmPhyWrite();
  176. * Removed use of PRxCmd to setup XMAC.
  177. * Added define PHY_B_AS_PAUSE_MSK for BCom Pause Res.
  178. * Added setting of XM_RX_DIS_CEXT in SkXmInitMac().
  179. * Removed status parameter from MAC IRQ handler SkMacIrq(),
  180. * SkXmIrq() and SkGmIrq().
  181. * SkXmAutoNegLipa...() for ext. Phy replaced by SkMacAutoNegLipaPhy().
  182. * Added SkMac...() functions to handle both XMAC and GMAC.
  183. * Added functions for YUKON: SkGmHardRst(), SkGmSoftRst(),
  184. * SkGmSetRxTxEn(), SkGmIrq(), SkGmInitMac(), SkGmInitPhyMarv(),
  185. * SkGmAutoNegDoneMarv(), SkGmPhyRead(), SkGmPhyWrite().
  186. * Changes for V-CPU support.
  187. * Editorial changes.
  188. *
  189. * Revision 1.62 2001/08/06 09:50:14 rschmidt
  190. * Workaround BCOM Errata #1 for the C5 type.
  191. * Editorial changes.
  192. *
  193. * Revision 1.61 2001/02/09 15:40:59 rassmann
  194. * Editorial changes.
  195. *
  196. * Revision 1.60 2001/02/07 15:02:01 cgoos
  197. * Added workaround for Fujitsu switch link down.
  198. *
  199. * Revision 1.59 2001/01/10 09:38:06 cgoos
  200. * Fixed Broadcom C0/A1 Id check for workaround.
  201. *
  202. * Revision 1.58 2000/11/29 11:30:38 cgoos
  203. * Changed DEBUG sections with NW output to xDEBUG
  204. *
  205. * Revision 1.57 2000/11/27 12:40:40 rassmann
  206. * Suppressing preamble after first access to BCom, not before (#10556).
  207. *
  208. * Revision 1.56 2000/11/09 12:32:48 rassmann
  209. * Renamed variables.
  210. *
  211. * Revision 1.55 2000/11/09 11:30:10 rassmann
  212. * WA: Waiting after releasing reset until BCom chip is accessible.
  213. *
  214. * Revision 1.54 2000/10/02 14:10:27 rassmann
  215. * Reading BCOM PHY after releasing reset until it returns a valid value.
  216. *
  217. * Revision 1.53 2000/07/27 12:22:11 gklug
  218. * fix: possible endless loop in XmHardRst.
  219. *
  220. * Revision 1.52 2000/05/22 08:48:31 malthoff
  221. * Fix: #10523 errata valid for all BCOM PHYs.
  222. *
  223. * Revision 1.51 2000/05/17 12:52:18 malthoff
  224. * Fixes BCom link errata (#10523).
  225. *
  226. * Revision 1.50 1999/11/22 13:40:14 cgoos
  227. * Changed license header to GPL.
  228. *
  229. * Revision 1.49 1999/11/22 08:12:13 malthoff
  230. * Add workaround for power consumption feature of BCom C0 chip.
  231. *
  232. * Revision 1.48 1999/11/16 08:39:01 malthoff
  233. * Fix: MDIO preamble suppression is port dependent.
  234. *
  235. * Revision 1.47 1999/08/27 08:55:35 malthoff
  236. * 1000BT: Optimizing MDIO transfer by oppressing MDIO preamble.
  237. *
  238. * Revision 1.46 1999/08/13 11:01:12 malthoff
  239. * Fix for 1000BT: pFlowCtrlMode was not set correctly.
  240. *
  241. * Revision 1.45 1999/08/12 19:18:28 malthoff
  242. * 1000BT Fixes: Do not owerwrite XM_MMU_CMD.
  243. * Do not execute BCOM A1 workaround for B1 chips.
  244. * Fix pause frame setting.
  245. * Always set PHY_B_AC_TX_TST in PHY_BCOM_AUX_CTRL.
  246. *
  247. * Revision 1.44 1999/08/03 15:23:48 cgoos
  248. * Fixed setting of PHY interrupt mask in half duplex mode.
  249. *
  250. * Revision 1.43 1999/08/03 15:22:17 cgoos
  251. * Added some debug output.
  252. * Disabled XMac GP0 interrupt for external PHYs.
  253. *
  254. * Revision 1.42 1999/08/02 08:39:23 malthoff
  255. * BCOM PHY: TX LED: To get the mono flop behaviour it is required
  256. * to set the LED Traffic Mode bit in PHY_BCOM_P_EXT_CTRL.
  257. *
  258. * Revision 1.41 1999/07/30 06:54:31 malthoff
  259. * Add temp. workarounds for the BCOM Phy revision A1.
  260. *
  261. * Revision 1.40 1999/06/01 07:43:26 cgoos
  262. * Changed Link Mode Status in SkXmAutoNegDone... from FULL/HALF to
  263. * AUTOFULL/AUTOHALF.
  264. *
  265. * Revision 1.39 1999/05/19 07:29:51 cgoos
  266. * Changes for 1000Base-T.
  267. *
  268. * Revision 1.38 1999/04/08 14:35:10 malthoff
  269. * Add code for enabling signal detect. Enabling signal detect is disabled.
  270. *
  271. * Revision 1.37 1999/03/12 13:42:54 malthoff
  272. * Add: Jumbo Frame Support.
  273. * Add: Receive modes SK_LENERR_OK_ON/OFF and
  274. * SK_BIG_PK_OK_ON/OFF in SkXmSetRxCmd().
  275. *
  276. * Revision 1.36 1999/03/08 10:10:55 gklug
  277. * fix: AutoSensing did switch to next mode even if LiPa indicated offline
  278. *
  279. * Revision 1.35 1999/02/22 15:16:41 malthoff
  280. * Remove some compiler warnings.
  281. *
  282. * Revision 1.34 1999/01/22 09:19:59 gklug
  283. * fix: Init DupMode and InitPauseMd are now called in RxTxEnable
  284. *
  285. * Revision 1.33 1998/12/11 15:19:11 gklug
  286. * chg: lipa autoneg stati
  287. * chg: debug messages
  288. * chg: do NOT use spurious XmIrq
  289. *
  290. * Revision 1.32 1998/12/10 11:08:44 malthoff
  291. * bug fix: pAC has been used for IOs in SkXmHardRst().
  292. * SkXmInitPhy() is also called for the Diag in SkXmInitMac().
  293. *
  294. * Revision 1.31 1998/12/10 10:39:11 gklug
  295. * fix: do 4 RESETS of the XMAC at the beginning
  296. * fix: dummy read interrupt source register BEFORE initializing the Phy
  297. * add: debug messages
  298. * fix: Linkpartners autoneg capability cannot be shown by TX_PAGE interrupt
  299. *
  300. * Revision 1.30 1998/12/07 12:18:32 gklug
  301. * add: refinement of autosense mode: take into account the autoneg cap of LiPa
  302. *
  303. * Revision 1.29 1998/12/07 07:12:29 gklug
  304. * fix: if page is received the link is down.
  305. *
  306. * Revision 1.28 1998/12/01 10:12:47 gklug
  307. * chg: if spurious IRQ from XMAC encountered, save it
  308. *
  309. * Revision 1.27 1998/11/26 07:33:38 gklug
  310. * add: InitPhy call is now in XmInit function
  311. *
  312. * Revision 1.26 1998/11/18 13:38:24 malthoff
  313. * 'Imsk' is also unused in SkXmAutoNegDone.
  314. *
  315. * Revision 1.25 1998/11/18 13:28:01 malthoff
  316. * Remove unused variable 'Reg' in SkXmAutoNegDone().
  317. *
  318. * Revision 1.24 1998/11/18 13:18:45 gklug
  319. * add: workaround for xmac errata #1
  320. * add: detect Link Down also when Link partner requested config
  321. * chg: XMIrq is only used when link is up
  322. *
  323. * Revision 1.23 1998/11/04 07:07:04 cgoos
  324. * Added function SkXmRxTxEnable.
  325. *
  326. * Revision 1.22 1998/10/30 07:35:54 gklug
  327. * fix: serve LinkDown interrupt when link is already down
  328. *
  329. * Revision 1.21 1998/10/29 15:32:03 gklug
  330. * fix: Link Down signaling
  331. *
  332. * Revision 1.20 1998/10/29 11:17:27 gklug
  333. * fix: AutoNegDone bug
  334. *
  335. * Revision 1.19 1998/10/29 10:14:43 malthoff
  336. * Add endainesss comment for reading/writing MAC addresses.
  337. *
  338. * Revision 1.18 1998/10/28 07:48:55 cgoos
  339. * Fix: ASS somtimes signaled although link is up.
  340. *
  341. * Revision 1.17 1998/10/26 07:55:39 malthoff
  342. * Fix in SkXmInitPauseMd(): Pause Mode
  343. * was disabled and not enabled.
  344. * Fix in SkXmAutoNegDone(): Checking Mode bits
  345. * always failed, becaues of some missing braces.
  346. *
  347. * Revision 1.16 1998/10/22 09:46:52 gklug
  348. * fix SysKonnectFileId typo
  349. *
  350. * Revision 1.15 1998/10/21 05:51:37 gklug
  351. * add: para DoLoop to InitPhy function for loopback set-up
  352. *
  353. * Revision 1.14 1998/10/16 10:59:23 malthoff
  354. * Remove Lint warning for dummy reads.
  355. *
  356. * Revision 1.13 1998/10/15 14:01:20 malthoff
  357. * Fix: SkXmAutoNegDone() is (int) but does not return a value.
  358. *
  359. * Revision 1.12 1998/10/14 14:45:04 malthoff
  360. * Remove SKERR_SIRQ_E0xx and SKERR_SIRQ_E0xxMSG by
  361. * SKERR_HWI_Exx and SKERR_HWI_E0xxMSG to be independent
  362. * from the Sirq module.
  363. *
  364. * Revision 1.11 1998/10/14 13:59:01 gklug
  365. * add: InitPhy function
  366. *
  367. * Revision 1.10 1998/10/14 11:20:57 malthoff
  368. * Make SkXmAutoNegDone() public, because it's
  369. * used in diagnostics, too.
  370. * The Link Up event to the RLMT is issued in SkXmIrq().
  371. * SkXmIrq() is not available in diagnostics.
  372. * Use PHY_READ when reading PHY registers.
  373. *
  374. * Revision 1.9 1998/10/14 05:50:10 cgoos
  375. * Added definition for Para.
  376. *
  377. * Revision 1.8 1998/10/14 05:41:28 gklug
  378. * add: Xmac IRQ
  379. * add: auto-negotiation done function
  380. *
  381. * Revision 1.7 1998/10/09 06:55:20 malthoff
  382. * The configuration of the XMACs Tx Request Threshold
  383. * depends from the drivers port usage now. The port
  384. * usage is configured in GIPortUsage.
  385. *
  386. * Revision 1.6 1998/10/05 07:48:00 malthoff
  387. * minor changes
  388. *
  389. * Revision 1.5 1998/10/01 07:03:54 gklug
  390. * add: dummy function for XMAC ISR
  391. *
  392. * Revision 1.4 1998/09/30 12:37:44 malthoff
  393. * Add SkXmSetRxCmd() and related code.
  394. *
  395. * Revision 1.3 1998/09/28 13:26:40 malthoff
  396. * Add SkXmInitMac(), SkXmInitDupMd(), and SkXmInitPauseMd()
  397. *
  398. * Revision 1.2 1998/09/16 14:34:21 malthoff
  399. * Add SkXmClrExactAddr(), SkXmClrSrcCheck(),
  400. * SkXmClrHashAddr(), SkXmFlushTxFifo(),
  401. * SkXmFlushRxFifo(), and SkXmHardRst().
  402. * Finish Coding of SkXmSoftRst().
  403. * The sources may be compiled now.
  404. *
  405. * Revision 1.1 1998/09/04 10:05:56 malthoff
  406. * Created.
  407. *
  408. *
  409. ******************************************************************************/
  410. #include <config.h>
  411. #include "h/skdrv1st.h"
  412. #include "h/skdrv2nd.h"
  413. /* typedefs *******************************************************************/
  414. /* BCOM PHY magic pattern list */
  415. typedef struct s_PhyHack {
  416. int PhyReg; /* Phy register */
  417. SK_U16 PhyVal; /* Value to write */
  418. } BCOM_HACK;
  419. /* local variables ************************************************************/
  420. static const char SysKonnectFileId[] =
  421. "@(#)$Id: skxmac2.c,v 1.91 2003/02/05 15:09:34 rschmidt Exp $ (C) SK ";
  422. BCOM_HACK BcomRegA1Hack[] = {
  423. { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
  424. { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
  425. { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
  426. { 0, 0 }
  427. };
  428. BCOM_HACK BcomRegC0Hack[] = {
  429. { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, { 0x17, 0x0013 },
  430. { 0x15, 0x0A04 }, { 0x18, 0x0420 },
  431. { 0, 0 }
  432. };
  433. /* function prototypes ********************************************************/
  434. static void SkXmInitPhyXmac(SK_AC*, SK_IOC, int, SK_BOOL);
  435. static void SkXmInitPhyBcom(SK_AC*, SK_IOC, int, SK_BOOL);
  436. static void SkGmInitPhyMarv(SK_AC*, SK_IOC, int, SK_BOOL);
  437. static int SkXmAutoNegDoneXmac(SK_AC*, SK_IOC, int);
  438. static int SkXmAutoNegDoneBcom(SK_AC*, SK_IOC, int);
  439. static int SkGmAutoNegDoneMarv(SK_AC*, SK_IOC, int);
  440. #ifdef OTHER_PHY
  441. static void SkXmInitPhyLone(SK_AC*, SK_IOC, int, SK_BOOL);
  442. static void SkXmInitPhyNat (SK_AC*, SK_IOC, int, SK_BOOL);
  443. static int SkXmAutoNegDoneLone(SK_AC*, SK_IOC, int);
  444. static int SkXmAutoNegDoneNat (SK_AC*, SK_IOC, int);
  445. #endif /* OTHER_PHY */
  446. /******************************************************************************
  447. *
  448. * SkXmPhyRead() - Read from XMAC PHY register
  449. *
  450. * Description: reads a 16-bit word from XMAC PHY or ext. PHY
  451. *
  452. * Returns:
  453. * nothing
  454. */
  455. void SkXmPhyRead(
  456. SK_AC *pAC, /* Adapter Context */
  457. SK_IOC IoC, /* I/O Context */
  458. int Port, /* Port Index (MAC_1 + n) */
  459. int PhyReg, /* Register Address (Offset) */
  460. SK_U16 *pVal) /* Pointer to Value */
  461. {
  462. SK_U16 Mmu;
  463. SK_GEPORT *pPrt;
  464. pPrt = &pAC->GIni.GP[Port];
  465. /* write the PHY register's address */
  466. XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
  467. /* get the PHY register's value */
  468. XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
  469. if (pPrt->PhyType != SK_PHY_XMAC) {
  470. do {
  471. XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
  472. /* wait until 'Ready' is set */
  473. } while ((Mmu & XM_MMU_PHY_RDY) == 0);
  474. /* get the PHY register's value */
  475. XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
  476. }
  477. } /* SkXmPhyRead */
  478. /******************************************************************************
  479. *
  480. * SkXmPhyWrite() - Write to XMAC PHY register
  481. *
  482. * Description: writes a 16-bit word to XMAC PHY or ext. PHY
  483. *
  484. * Returns:
  485. * nothing
  486. */
  487. void SkXmPhyWrite(
  488. SK_AC *pAC, /* Adapter Context */
  489. SK_IOC IoC, /* I/O Context */
  490. int Port, /* Port Index (MAC_1 + n) */
  491. int PhyReg, /* Register Address (Offset) */
  492. SK_U16 Val) /* Value */
  493. {
  494. SK_U16 Mmu;
  495. SK_GEPORT *pPrt;
  496. pPrt = &pAC->GIni.GP[Port];
  497. if (pPrt->PhyType != SK_PHY_XMAC) {
  498. do {
  499. XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
  500. /* wait until 'Busy' is cleared */
  501. } while ((Mmu & XM_MMU_PHY_BUSY) != 0);
  502. }
  503. /* write the PHY register's address */
  504. XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
  505. /* write the PHY register's value */
  506. XM_OUT16(IoC, Port, XM_PHY_DATA, Val);
  507. if (pPrt->PhyType != SK_PHY_XMAC) {
  508. do {
  509. XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
  510. /* wait until 'Busy' is cleared */
  511. } while ((Mmu & XM_MMU_PHY_BUSY) != 0);
  512. }
  513. } /* SkXmPhyWrite */
  514. /******************************************************************************
  515. *
  516. * SkGmPhyRead() - Read from GPHY register
  517. *
  518. * Description: reads a 16-bit word from GPHY through MDIO
  519. *
  520. * Returns:
  521. * nothing
  522. */
  523. void SkGmPhyRead(
  524. SK_AC *pAC, /* Adapter Context */
  525. SK_IOC IoC, /* I/O Context */
  526. int Port, /* Port Index (MAC_1 + n) */
  527. int PhyReg, /* Register Address (Offset) */
  528. SK_U16 *pVal) /* Pointer to Value */
  529. {
  530. SK_U16 Ctrl;
  531. SK_GEPORT *pPrt;
  532. #ifdef VCPU
  533. u_long SimCyle;
  534. u_long SimLowTime;
  535. VCPUgetTime(&SimCyle, &SimLowTime);
  536. VCPUprintf(0, "SkGmPhyRead(%u), SimCyle=%u, SimLowTime=%u\n",
  537. PhyReg, SimCyle, SimLowTime);
  538. #endif /* VCPU */
  539. pPrt = &pAC->GIni.GP[Port];
  540. /* set PHY-Register offset and 'Read' OpCode (= 1) */
  541. *pVal = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
  542. GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD);
  543. GM_OUT16(IoC, Port, GM_SMI_CTRL, *pVal);
  544. GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
  545. /* additional check for MDC/MDIO activity */
  546. if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
  547. *pVal = 0;
  548. return;
  549. }
  550. *pVal |= GM_SMI_CT_BUSY;
  551. do {
  552. #ifdef VCPU
  553. VCPUwaitTime(1000);
  554. #endif /* VCPU */
  555. GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
  556. /* wait until 'ReadValid' is set */
  557. } while (Ctrl == *pVal);
  558. /* get the PHY register's value */
  559. GM_IN16(IoC, Port, GM_SMI_DATA, pVal);
  560. #ifdef VCPU
  561. VCPUgetTime(&SimCyle, &SimLowTime);
  562. VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
  563. SimCyle, SimLowTime);
  564. #endif /* VCPU */
  565. } /* SkGmPhyRead */
  566. /******************************************************************************
  567. *
  568. * SkGmPhyWrite() - Write to GPHY register
  569. *
  570. * Description: writes a 16-bit word to GPHY through MDIO
  571. *
  572. * Returns:
  573. * nothing
  574. */
  575. void SkGmPhyWrite(
  576. SK_AC *pAC, /* Adapter Context */
  577. SK_IOC IoC, /* I/O Context */
  578. int Port, /* Port Index (MAC_1 + n) */
  579. int PhyReg, /* Register Address (Offset) */
  580. SK_U16 Val) /* Value */
  581. {
  582. SK_U16 Ctrl;
  583. SK_GEPORT *pPrt;
  584. #ifdef VCPU
  585. SK_U32 DWord;
  586. u_long SimCyle;
  587. u_long SimLowTime;
  588. VCPUgetTime(&SimCyle, &SimLowTime);
  589. VCPUprintf(0, "SkGmPhyWrite(Reg=%u, Val=0x%04x), SimCyle=%u, SimLowTime=%u\n",
  590. PhyReg, Val, SimCyle, SimLowTime);
  591. #endif /* VCPU */
  592. pPrt = &pAC->GIni.GP[Port];
  593. /* write the PHY register's value */
  594. GM_OUT16(IoC, Port, GM_SMI_DATA, Val);
  595. /* set PHY-Register offset and 'Write' OpCode (= 0) */
  596. Val = GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg);
  597. GM_OUT16(IoC, Port, GM_SMI_CTRL, Val);
  598. GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
  599. /* additional check for MDC/MDIO activity */
  600. if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
  601. return;
  602. }
  603. Val |= GM_SMI_CT_BUSY;
  604. do {
  605. #ifdef VCPU
  606. /* read Timer value */
  607. SK_IN32(IoC, B2_TI_VAL, &DWord);
  608. VCPUwaitTime(1000);
  609. #endif /* VCPU */
  610. GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
  611. /* wait until 'Busy' is cleared */
  612. } while (Ctrl == Val);
  613. #ifdef VCPU
  614. VCPUgetTime(&SimCyle, &SimLowTime);
  615. VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
  616. SimCyle, SimLowTime);
  617. #endif /* VCPU */
  618. } /* SkGmPhyWrite */
  619. /******************************************************************************
  620. *
  621. * SkGePhyRead() - Read from PHY register
  622. *
  623. * Description: calls a read PHY routine dep. on board type
  624. *
  625. * Returns:
  626. * nothing
  627. */
  628. void SkGePhyRead(
  629. SK_AC *pAC, /* Adapter Context */
  630. SK_IOC IoC, /* I/O Context */
  631. int Port, /* Port Index (MAC_1 + n) */
  632. int PhyReg, /* Register Address (Offset) */
  633. SK_U16 *pVal) /* Pointer to Value */
  634. {
  635. void (*r_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 *pVal);
  636. if (pAC->GIni.GIGenesis) {
  637. r_func = SkXmPhyRead;
  638. }
  639. else {
  640. r_func = SkGmPhyRead;
  641. }
  642. r_func(pAC, IoC, Port, PhyReg, pVal);
  643. } /* SkGePhyRead */
  644. /******************************************************************************
  645. *
  646. * SkGePhyWrite() - Write to PHY register
  647. *
  648. * Description: calls a write PHY routine dep. on board type
  649. *
  650. * Returns:
  651. * nothing
  652. */
  653. void SkGePhyWrite(
  654. SK_AC *pAC, /* Adapter Context */
  655. SK_IOC IoC, /* I/O Context */
  656. int Port, /* Port Index (MAC_1 + n) */
  657. int PhyReg, /* Register Address (Offset) */
  658. SK_U16 Val) /* Value */
  659. {
  660. void (*w_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 Val);
  661. if (pAC->GIni.GIGenesis) {
  662. w_func = SkXmPhyWrite;
  663. }
  664. else {
  665. w_func = SkGmPhyWrite;
  666. }
  667. w_func(pAC, IoC, Port, PhyReg, Val);
  668. } /* SkGePhyWrite */
  669. /******************************************************************************
  670. *
  671. * SkMacPromiscMode() - Enable / Disable Promiscuous Mode
  672. *
  673. * Description:
  674. * enables / disables promiscuous mode by setting Mode Register (XMAC) or
  675. * Receive Control Register (GMAC) dep. on board type
  676. *
  677. * Returns:
  678. * nothing
  679. */
  680. void SkMacPromiscMode(
  681. SK_AC *pAC, /* adapter context */
  682. SK_IOC IoC, /* IO context */
  683. int Port, /* Port Index (MAC_1 + n) */
  684. SK_BOOL Enable) /* Enable / Disable */
  685. {
  686. SK_U16 RcReg;
  687. SK_U32 MdReg;
  688. SK_U32 *pMdReg = &MdReg;
  689. if (pAC->GIni.GIGenesis) {
  690. XM_IN32(IoC, Port, XM_MODE, pMdReg);
  691. /* enable or disable promiscuous mode */
  692. if (Enable) {
  693. MdReg |= XM_MD_ENA_PROM;
  694. }
  695. else {
  696. MdReg &= ~XM_MD_ENA_PROM;
  697. }
  698. /* setup Mode Register */
  699. XM_OUT32(IoC, Port, XM_MODE, MdReg);
  700. }
  701. else {
  702. GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
  703. /* enable or disable unicast and multicast filtering */
  704. if (Enable) {
  705. RcReg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  706. }
  707. else {
  708. RcReg |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  709. }
  710. /* setup Receive Control Register */
  711. GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg);
  712. }
  713. } /* SkMacPromiscMode*/
  714. /******************************************************************************
  715. *
  716. * SkMacHashing() - Enable / Disable Hashing
  717. *
  718. * Description:
  719. * enables / disables hashing by setting Mode Register (XMAC) or
  720. * Receive Control Register (GMAC) dep. on board type
  721. *
  722. * Returns:
  723. * nothing
  724. */
  725. void SkMacHashing(
  726. SK_AC *pAC, /* adapter context */
  727. SK_IOC IoC, /* IO context */
  728. int Port, /* Port Index (MAC_1 + n) */
  729. SK_BOOL Enable) /* Enable / Disable */
  730. {
  731. SK_U16 RcReg;
  732. SK_U32 MdReg;
  733. SK_U32 *pMdReg = &MdReg;
  734. if (pAC->GIni.GIGenesis) {
  735. XM_IN32(IoC, Port, XM_MODE, pMdReg);
  736. /* enable or disable hashing */
  737. if (Enable) {
  738. MdReg |= XM_MD_ENA_HASH;
  739. }
  740. else {
  741. MdReg &= ~XM_MD_ENA_HASH;
  742. }
  743. /* setup Mode Register */
  744. XM_OUT32(IoC, Port, XM_MODE, MdReg);
  745. }
  746. else {
  747. GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
  748. /* enable or disable multicast filtering */
  749. if (Enable) {
  750. RcReg |= GM_RXCR_MCF_ENA;
  751. }
  752. else {
  753. RcReg &= ~GM_RXCR_MCF_ENA;
  754. }
  755. /* setup Receive Control Register */
  756. GM_OUT16(IoC, Port, GM_RX_CTRL, RcReg);
  757. }
  758. } /* SkMacHashing*/
  759. #ifdef SK_DIAG
  760. /******************************************************************************
  761. *
  762. * SkXmSetRxCmd() - Modify the value of the XMAC's Rx Command Register
  763. *
  764. * Description:
  765. * The features
  766. * - FCS stripping, SK_STRIP_FCS_ON/OFF
  767. * - pad byte stripping, SK_STRIP_PAD_ON/OFF
  768. * - don't set XMR_FS_ERR in status SK_LENERR_OK_ON/OFF
  769. * for inrange length error frames
  770. * - don't set XMR_FS_ERR in status SK_BIG_PK_OK_ON/OFF
  771. * for frames > 1514 bytes
  772. * - enable Rx of own packets SK_SELF_RX_ON/OFF
  773. *
  774. * for incoming packets may be enabled/disabled by this function.
  775. * Additional modes may be added later.
  776. * Multiple modes can be enabled/disabled at the same time.
  777. * The new configuration is written to the Rx Command register immediately.
  778. *
  779. * Returns:
  780. * nothing
  781. */
  782. static void SkXmSetRxCmd(
  783. SK_AC *pAC, /* adapter context */
  784. SK_IOC IoC, /* IO context */
  785. int Port, /* Port Index (MAC_1 + n) */
  786. int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
  787. SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
  788. {
  789. SK_U16 OldRxCmd;
  790. SK_U16 RxCmd;
  791. XM_IN16(IoC, Port, XM_RX_CMD, &OldRxCmd);
  792. RxCmd = OldRxCmd;
  793. switch (Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) {
  794. case SK_STRIP_FCS_ON:
  795. RxCmd |= XM_RX_STRIP_FCS;
  796. break;
  797. case SK_STRIP_FCS_OFF:
  798. RxCmd &= ~XM_RX_STRIP_FCS;
  799. break;
  800. }
  801. switch (Mode & (SK_STRIP_PAD_ON | SK_STRIP_PAD_OFF)) {
  802. case SK_STRIP_PAD_ON:
  803. RxCmd |= XM_RX_STRIP_PAD;
  804. break;
  805. case SK_STRIP_PAD_OFF:
  806. RxCmd &= ~XM_RX_STRIP_PAD;
  807. break;
  808. }
  809. switch (Mode & (SK_LENERR_OK_ON | SK_LENERR_OK_OFF)) {
  810. case SK_LENERR_OK_ON:
  811. RxCmd |= XM_RX_LENERR_OK;
  812. break;
  813. case SK_LENERR_OK_OFF:
  814. RxCmd &= ~XM_RX_LENERR_OK;
  815. break;
  816. }
  817. switch (Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) {
  818. case SK_BIG_PK_OK_ON:
  819. RxCmd |= XM_RX_BIG_PK_OK;
  820. break;
  821. case SK_BIG_PK_OK_OFF:
  822. RxCmd &= ~XM_RX_BIG_PK_OK;
  823. break;
  824. }
  825. switch (Mode & (SK_SELF_RX_ON | SK_SELF_RX_OFF)) {
  826. case SK_SELF_RX_ON:
  827. RxCmd |= XM_RX_SELF_RX;
  828. break;
  829. case SK_SELF_RX_OFF:
  830. RxCmd &= ~XM_RX_SELF_RX;
  831. break;
  832. }
  833. /* Write the new mode to the Rx command register if required */
  834. if (OldRxCmd != RxCmd) {
  835. XM_OUT16(IoC, Port, XM_RX_CMD, RxCmd);
  836. }
  837. } /* SkXmSetRxCmd */
  838. /******************************************************************************
  839. *
  840. * SkGmSetRxCmd() - Modify the value of the GMAC's Rx Control Register
  841. *
  842. * Description:
  843. * The features
  844. * - FCS (CRC) stripping, SK_STRIP_FCS_ON/OFF
  845. * - don't set GMR_FS_LONG_ERR SK_BIG_PK_OK_ON/OFF
  846. * for frames > 1514 bytes
  847. * - enable Rx of own packets SK_SELF_RX_ON/OFF
  848. *
  849. * for incoming packets may be enabled/disabled by this function.
  850. * Additional modes may be added later.
  851. * Multiple modes can be enabled/disabled at the same time.
  852. * The new configuration is written to the Rx Command register immediately.
  853. *
  854. * Returns:
  855. * nothing
  856. */
  857. static void SkGmSetRxCmd(
  858. SK_AC *pAC, /* adapter context */
  859. SK_IOC IoC, /* IO context */
  860. int Port, /* Port Index (MAC_1 + n) */
  861. int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
  862. SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
  863. {
  864. SK_U16 OldRxCmd;
  865. SK_U16 RxCmd;
  866. if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) {
  867. GM_IN16(IoC, Port, GM_RX_CTRL, &OldRxCmd);
  868. RxCmd = OldRxCmd;
  869. if ((Mode & SK_STRIP_FCS_ON) != 0) {
  870. RxCmd |= GM_RXCR_CRC_DIS;
  871. }
  872. else {
  873. RxCmd &= ~GM_RXCR_CRC_DIS;
  874. }
  875. /* Write the new mode to the Rx control register if required */
  876. if (OldRxCmd != RxCmd) {
  877. GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);
  878. }
  879. }
  880. if ((Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) != 0) {
  881. GM_IN16(IoC, Port, GM_SERIAL_MODE, &OldRxCmd);
  882. RxCmd = OldRxCmd;
  883. if ((Mode & SK_BIG_PK_OK_ON) != 0) {
  884. RxCmd |= GM_SMOD_JUMBO_ENA;
  885. }
  886. else {
  887. RxCmd &= ~GM_SMOD_JUMBO_ENA;
  888. }
  889. /* Write the new mode to the Rx control register if required */
  890. if (OldRxCmd != RxCmd) {
  891. GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd);
  892. }
  893. }
  894. } /* SkGmSetRxCmd */
  895. /******************************************************************************
  896. *
  897. * SkMacSetRxCmd() - Modify the value of the MAC's Rx Control Register
  898. *
  899. * Description: modifies the MAC's Rx Control reg. dep. on board type
  900. *
  901. * Returns:
  902. * nothing
  903. */
  904. void SkMacSetRxCmd(
  905. SK_AC *pAC, /* adapter context */
  906. SK_IOC IoC, /* IO context */
  907. int Port, /* Port Index (MAC_1 + n) */
  908. int Mode) /* Rx Mode */
  909. {
  910. if (pAC->GIni.GIGenesis) {
  911. SkXmSetRxCmd(pAC, IoC, Port, Mode);
  912. }
  913. else {
  914. SkGmSetRxCmd(pAC, IoC, Port, Mode);
  915. }
  916. } /* SkMacSetRxCmd */
  917. /******************************************************************************
  918. *
  919. * SkMacCrcGener() - Enable / Disable CRC Generation
  920. *
  921. * Description: enables / disables CRC generation dep. on board type
  922. *
  923. * Returns:
  924. * nothing
  925. */
  926. void SkMacCrcGener(
  927. SK_AC *pAC, /* adapter context */
  928. SK_IOC IoC, /* IO context */
  929. int Port, /* Port Index (MAC_1 + n) */
  930. SK_BOOL Enable) /* Enable / Disable */
  931. {
  932. SK_U16 Word;
  933. if (pAC->GIni.GIGenesis) {
  934. XM_IN16(IoC, Port, XM_TX_CMD, &Word);
  935. if (Enable) {
  936. Word &= ~XM_TX_NO_CRC;
  937. }
  938. else {
  939. Word |= XM_TX_NO_CRC;
  940. }
  941. /* setup Tx Command Register */
  942. XM_OUT16(pAC, Port, XM_TX_CMD, Word);
  943. }
  944. else {
  945. GM_IN16(IoC, Port, GM_TX_CTRL, &Word);
  946. if (Enable) {
  947. Word &= ~GM_TXCR_CRC_DIS;
  948. }
  949. else {
  950. Word |= GM_TXCR_CRC_DIS;
  951. }
  952. /* setup Tx Control Register */
  953. GM_OUT16(IoC, Port, GM_TX_CTRL, Word);
  954. }
  955. } /* SkMacCrcGener*/
  956. #endif /* SK_DIAG */
  957. /******************************************************************************
  958. *
  959. * SkXmClrExactAddr() - Clear Exact Match Address Registers
  960. *
  961. * Description:
  962. * All Exact Match Address registers of the XMAC 'Port' will be
  963. * cleared starting with 'StartNum' up to (and including) the
  964. * Exact Match address number of 'StopNum'.
  965. *
  966. * Returns:
  967. * nothing
  968. */
  969. void SkXmClrExactAddr(
  970. SK_AC *pAC, /* adapter context */
  971. SK_IOC IoC, /* IO context */
  972. int Port, /* Port Index (MAC_1 + n) */
  973. int StartNum, /* Begin with this Address Register Index (0..15) */
  974. int StopNum) /* Stop after finished with this Register Idx (0..15) */
  975. {
  976. int i;
  977. SK_U16 ZeroAddr[3] = {0x0000, 0x0000, 0x0000};
  978. if ((unsigned)StartNum > 15 || (unsigned)StopNum > 15 ||
  979. StartNum > StopNum) {
  980. SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E001, SKERR_HWI_E001MSG);
  981. return;
  982. }
  983. for (i = StartNum; i <= StopNum; i++) {
  984. XM_OUTADDR(IoC, Port, XM_EXM(i), &ZeroAddr[0]);
  985. }
  986. } /* SkXmClrExactAddr */
  987. /******************************************************************************
  988. *
  989. * SkMacFlushTxFifo() - Flush the MAC's transmit FIFO
  990. *
  991. * Description:
  992. * Flush the transmit FIFO of the MAC specified by the index 'Port'
  993. *
  994. * Returns:
  995. * nothing
  996. */
  997. void SkMacFlushTxFifo(
  998. SK_AC *pAC, /* adapter context */
  999. SK_IOC IoC, /* IO context */
  1000. int Port) /* Port Index (MAC_1 + n) */
  1001. {
  1002. SK_U32 MdReg;
  1003. SK_U32 *pMdReg = &MdReg;
  1004. if (pAC->GIni.GIGenesis) {
  1005. XM_IN32(IoC, Port, XM_MODE, pMdReg);
  1006. XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FTF);
  1007. }
  1008. else {
  1009. /* no way to flush the FIFO we have to issue a reset */
  1010. /* TBD */
  1011. }
  1012. } /* SkMacFlushTxFifo */
  1013. /******************************************************************************
  1014. *
  1015. * SkMacFlushRxFifo() - Flush the MAC's receive FIFO
  1016. *
  1017. * Description:
  1018. * Flush the receive FIFO of the MAC specified by the index 'Port'
  1019. *
  1020. * Returns:
  1021. * nothing
  1022. */
  1023. void SkMacFlushRxFifo(
  1024. SK_AC *pAC, /* adapter context */
  1025. SK_IOC IoC, /* IO context */
  1026. int Port) /* Port Index (MAC_1 + n) */
  1027. {
  1028. SK_U32 MdReg;
  1029. SK_U32 *pMdReg = &MdReg;
  1030. if (pAC->GIni.GIGenesis) {
  1031. XM_IN32(IoC, Port, XM_MODE, pMdReg);
  1032. XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FRF);
  1033. }
  1034. else {
  1035. /* no way to flush the FIFO we have to issue a reset */
  1036. /* TBD */
  1037. }
  1038. } /* SkMacFlushRxFifo */
  1039. /******************************************************************************
  1040. *
  1041. * SkXmSoftRst() - Do a XMAC software reset
  1042. *
  1043. * Description:
  1044. * The PHY registers should not be destroyed during this
  1045. * kind of software reset. Therefore the XMAC Software Reset
  1046. * (XM_GP_RES_MAC bit in XM_GP_PORT) must not be used!
  1047. *
  1048. * The software reset is done by
  1049. * - disabling the Rx and Tx state machine,
  1050. * - resetting the statistics module,
  1051. * - clear all other significant XMAC Mode,
  1052. * Command, and Control Registers
  1053. * - clearing the Hash Register and the
  1054. * Exact Match Address registers, and
  1055. * - flushing the XMAC's Rx and Tx FIFOs.
  1056. *
  1057. * Note:
  1058. * Another requirement when stopping the XMAC is to
  1059. * avoid sending corrupted frames on the network.
  1060. * Disabling the Tx state machine will NOT interrupt
  1061. * the currently transmitted frame. But we must take care
  1062. * that the Tx FIFO is cleared AFTER the current frame
  1063. * is complete sent to the network.
  1064. *
  1065. * It takes about 12ns to send a frame with 1538 bytes.
  1066. * One PCI clock goes at least 15ns (66MHz). Therefore
  1067. * after reading XM_GP_PORT back, we are sure that the
  1068. * transmitter is disabled AND idle. And this means
  1069. * we may flush the transmit FIFO now.
  1070. *
  1071. * Returns:
  1072. * nothing
  1073. */
  1074. static void SkXmSoftRst(
  1075. SK_AC *pAC, /* adapter context */
  1076. SK_IOC IoC, /* IO context */
  1077. int Port) /* Port Index (MAC_1 + n) */
  1078. {
  1079. SK_U16 ZeroAddr[4] = {0x0000, 0x0000, 0x0000, 0x0000};
  1080. /* reset the statistics module */
  1081. XM_OUT32(IoC, Port, XM_GP_PORT, XM_GP_RES_STAT);
  1082. /* disable all XMAC IRQs */
  1083. XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
  1084. XM_OUT32(IoC, Port, XM_MODE, 0); /* clear Mode Reg */
  1085. XM_OUT16(IoC, Port, XM_TX_CMD, 0); /* reset TX CMD Reg */
  1086. XM_OUT16(IoC, Port, XM_RX_CMD, 0); /* reset RX CMD Reg */
  1087. /* disable all PHY IRQs */
  1088. switch (pAC->GIni.GP[Port].PhyType) {
  1089. case SK_PHY_BCOM:
  1090. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, 0xffff);
  1091. break;
  1092. #ifdef OTHER_PHY
  1093. case SK_PHY_LONE:
  1094. SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_INT_ENAB, 0);
  1095. break;
  1096. case SK_PHY_NAT:
  1097. /* todo: National
  1098. SkXmPhyWrite(pAC, IoC, Port, PHY_NAT_INT_MASK, 0xffff); */
  1099. break;
  1100. #endif /* OTHER_PHY */
  1101. }
  1102. /* clear the Hash Register */
  1103. XM_OUTHASH(IoC, Port, XM_HSM, &ZeroAddr);
  1104. /* clear the Exact Match Address registers */
  1105. SkXmClrExactAddr(pAC, IoC, Port, 0, 15);
  1106. /* clear the Source Check Address registers */
  1107. XM_OUTHASH(IoC, Port, XM_SRC_CHK, &ZeroAddr);
  1108. } /* SkXmSoftRst */
  1109. /******************************************************************************
  1110. *
  1111. * SkXmHardRst() - Do a XMAC hardware reset
  1112. *
  1113. * Description:
  1114. * The XMAC of the specified 'Port' and all connected devices
  1115. * (PHY and SERDES) will receive a reset signal on its *Reset pins.
  1116. * External PHYs must be reset be clearing a bit in the GPIO register
  1117. * (Timing requirements: Broadcom: 400ns, Level One: none, National: 80ns).
  1118. *
  1119. * ATTENTION:
  1120. * It is absolutely necessary to reset the SW_RST Bit first
  1121. * before calling this function.
  1122. *
  1123. * Returns:
  1124. * nothing
  1125. */
  1126. static void SkXmHardRst(
  1127. SK_AC *pAC, /* adapter context */
  1128. SK_IOC IoC, /* IO context */
  1129. int Port) /* Port Index (MAC_1 + n) */
  1130. {
  1131. SK_U32 Reg;
  1132. int i;
  1133. int TOut;
  1134. SK_U16 Word;
  1135. for (i = 0; i < 4; i++) {
  1136. /* TX_MFF_CTRL1 has 32 bits, but only the lowest 16 bits are used */
  1137. SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
  1138. TOut = 0;
  1139. do {
  1140. if (TOut++ > 10000) {
  1141. /*
  1142. * Adapter seems to be in RESET state.
  1143. * Registers cannot be written.
  1144. */
  1145. return;
  1146. }
  1147. SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
  1148. SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &Word);
  1149. } while ((Word & MFF_SET_MAC_RST) == 0);
  1150. }
  1151. /* For external PHYs there must be special handling */
  1152. if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) {
  1153. /* reset external PHY */
  1154. SK_IN32(IoC, B2_GP_IO, &Reg);
  1155. if (Port == 0) {
  1156. Reg |= GP_DIR_0; /* set to output */
  1157. Reg &= ~GP_IO_0;
  1158. }
  1159. else {
  1160. Reg |= GP_DIR_2; /* set to output */
  1161. Reg &= ~GP_IO_2;
  1162. }
  1163. SK_OUT32(IoC, B2_GP_IO, Reg);
  1164. /* short delay */
  1165. SK_IN32(IoC, B2_GP_IO, &Reg);
  1166. }
  1167. } /* SkXmHardRst */
  1168. /******************************************************************************
  1169. *
  1170. * SkGmSoftRst() - Do a GMAC software reset
  1171. *
  1172. * Description:
  1173. * The GPHY registers should not be destroyed during this
  1174. * kind of software reset.
  1175. *
  1176. * Returns:
  1177. * nothing
  1178. */
  1179. static void SkGmSoftRst(
  1180. SK_AC *pAC, /* adapter context */
  1181. SK_IOC IoC, /* IO context */
  1182. int Port) /* Port Index (MAC_1 + n) */
  1183. {
  1184. SK_U16 EmptyHash[4] = {0x0000, 0x0000, 0x0000, 0x0000};
  1185. SK_U16 RxCtrl;
  1186. /* reset the statistics module */
  1187. /* disable all GMAC IRQs */
  1188. SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
  1189. /* disable all PHY IRQs */
  1190. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
  1191. /* clear the Hash Register */
  1192. GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash);
  1193. /* Enable Unicast and Multicast filtering */
  1194. GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
  1195. GM_OUT16(IoC, Port, GM_RX_CTRL,
  1196. RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
  1197. } /* SkGmSoftRst */
  1198. /******************************************************************************
  1199. *
  1200. * SkGmHardRst() - Do a GMAC hardware reset
  1201. *
  1202. * Description:
  1203. *
  1204. * ATTENTION:
  1205. * It is absolutely necessary to reset the SW_RST Bit first
  1206. * before calling this function.
  1207. *
  1208. * Returns:
  1209. * nothing
  1210. */
  1211. static void SkGmHardRst(
  1212. SK_AC *pAC, /* adapter context */
  1213. SK_IOC IoC, /* IO context */
  1214. int Port) /* Port Index (MAC_1 + n) */
  1215. {
  1216. /* set GPHY Control reset */
  1217. SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET);
  1218. /* set GMAC Control reset */
  1219. SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
  1220. } /* SkGmHardRst */
  1221. /******************************************************************************
  1222. *
  1223. * SkMacSoftRst() - Do a MAC software reset
  1224. *
  1225. * Description: calls a MAC software reset routine dep. on board type
  1226. *
  1227. * Returns:
  1228. * nothing
  1229. */
  1230. void SkMacSoftRst(
  1231. SK_AC *pAC, /* adapter context */
  1232. SK_IOC IoC, /* IO context */
  1233. int Port) /* Port Index (MAC_1 + n) */
  1234. {
  1235. SK_GEPORT *pPrt;
  1236. pPrt = &pAC->GIni.GP[Port];
  1237. /* disable receiver and transmitter */
  1238. SkMacRxTxDisable(pAC, IoC, Port);
  1239. if (pAC->GIni.GIGenesis) {
  1240. SkXmSoftRst(pAC, IoC, Port);
  1241. }
  1242. else {
  1243. SkGmSoftRst(pAC, IoC, Port);
  1244. }
  1245. /* flush the MAC's Rx and Tx FIFOs */
  1246. SkMacFlushTxFifo(pAC, IoC, Port);
  1247. SkMacFlushRxFifo(pAC, IoC, Port);
  1248. pPrt->PState = SK_PRT_STOP;
  1249. } /* SkMacSoftRst */
  1250. /******************************************************************************
  1251. *
  1252. * SkMacHardRst() - Do a MAC hardware reset
  1253. *
  1254. * Description: calls a MAC hardware reset routine dep. on board type
  1255. *
  1256. * Returns:
  1257. * nothing
  1258. */
  1259. void SkMacHardRst(
  1260. SK_AC *pAC, /* adapter context */
  1261. SK_IOC IoC, /* IO context */
  1262. int Port) /* Port Index (MAC_1 + n) */
  1263. {
  1264. if (pAC->GIni.GIGenesis) {
  1265. SkXmHardRst(pAC, IoC, Port);
  1266. }
  1267. else {
  1268. SkGmHardRst(pAC, IoC, Port);
  1269. }
  1270. pAC->GIni.GP[Port].PState = SK_PRT_RESET;
  1271. } /* SkMacHardRst */
  1272. /******************************************************************************
  1273. *
  1274. * SkXmInitMac() - Initialize the XMAC II
  1275. *
  1276. * Description:
  1277. * Initialize the XMAC of the specified port.
  1278. * The XMAC must be reset or stopped before calling this function.
  1279. *
  1280. * Note:
  1281. * The XMAC's Rx and Tx state machine is still disabled when returning.
  1282. *
  1283. * Returns:
  1284. * nothing
  1285. */
  1286. void SkXmInitMac(
  1287. SK_AC *pAC, /* adapter context */
  1288. SK_IOC IoC, /* IO context */
  1289. int Port) /* Port Index (MAC_1 + n) */
  1290. {
  1291. SK_GEPORT *pPrt;
  1292. SK_U32 Reg;
  1293. int i;
  1294. SK_U16 SWord;
  1295. pPrt = &pAC->GIni.GP[Port];
  1296. if (pPrt->PState == SK_PRT_STOP) {
  1297. /* Port State: SK_PRT_STOP */
  1298. /* Verify that the reset bit is cleared */
  1299. SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord);
  1300. if ((SWord & MFF_SET_MAC_RST) != 0) {
  1301. /* PState does not match HW state */
  1302. SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
  1303. /* Correct it */
  1304. pPrt->PState = SK_PRT_RESET;
  1305. }
  1306. }
  1307. if (pPrt->PState == SK_PRT_RESET) {
  1308. /*
  1309. * clear HW reset
  1310. * Note: The SW reset is self clearing, therefore there is
  1311. * nothing to do here.
  1312. */
  1313. SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
  1314. /* Ensure that XMAC reset release is done (errata from LReinbold?) */
  1315. SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord);
  1316. /* Clear PHY reset */
  1317. if (pPrt->PhyType != SK_PHY_XMAC) {
  1318. SK_IN32(IoC, B2_GP_IO, &Reg);
  1319. if (Port == 0) {
  1320. Reg |= (GP_DIR_0 | GP_IO_0); /* set to output */
  1321. }
  1322. else {
  1323. Reg |= (GP_DIR_2 | GP_IO_2); /* set to output */
  1324. }
  1325. SK_OUT32(IoC, B2_GP_IO, Reg);
  1326. /* Enable GMII interface */
  1327. XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_GMII_MD);
  1328. /* read Id from external PHY (all have the same address) */
  1329. SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_ID1, &pPrt->PhyId1);
  1330. /*
  1331. * Optimize MDIO transfer by suppressing preamble.
  1332. * Must be done AFTER first access to BCOM chip.
  1333. */
  1334. XM_IN16(IoC, Port, XM_MMU_CMD, &SWord);
  1335. XM_OUT16(IoC, Port, XM_MMU_CMD, SWord | XM_MMU_NO_PRE);
  1336. if (pPrt->PhyId1 == PHY_BCOM_ID1_C0) {
  1337. /*
  1338. * Workaround BCOM Errata for the C0 type.
  1339. * Write magic patterns to reserved registers.
  1340. */
  1341. i = 0;
  1342. while (BcomRegC0Hack[i].PhyReg != 0) {
  1343. SkXmPhyWrite(pAC, IoC, Port, BcomRegC0Hack[i].PhyReg,
  1344. BcomRegC0Hack[i].PhyVal);
  1345. i++;
  1346. }
  1347. }
  1348. else if (pPrt->PhyId1 == PHY_BCOM_ID1_A1) {
  1349. /*
  1350. * Workaround BCOM Errata for the A1 type.
  1351. * Write magic patterns to reserved registers.
  1352. */
  1353. i = 0;
  1354. while (BcomRegA1Hack[i].PhyReg != 0) {
  1355. SkXmPhyWrite(pAC, IoC, Port, BcomRegA1Hack[i].PhyReg,
  1356. BcomRegA1Hack[i].PhyVal);
  1357. i++;
  1358. }
  1359. }
  1360. /*
  1361. * Workaround BCOM Errata (#10523) for all BCom PHYs.
  1362. * Disable Power Management after reset.
  1363. */
  1364. SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
  1365. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
  1366. (SK_U16)(SWord | PHY_B_AC_DIS_PM));
  1367. /* PHY LED initialization is done in SkGeXmitLED() */
  1368. }
  1369. /* Dummy read the Interrupt source register */
  1370. XM_IN16(IoC, Port, XM_ISRC, &SWord);
  1371. /*
  1372. * The auto-negotiation process starts immediately after
  1373. * clearing the reset. The auto-negotiation process should be
  1374. * started by the SIRQ, therefore stop it here immediately.
  1375. */
  1376. SkMacInitPhy(pAC, IoC, Port, SK_FALSE);
  1377. #if 0
  1378. /* temp. code: enable signal detect */
  1379. /* WARNING: do not override GMII setting above */
  1380. XM_OUT16(pAC, Port, XM_HW_CFG, XM_HW_COM4SIG);
  1381. #endif
  1382. }
  1383. /*
  1384. * configure the XMACs Station Address
  1385. * B2_MAC_2 = xx xx xx xx xx x1 is programmed to XMAC A
  1386. * B2_MAC_3 = xx xx xx xx xx x2 is programmed to XMAC B
  1387. */
  1388. for (i = 0; i < 3; i++) {
  1389. /*
  1390. * The following 2 statements are together endianess
  1391. * independent. Remember this when changing.
  1392. */
  1393. SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord);
  1394. XM_OUT16(IoC, Port, (XM_SA + i * 2), SWord);
  1395. }
  1396. /* Tx Inter Packet Gap (XM_TX_IPG): use default */
  1397. /* Tx High Water Mark (XM_TX_HI_WM): use default */
  1398. /* Tx Low Water Mark (XM_TX_LO_WM): use default */
  1399. /* Host Request Threshold (XM_HT_THR): use default */
  1400. /* Rx Request Threshold (XM_RX_THR): use default */
  1401. /* Rx Low Water Mark (XM_RX_LO_WM): use default */
  1402. /* configure Rx High Water Mark (XM_RX_HI_WM) */
  1403. XM_OUT16(IoC, Port, XM_RX_HI_WM, SK_XM_RX_HI_WM);
  1404. /* Configure Tx Request Threshold */
  1405. SWord = SK_XM_THR_SL; /* for single port */
  1406. if (pAC->GIni.GIMacsFound > 1) {
  1407. switch (pAC->GIni.GIPortUsage) {
  1408. case SK_RED_LINK:
  1409. SWord = SK_XM_THR_REDL; /* redundant link */
  1410. break;
  1411. case SK_MUL_LINK:
  1412. SWord = SK_XM_THR_MULL; /* load balancing */
  1413. break;
  1414. case SK_JUMBO_LINK:
  1415. SWord = SK_XM_THR_JUMBO; /* jumbo frames */
  1416. break;
  1417. default:
  1418. SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E014, SKERR_HWI_E014MSG);
  1419. break;
  1420. }
  1421. }
  1422. XM_OUT16(IoC, Port, XM_TX_THR, SWord);
  1423. /* setup register defaults for the Tx Command Register */
  1424. XM_OUT16(IoC, Port, XM_TX_CMD, XM_TX_AUTO_PAD);
  1425. /* setup register defaults for the Rx Command Register */
  1426. SWord = XM_RX_STRIP_FCS | XM_RX_LENERR_OK;
  1427. if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
  1428. SWord |= XM_RX_BIG_PK_OK;
  1429. }
  1430. if (pPrt->PLinkModeConf == SK_LMODE_HALF) {
  1431. /*
  1432. * If in manual half duplex mode the other side might be in
  1433. * full duplex mode, so ignore if a carrier extension is not seen
  1434. * on frames received
  1435. */
  1436. SWord |= XM_RX_DIS_CEXT;
  1437. }
  1438. XM_OUT16(IoC, Port, XM_RX_CMD, SWord);
  1439. /*
  1440. * setup register defaults for the Mode Register
  1441. * - Don't strip error frames to avoid Store & Forward
  1442. * on the Rx side.
  1443. * - Enable 'Check Station Address' bit
  1444. * - Enable 'Check Address Array' bit
  1445. */
  1446. XM_OUT32(IoC, Port, XM_MODE, XM_DEF_MODE);
  1447. /*
  1448. * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
  1449. * - Enable all bits excepting 'Octets Rx OK Low CntOv'
  1450. * and 'Octets Rx OK Hi Cnt Ov'.
  1451. */
  1452. XM_OUT32(IoC, Port, XM_RX_EV_MSK, XMR_DEF_MSK);
  1453. /*
  1454. * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
  1455. * - Enable all bits excepting 'Octets Tx OK Low CntOv'
  1456. * and 'Octets Tx OK Hi Cnt Ov'.
  1457. */
  1458. XM_OUT32(IoC, Port, XM_TX_EV_MSK, XMT_DEF_MSK);
  1459. /*
  1460. * Do NOT init XMAC interrupt mask here.
  1461. * All interrupts remain disable until link comes up!
  1462. */
  1463. /*
  1464. * Any additional configuration changes may be done now.
  1465. * The last action is to enable the Rx and Tx state machine.
  1466. * This should be done after the auto-negotiation process
  1467. * has been completed successfully.
  1468. */
  1469. } /* SkXmInitMac */
  1470. /******************************************************************************
  1471. *
  1472. * SkGmInitMac() - Initialize the GMAC
  1473. *
  1474. * Description:
  1475. * Initialize the GMAC of the specified port.
  1476. * The GMAC must be reset or stopped before calling this function.
  1477. *
  1478. * Note:
  1479. * The GMAC's Rx and Tx state machine is still disabled when returning.
  1480. *
  1481. * Returns:
  1482. * nothing
  1483. */
  1484. void SkGmInitMac(
  1485. SK_AC *pAC, /* adapter context */
  1486. SK_IOC IoC, /* IO context */
  1487. int Port) /* Port Index (MAC_1 + n) */
  1488. {
  1489. SK_GEPORT *pPrt;
  1490. int i;
  1491. SK_U16 SWord;
  1492. SK_U32 DWord;
  1493. pPrt = &pAC->GIni.GP[Port];
  1494. if (pPrt->PState == SK_PRT_STOP) {
  1495. /* Port State: SK_PRT_STOP */
  1496. /* Verify that the reset bit is cleared */
  1497. SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord);
  1498. if ((DWord & GMC_RST_SET) != 0) {
  1499. /* PState does not match HW state */
  1500. SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
  1501. /* Correct it */
  1502. pPrt->PState = SK_PRT_RESET;
  1503. }
  1504. }
  1505. if (pPrt->PState == SK_PRT_RESET) {
  1506. /* set GPHY Control reset */
  1507. SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET);
  1508. /* set GMAC Control reset */
  1509. SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
  1510. /* clear GMAC Control reset */
  1511. SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_CLR);
  1512. /* set GMAC Control reset */
  1513. SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
  1514. /* set HWCFG_MODE */
  1515. DWord = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
  1516. GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
  1517. (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
  1518. GPC_HWCFG_GMII_FIB);
  1519. /* set GPHY Control reset */
  1520. SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);
  1521. /* release GPHY Control reset */
  1522. SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
  1523. /* clear GMAC Control reset */
  1524. SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
  1525. /* Dummy read the Interrupt source register */
  1526. SK_IN16(IoC, GMAC_IRQ_SRC, &SWord);
  1527. #ifndef VCPU
  1528. /* read Id from PHY */
  1529. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1);
  1530. SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE);
  1531. #endif /* VCPU */
  1532. }
  1533. (void)SkGmResetCounter(pAC, IoC, Port);
  1534. SWord = 0;
  1535. /* speed settings */
  1536. switch (pPrt->PLinkSpeed) {
  1537. case SK_LSPEED_AUTO:
  1538. case SK_LSPEED_1000MBPS:
  1539. SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100;
  1540. break;
  1541. case SK_LSPEED_100MBPS:
  1542. SWord |= GM_GPCR_SPEED_100;
  1543. break;
  1544. case SK_LSPEED_10MBPS:
  1545. break;
  1546. }
  1547. /* duplex settings */
  1548. if (pPrt->PLinkMode != SK_LMODE_HALF) {
  1549. /* set full duplex */
  1550. SWord |= GM_GPCR_DUP_FULL;
  1551. }
  1552. /* flow control settings */
  1553. switch (pPrt->PFlowCtrlMode) {
  1554. case SK_FLOW_MODE_NONE:
  1555. /* disable auto-negotiation for flow-control */
  1556. SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS;
  1557. break;
  1558. case SK_FLOW_MODE_LOC_SEND:
  1559. SWord |= GM_GPCR_FC_RX_DIS;
  1560. break;
  1561. case SK_FLOW_MODE_SYMMETRIC:
  1562. /* TBD */
  1563. case SK_FLOW_MODE_SYM_OR_REM:
  1564. /* enable auto-negotiation for flow-control and */
  1565. /* enable Rx and Tx of pause frames */
  1566. break;
  1567. }
  1568. /* Auto-negotiation ? */
  1569. if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
  1570. /* disable auto-update for speed, duplex and flow-control */
  1571. SWord |= GM_GPCR_AU_ALL_DIS;
  1572. }
  1573. /* setup General Purpose Control Register */
  1574. GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
  1575. /* setup Transmit Control Register */
  1576. GM_OUT16(IoC, Port, GM_TX_CTRL, GM_TXCR_COL_THR);
  1577. /* setup Receive Control Register */
  1578. GM_OUT16(IoC, Port, GM_RX_CTRL, GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA |
  1579. GM_RXCR_CRC_DIS);
  1580. /* setup Transmit Flow Control Register */
  1581. GM_OUT16(IoC, Port, GM_TX_FLOW_CTRL, 0xffff);
  1582. /* setup Transmit Parameter Register */
  1583. #ifdef VCPU
  1584. GM_IN16(IoC, Port, GM_TX_PARAM, &SWord);
  1585. #endif /* VCPU */
  1586. SWord = JAM_LEN_VAL(3) | JAM_IPG_VAL(11) | IPG_JAM_DATA(26);
  1587. GM_OUT16(IoC, Port, GM_TX_PARAM, SWord);
  1588. /* configure the Serial Mode Register */
  1589. #ifdef VCPU
  1590. GM_IN16(IoC, Port, GM_SERIAL_MODE, &SWord);
  1591. #endif /* VCPU */
  1592. SWord = GM_SMOD_VLAN_ENA | IPG_VAL_FAST_ETH;
  1593. if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
  1594. /* enable jumbo mode (Max. Frame Length = 9018) */
  1595. SWord |= GM_SMOD_JUMBO_ENA;
  1596. }
  1597. GM_OUT16(IoC, Port, GM_SERIAL_MODE, SWord);
  1598. /*
  1599. * configure the GMACs Station Addresses
  1600. * in PROM you can find our addresses at:
  1601. * B2_MAC_1 = xx xx xx xx xx x0 virtual address
  1602. * B2_MAC_2 = xx xx xx xx xx x1 is programmed to GMAC A
  1603. * B2_MAC_3 = xx xx xx xx xx x2 is reserved for DualPort
  1604. */
  1605. for (i = 0; i < 3; i++) {
  1606. /*
  1607. * The following 2 statements are together endianess
  1608. * independent. Remember this when changing.
  1609. */
  1610. /* physical address: will be used for pause frames */
  1611. SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord);
  1612. #ifdef WA_DEV_16
  1613. /* WA for deviation #16 */
  1614. if (pAC->GIni.GIChipRev == 0) {
  1615. /* swap the address bytes */
  1616. SWord = ((SWord & 0xff00) >> 8) | ((SWord & 0x00ff) << 8);
  1617. /* write to register in reversed order */
  1618. GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + (2 - i) * 4), SWord);
  1619. }
  1620. else {
  1621. GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
  1622. }
  1623. #else
  1624. GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
  1625. #endif /* WA_DEV_16 */
  1626. /* virtual address: will be used for data */
  1627. SK_IN16(IoC, (B2_MAC_1 + Port * 8 + i * 2), &SWord);
  1628. GM_OUT16(IoC, Port, (GM_SRC_ADDR_2L + i * 4), SWord);
  1629. /* reset Multicast filtering Hash registers 1-3 */
  1630. GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + 4*i, 0);
  1631. }
  1632. /* reset Multicast filtering Hash register 4 */
  1633. GM_OUT16(IoC, Port, GM_MC_ADDR_H4, 0);
  1634. /* enable interrupt mask for counter overflows */
  1635. GM_OUT16(IoC, Port, GM_TX_IRQ_MSK, 0);
  1636. GM_OUT16(IoC, Port, GM_RX_IRQ_MSK, 0);
  1637. GM_OUT16(IoC, Port, GM_TR_IRQ_MSK, 0);
  1638. /* read General Purpose Status */
  1639. GM_IN16(IoC, Port, GM_GP_STAT, &SWord);
  1640. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  1641. ("MAC Stat Reg=0x%04X\n", SWord));
  1642. #ifdef SK_DIAG
  1643. c_print("MAC Stat Reg=0x%04X\n", SWord);
  1644. #endif /* SK_DIAG */
  1645. } /* SkGmInitMac */
  1646. /******************************************************************************
  1647. *
  1648. * SkXmInitDupMd() - Initialize the XMACs Duplex Mode
  1649. *
  1650. * Description:
  1651. * This function initializes the XMACs Duplex Mode.
  1652. * It should be called after successfully finishing
  1653. * the Auto-negotiation Process
  1654. *
  1655. * Returns:
  1656. * nothing
  1657. */
  1658. void SkXmInitDupMd(
  1659. SK_AC *pAC, /* adapter context */
  1660. SK_IOC IoC, /* IO context */
  1661. int Port) /* Port Index (MAC_1 + n) */
  1662. {
  1663. switch (pAC->GIni.GP[Port].PLinkModeStatus) {
  1664. case SK_LMODE_STAT_AUTOHALF:
  1665. case SK_LMODE_STAT_HALF:
  1666. /* Configuration Actions for Half Duplex Mode */
  1667. /*
  1668. * XM_BURST = default value. We are probable not quick
  1669. * enough at the 'XMAC' bus to burst 8kB.
  1670. * The XMAC stops bursting if no transmit frames
  1671. * are available or the burst limit is exceeded.
  1672. */
  1673. /* XM_TX_RT_LIM = default value (15) */
  1674. /* XM_TX_STIME = default value (0xff = 4096 bit times) */
  1675. break;
  1676. case SK_LMODE_STAT_AUTOFULL:
  1677. case SK_LMODE_STAT_FULL:
  1678. /* Configuration Actions for Full Duplex Mode */
  1679. /*
  1680. * The duplex mode is configured by the PHY,
  1681. * therefore it seems to be that there is nothing
  1682. * to do here.
  1683. */
  1684. break;
  1685. case SK_LMODE_STAT_UNKNOWN:
  1686. default:
  1687. SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E007, SKERR_HWI_E007MSG);
  1688. break;
  1689. }
  1690. } /* SkXmInitDupMd */
  1691. /******************************************************************************
  1692. *
  1693. * SkXmInitPauseMd() - initialize the Pause Mode to be used for this port
  1694. *
  1695. * Description:
  1696. * This function initializes the Pause Mode which should
  1697. * be used for this port.
  1698. * It should be called after successfully finishing
  1699. * the Auto-negotiation Process
  1700. *
  1701. * Returns:
  1702. * nothing
  1703. */
  1704. void SkXmInitPauseMd(
  1705. SK_AC *pAC, /* adapter context */
  1706. SK_IOC IoC, /* IO context */
  1707. int Port) /* Port Index (MAC_1 + n) */
  1708. {
  1709. SK_GEPORT *pPrt;
  1710. SK_U32 DWord;
  1711. SK_U32 *pDWord = &DWord;
  1712. SK_U16 Word;
  1713. pPrt = &pAC->GIni.GP[Port];
  1714. XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
  1715. if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE ||
  1716. pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {
  1717. /* Disable Pause Frame Reception */
  1718. Word |= XM_MMU_IGN_PF;
  1719. }
  1720. else {
  1721. /*
  1722. * enabling pause frame reception is required for 1000BT
  1723. * because the XMAC is not reset if the link is going down
  1724. */
  1725. /* Enable Pause Frame Reception */
  1726. Word &= ~XM_MMU_IGN_PF;
  1727. }
  1728. XM_OUT16(IoC, Port, XM_MMU_CMD, Word);
  1729. XM_IN32(IoC, Port, XM_MODE, pDWord);
  1730. if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_SYMMETRIC ||
  1731. pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {
  1732. /*
  1733. * Configure Pause Frame Generation
  1734. * Use internal and external Pause Frame Generation.
  1735. * Sending pause frames is edge triggered.
  1736. * Send a Pause frame with the maximum pause time if
  1737. * internal oder external FIFO full condition occurs.
  1738. * Send a zero pause time frame to re-start transmission.
  1739. */
  1740. /* XM_PAUSE_DA = '010000C28001' (default) */
  1741. /* XM_MAC_PTIME = 0xffff (maximum) */
  1742. /* remember this value is defined in big endian (!) */
  1743. XM_OUT16(IoC, Port, XM_MAC_PTIME, 0xffff);
  1744. /* Set Pause Mode in Mode Register */
  1745. DWord |= XM_PAUSE_MODE;
  1746. /* Set Pause Mode in MAC Rx FIFO */
  1747. SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
  1748. }
  1749. else {
  1750. /*
  1751. * disable pause frame generation is required for 1000BT
  1752. * because the XMAC is not reset if the link is going down
  1753. */
  1754. /* Disable Pause Mode in Mode Register */
  1755. DWord &= ~XM_PAUSE_MODE;
  1756. /* Disable Pause Mode in MAC Rx FIFO */
  1757. SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
  1758. }
  1759. XM_OUT32(IoC, Port, XM_MODE, DWord);
  1760. } /* SkXmInitPauseMd*/
  1761. /******************************************************************************
  1762. *
  1763. * SkXmInitPhyXmac() - Initialize the XMAC Phy registers
  1764. *
  1765. * Description: initializes all the XMACs Phy registers
  1766. *
  1767. * Note:
  1768. *
  1769. * Returns:
  1770. * nothing
  1771. */
  1772. static void SkXmInitPhyXmac(
  1773. SK_AC *pAC, /* adapter context */
  1774. SK_IOC IoC, /* IO context */
  1775. int Port, /* Port Index (MAC_1 + n) */
  1776. SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
  1777. {
  1778. SK_GEPORT *pPrt;
  1779. SK_U16 Ctrl;
  1780. pPrt = &pAC->GIni.GP[Port];
  1781. Ctrl = 0;
  1782. /* Auto-negotiation ? */
  1783. if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
  1784. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  1785. ("InitPhyXmac: no auto-negotiation Port %d\n", Port));
  1786. /* Set DuplexMode in Config register */
  1787. if (pPrt->PLinkMode == SK_LMODE_FULL) {
  1788. Ctrl |= PHY_CT_DUP_MD;
  1789. }
  1790. /*
  1791. * Do NOT enable Auto-negotiation here. This would hold
  1792. * the link down because no IDLEs are transmitted
  1793. */
  1794. }
  1795. else {
  1796. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  1797. ("InitPhyXmac: with auto-negotiation Port %d\n", Port));
  1798. /* Set Auto-negotiation advertisement */
  1799. /* Set Full/half duplex capabilities */
  1800. switch (pPrt->PLinkMode) {
  1801. case SK_LMODE_AUTOHALF:
  1802. Ctrl |= PHY_X_AN_HD;
  1803. break;
  1804. case SK_LMODE_AUTOFULL:
  1805. Ctrl |= PHY_X_AN_FD;
  1806. break;
  1807. case SK_LMODE_AUTOBOTH:
  1808. Ctrl |= PHY_X_AN_FD | PHY_X_AN_HD;
  1809. break;
  1810. default:
  1811. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
  1812. SKERR_HWI_E015MSG);
  1813. }
  1814. switch (pPrt->PFlowCtrlMode) {
  1815. case SK_FLOW_MODE_NONE:
  1816. Ctrl |= PHY_X_P_NO_PAUSE;
  1817. break;
  1818. case SK_FLOW_MODE_LOC_SEND:
  1819. Ctrl |= PHY_X_P_ASYM_MD;
  1820. break;
  1821. case SK_FLOW_MODE_SYMMETRIC:
  1822. Ctrl |= PHY_X_P_SYM_MD;
  1823. break;
  1824. case SK_FLOW_MODE_SYM_OR_REM:
  1825. Ctrl |= PHY_X_P_BOTH_MD;
  1826. break;
  1827. default:
  1828. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
  1829. SKERR_HWI_E016MSG);
  1830. }
  1831. /* Write AutoNeg Advertisement Register */
  1832. SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_AUNE_ADV, Ctrl);
  1833. /* Restart Auto-negotiation */
  1834. Ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
  1835. }
  1836. if (DoLoop) {
  1837. /* Set the Phy Loopback bit, too */
  1838. Ctrl |= PHY_CT_LOOP;
  1839. }
  1840. /* Write to the Phy control register */
  1841. SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_CTRL, Ctrl);
  1842. } /* SkXmInitPhyXmac */
  1843. /******************************************************************************
  1844. *
  1845. * SkXmInitPhyBcom() - Initialize the Broadcom Phy registers
  1846. *
  1847. * Description: initializes all the Broadcom Phy registers
  1848. *
  1849. * Note:
  1850. *
  1851. * Returns:
  1852. * nothing
  1853. */
  1854. static void SkXmInitPhyBcom(
  1855. SK_AC *pAC, /* adapter context */
  1856. SK_IOC IoC, /* IO context */
  1857. int Port, /* Port Index (MAC_1 + n) */
  1858. SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
  1859. {
  1860. SK_GEPORT *pPrt;
  1861. SK_U16 Ctrl1;
  1862. SK_U16 Ctrl2;
  1863. SK_U16 Ctrl3;
  1864. SK_U16 Ctrl4;
  1865. SK_U16 Ctrl5;
  1866. Ctrl1 = PHY_CT_SP1000;
  1867. Ctrl2 = 0;
  1868. Ctrl3 = PHY_SEL_TYPE;
  1869. Ctrl4 = PHY_B_PEC_EN_LTR;
  1870. Ctrl5 = PHY_B_AC_TX_TST;
  1871. pPrt = &pAC->GIni.GP[Port];
  1872. /* manually Master/Slave ? */
  1873. if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
  1874. Ctrl2 |= PHY_B_1000C_MSE;
  1875. if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
  1876. Ctrl2 |= PHY_B_1000C_MSC;
  1877. }
  1878. }
  1879. /* Auto-negotiation ? */
  1880. if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
  1881. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  1882. ("InitPhyBcom: no auto-negotiation Port %d\n", Port));
  1883. /* Set DuplexMode in Config register */
  1884. Ctrl1 |= (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0);
  1885. /* Determine Master/Slave manually if not already done */
  1886. if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
  1887. Ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
  1888. }
  1889. /*
  1890. * Do NOT enable Auto-negotiation here. This would hold
  1891. * the link down because no IDLES are transmitted
  1892. */
  1893. }
  1894. else {
  1895. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  1896. ("InitPhyBcom: with auto-negotiation Port %d\n", Port));
  1897. /* Set Auto-negotiation advertisement */
  1898. /*
  1899. * Workaround BCOM Errata #1 for the C5 type.
  1900. * 1000Base-T Link Acquisition Failure in Slave Mode
  1901. * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
  1902. */
  1903. Ctrl2 |= PHY_B_1000C_RD;
  1904. /* Set Full/half duplex capabilities */
  1905. switch (pPrt->PLinkMode) {
  1906. case SK_LMODE_AUTOHALF:
  1907. Ctrl2 |= PHY_B_1000C_AHD;
  1908. break;
  1909. case SK_LMODE_AUTOFULL:
  1910. Ctrl2 |= PHY_B_1000C_AFD;
  1911. break;
  1912. case SK_LMODE_AUTOBOTH:
  1913. Ctrl2 |= PHY_B_1000C_AFD | PHY_B_1000C_AHD;
  1914. break;
  1915. default:
  1916. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
  1917. SKERR_HWI_E015MSG);
  1918. }
  1919. switch (pPrt->PFlowCtrlMode) {
  1920. case SK_FLOW_MODE_NONE:
  1921. Ctrl3 |= PHY_B_P_NO_PAUSE;
  1922. break;
  1923. case SK_FLOW_MODE_LOC_SEND:
  1924. Ctrl3 |= PHY_B_P_ASYM_MD;
  1925. break;
  1926. case SK_FLOW_MODE_SYMMETRIC:
  1927. Ctrl3 |= PHY_B_P_SYM_MD;
  1928. break;
  1929. case SK_FLOW_MODE_SYM_OR_REM:
  1930. Ctrl3 |= PHY_B_P_BOTH_MD;
  1931. break;
  1932. default:
  1933. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
  1934. SKERR_HWI_E016MSG);
  1935. }
  1936. /* Restart Auto-negotiation */
  1937. Ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
  1938. }
  1939. /* Initialize LED register here? */
  1940. /* No. Please do it in SkDgXmitLed() (if required) and swap
  1941. init order of LEDs and XMAC. (MAl) */
  1942. /* Write 1000Base-T Control Register */
  1943. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, Ctrl2);
  1944. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  1945. ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
  1946. /* Write AutoNeg Advertisement Register */
  1947. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, Ctrl3);
  1948. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  1949. ("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3));
  1950. if (DoLoop) {
  1951. /* Set the Phy Loopback bit, too */
  1952. Ctrl1 |= PHY_CT_LOOP;
  1953. }
  1954. if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
  1955. /* configure FIFO to high latency for transmission of ext. packets */
  1956. Ctrl4 |= PHY_B_PEC_HIGH_LA;
  1957. /* configure reception of extended packets */
  1958. Ctrl5 |= PHY_B_AC_LONG_PACK;
  1959. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, Ctrl5);
  1960. }
  1961. /* Configure LED Traffic Mode and Jumbo Frame usage if specified */
  1962. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, Ctrl4);
  1963. /* Write to the Phy control register */
  1964. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, Ctrl1);
  1965. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  1966. ("PHY Control Reg=0x%04X\n", Ctrl1));
  1967. } /* SkXmInitPhyBcom */
  1968. /******************************************************************************
  1969. *
  1970. * SkGmInitPhyMarv() - Initialize the Marvell Phy registers
  1971. *
  1972. * Description: initializes all the Marvell Phy registers
  1973. *
  1974. * Note:
  1975. *
  1976. * Returns:
  1977. * nothing
  1978. */
  1979. static void SkGmInitPhyMarv(
  1980. SK_AC *pAC, /* adapter context */
  1981. SK_IOC IoC, /* IO context */
  1982. int Port, /* Port Index (MAC_1 + n) */
  1983. SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
  1984. {
  1985. SK_GEPORT *pPrt;
  1986. SK_U16 PhyCtrl;
  1987. SK_U16 C1000BaseT;
  1988. SK_U16 AutoNegAdv;
  1989. SK_U16 ExtPhyCtrl;
  1990. SK_U16 PhyStat;
  1991. SK_U16 PhyStat1;
  1992. SK_U16 PhySpecStat;
  1993. SK_U16 LedCtrl;
  1994. SK_BOOL AutoNeg;
  1995. #ifdef VCPU
  1996. VCPUprintf(0, "SkGmInitPhyMarv(), Port=%u, DoLoop=%u\n",
  1997. Port, DoLoop);
  1998. #else /* VCPU */
  1999. pPrt = &pAC->GIni.GP[Port];
  2000. /* Auto-negotiation ? */
  2001. if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
  2002. AutoNeg = SK_FALSE;
  2003. }
  2004. else {
  2005. AutoNeg = SK_TRUE;
  2006. }
  2007. if (!DoLoop) {
  2008. /* Read Ext. PHY Specific Control */
  2009. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
  2010. ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
  2011. PHY_M_EC_MAC_S_MSK);
  2012. ExtPhyCtrl |= PHY_M_EC_M_DSC(1) | PHY_M_EC_S_DSC(1) |
  2013. PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
  2014. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
  2015. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2016. ("Ext.PHYCtrl=0x%04X\n", ExtPhyCtrl));
  2017. /* Read PHY Control */
  2018. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
  2019. /* Assert software reset */
  2020. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL,
  2021. (SK_U16)(PhyCtrl | PHY_CT_RESET));
  2022. }
  2023. #endif /* VCPU */
  2024. PhyCtrl = 0 /* PHY_CT_COL_TST */;
  2025. C1000BaseT = 0;
  2026. AutoNegAdv = PHY_SEL_TYPE;
  2027. /* manually Master/Slave ? */
  2028. if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
  2029. /* enable Manual Master/Slave */
  2030. C1000BaseT |= PHY_M_1000C_MSE;
  2031. if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
  2032. C1000BaseT |= PHY_M_1000C_MSC; /* set it to Master */
  2033. }
  2034. }
  2035. /* Auto-negotiation ? */
  2036. if (!AutoNeg) {
  2037. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2038. ("InitPhyMarv: no auto-negotiation Port %d\n", Port));
  2039. if (pPrt->PLinkMode == SK_LMODE_FULL) {
  2040. /* Set Full Duplex Mode */
  2041. PhyCtrl |= PHY_CT_DUP_MD;
  2042. }
  2043. /* Set Master/Slave manually if not already done */
  2044. if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
  2045. C1000BaseT |= PHY_M_1000C_MSE; /* set it to Slave */
  2046. }
  2047. /* Set Speed */
  2048. switch (pPrt->PLinkSpeed) {
  2049. case SK_LSPEED_AUTO:
  2050. case SK_LSPEED_1000MBPS:
  2051. PhyCtrl |= PHY_CT_SP1000;
  2052. break;
  2053. case SK_LSPEED_100MBPS:
  2054. PhyCtrl |= PHY_CT_SP100;
  2055. break;
  2056. case SK_LSPEED_10MBPS:
  2057. break;
  2058. default:
  2059. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019,
  2060. SKERR_HWI_E019MSG);
  2061. }
  2062. if (!DoLoop) {
  2063. PhyCtrl |= PHY_CT_RESET;
  2064. }
  2065. /*
  2066. * Do NOT enable Auto-negotiation here. This would hold
  2067. * the link down because no IDLES are transmitted
  2068. */
  2069. }
  2070. else {
  2071. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2072. ("InitPhyMarv: with auto-negotiation Port %d\n", Port));
  2073. PhyCtrl |= PHY_CT_ANE;
  2074. if (pAC->GIni.GICopperType) {
  2075. /* Set Speed capabilities */
  2076. switch (pPrt->PLinkSpeed) {
  2077. case SK_LSPEED_AUTO:
  2078. C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;
  2079. AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
  2080. PHY_M_AN_10_FD | PHY_M_AN_10_HD;
  2081. break;
  2082. case SK_LSPEED_1000MBPS:
  2083. C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;
  2084. break;
  2085. case SK_LSPEED_100MBPS:
  2086. AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
  2087. PHY_M_AN_10_FD | PHY_M_AN_10_HD;
  2088. break;
  2089. case SK_LSPEED_10MBPS:
  2090. AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD;
  2091. break;
  2092. default:
  2093. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019,
  2094. SKERR_HWI_E019MSG);
  2095. }
  2096. /* Set Full/half duplex capabilities */
  2097. switch (pPrt->PLinkMode) {
  2098. case SK_LMODE_AUTOHALF:
  2099. C1000BaseT &= ~PHY_M_1000C_AFD;
  2100. AutoNegAdv &= ~(PHY_M_AN_100_FD | PHY_M_AN_10_FD);
  2101. break;
  2102. case SK_LMODE_AUTOFULL:
  2103. C1000BaseT &= ~PHY_M_1000C_AHD;
  2104. AutoNegAdv &= ~(PHY_M_AN_100_HD | PHY_M_AN_10_HD);
  2105. break;
  2106. case SK_LMODE_AUTOBOTH:
  2107. break;
  2108. default:
  2109. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
  2110. SKERR_HWI_E015MSG);
  2111. }
  2112. /* Set Auto-negotiation advertisement */
  2113. switch (pPrt->PFlowCtrlMode) {
  2114. case SK_FLOW_MODE_NONE:
  2115. AutoNegAdv |= PHY_B_P_NO_PAUSE;
  2116. break;
  2117. case SK_FLOW_MODE_LOC_SEND:
  2118. AutoNegAdv |= PHY_B_P_ASYM_MD;
  2119. break;
  2120. case SK_FLOW_MODE_SYMMETRIC:
  2121. AutoNegAdv |= PHY_B_P_SYM_MD;
  2122. break;
  2123. case SK_FLOW_MODE_SYM_OR_REM:
  2124. AutoNegAdv |= PHY_B_P_BOTH_MD;
  2125. break;
  2126. default:
  2127. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
  2128. SKERR_HWI_E016MSG);
  2129. }
  2130. }
  2131. else { /* special defines for FIBER (88E1011S only) */
  2132. /* Set Full/half duplex capabilities */
  2133. switch (pPrt->PLinkMode) {
  2134. case SK_LMODE_AUTOHALF:
  2135. AutoNegAdv |= PHY_M_AN_1000X_AHD;
  2136. break;
  2137. case SK_LMODE_AUTOFULL:
  2138. AutoNegAdv |= PHY_M_AN_1000X_AFD;
  2139. break;
  2140. case SK_LMODE_AUTOBOTH:
  2141. AutoNegAdv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
  2142. break;
  2143. default:
  2144. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
  2145. SKERR_HWI_E015MSG);
  2146. }
  2147. /* Set Auto-negotiation advertisement */
  2148. switch (pPrt->PFlowCtrlMode) {
  2149. case SK_FLOW_MODE_NONE:
  2150. AutoNegAdv |= PHY_M_P_NO_PAUSE_X;
  2151. break;
  2152. case SK_FLOW_MODE_LOC_SEND:
  2153. AutoNegAdv |= PHY_M_P_ASYM_MD_X;
  2154. break;
  2155. case SK_FLOW_MODE_SYMMETRIC:
  2156. AutoNegAdv |= PHY_M_P_SYM_MD_X;
  2157. break;
  2158. case SK_FLOW_MODE_SYM_OR_REM:
  2159. AutoNegAdv |= PHY_M_P_BOTH_MD_X;
  2160. break;
  2161. default:
  2162. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
  2163. SKERR_HWI_E016MSG);
  2164. }
  2165. }
  2166. if (!DoLoop) {
  2167. /* Restart Auto-negotiation */
  2168. PhyCtrl |= PHY_CT_RE_CFG;
  2169. }
  2170. }
  2171. #ifdef VCPU
  2172. /*
  2173. * E-mail from Gu Lin (08-03-2002):
  2174. */
  2175. /* Program PHY register 30 as 16'h0708 for simulation speed up */
  2176. SkGmPhyWrite(pAC, IoC, Port, 30, 0x0708);
  2177. VCpuWait(2000);
  2178. #else /* VCPU */
  2179. /* Write 1000Base-T Control Register */
  2180. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
  2181. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2182. ("1000B-T Ctrl=0x%04X\n", C1000BaseT));
  2183. /* Write AutoNeg Advertisement Register */
  2184. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv);
  2185. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2186. ("Auto-Neg.Ad.=0x%04X\n", AutoNegAdv));
  2187. #endif /* VCPU */
  2188. if (DoLoop) {
  2189. /* Set the PHY Loopback bit */
  2190. PhyCtrl |= PHY_CT_LOOP;
  2191. /* Program PHY register 16 as 16'h0400 to force link good */
  2192. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_FL_GOOD);
  2193. #if 0
  2194. if (pPrt->PLinkSpeed != SK_LSPEED_AUTO) {
  2195. /* Write Ext. PHY Specific Control */
  2196. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL,
  2197. (SK_U16)((pPrt->PLinkSpeed + 2) << 4));
  2198. }
  2199. }
  2200. else if (pPrt->PLinkSpeed == SK_LSPEED_10MBPS) {
  2201. /* Write PHY Specific Control */
  2202. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_EN_DET_MSK);
  2203. }
  2204. #endif /* 0 */
  2205. }
  2206. /* Write to the PHY Control register */
  2207. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl);
  2208. #ifdef VCPU
  2209. VCpuWait(2000);
  2210. #else
  2211. LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS) | PHY_M_LED_BLINK_RT(BLINK_84MS);
  2212. #ifdef ACT_LED_BLINK
  2213. LedCtrl |= PHY_M_LEDC_RX_CTRL | PHY_M_LEDC_TX_CTRL;
  2214. #endif /* ACT_LED_BLINK */
  2215. #ifdef DUP_LED_NORMAL
  2216. LedCtrl |= PHY_M_LEDC_DP_CTRL;
  2217. #endif /* DUP_LED_NORMAL */
  2218. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl);
  2219. #endif /* VCPU */
  2220. #ifdef SK_DIAG
  2221. c_print("Set PHY Ctrl=0x%04X\n", PhyCtrl);
  2222. c_print("Set 1000 B-T=0x%04X\n", C1000BaseT);
  2223. c_print("Set Auto-Neg=0x%04X\n", AutoNegAdv);
  2224. c_print("Set Ext Ctrl=0x%04X\n", ExtPhyCtrl);
  2225. #endif /* SK_DIAG */
  2226. #ifndef xDEBUG
  2227. /* Read PHY Control */
  2228. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
  2229. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2230. ("PHY Ctrl Reg.=0x%04X\n", PhyCtrl));
  2231. /* Read 1000Base-T Control Register */
  2232. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
  2233. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2234. ("1000B-T Ctrl =0x%04X\n", C1000BaseT));
  2235. /* Read AutoNeg Advertisement Register */
  2236. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &AutoNegAdv);
  2237. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2238. ("Auto-Neg. Ad.=0x%04X\n", AutoNegAdv));
  2239. /* Read Ext. PHY Specific Control */
  2240. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
  2241. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2242. ("Ext PHY Ctrl=0x%04X\n", ExtPhyCtrl));
  2243. /* Read PHY Status */
  2244. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat);
  2245. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2246. ("PHY Stat Reg.=0x%04X\n", PhyStat));
  2247. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat1);
  2248. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2249. ("PHY Stat Reg.=0x%04X\n", PhyStat1));
  2250. /* Read PHY Specific Status */
  2251. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
  2252. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2253. ("PHY Spec Stat=0x%04X\n", PhySpecStat));
  2254. #endif /* DEBUG */
  2255. #ifdef SK_DIAG
  2256. c_print("PHY Ctrl Reg=0x%04X\n", PhyCtrl);
  2257. c_print("PHY 1000 Reg=0x%04X\n", C1000BaseT);
  2258. c_print("PHY AnAd Reg=0x%04X\n", AutoNegAdv);
  2259. c_print("Ext Ctrl Reg=0x%04X\n", ExtPhyCtrl);
  2260. c_print("PHY Stat Reg=0x%04X\n", PhyStat);
  2261. c_print("PHY Stat Reg=0x%04X\n", PhyStat1);
  2262. c_print("PHY Spec Reg=0x%04X\n", PhySpecStat);
  2263. #endif /* SK_DIAG */
  2264. } /* SkGmInitPhyMarv */
  2265. #ifdef OTHER_PHY
  2266. /******************************************************************************
  2267. *
  2268. * SkXmInitPhyLone() - Initialize the Level One Phy registers
  2269. *
  2270. * Description: initializes all the Level One Phy registers
  2271. *
  2272. * Note:
  2273. *
  2274. * Returns:
  2275. * nothing
  2276. */
  2277. static void SkXmInitPhyLone(
  2278. SK_AC *pAC, /* adapter context */
  2279. SK_IOC IoC, /* IO context */
  2280. int Port, /* Port Index (MAC_1 + n) */
  2281. SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
  2282. {
  2283. SK_GEPORT *pPrt;
  2284. SK_U16 Ctrl1;
  2285. SK_U16 Ctrl2;
  2286. SK_U16 Ctrl3;
  2287. Ctrl1 = PHY_CT_SP1000;
  2288. Ctrl2 = 0;
  2289. Ctrl3 = PHY_SEL_TYPE;
  2290. pPrt = &pAC->GIni.GP[Port];
  2291. /* manually Master/Slave ? */
  2292. if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
  2293. Ctrl2 |= PHY_L_1000C_MSE;
  2294. if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
  2295. Ctrl2 |= PHY_L_1000C_MSC;
  2296. }
  2297. }
  2298. /* Auto-negotiation ? */
  2299. if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
  2300. /*
  2301. * level one spec say: "1000Mbps: manual mode not allowed"
  2302. * but lets see what happens...
  2303. */
  2304. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2305. ("InitPhyLone: no auto-negotiation Port %d\n", Port));
  2306. /* Set DuplexMode in Config register */
  2307. Ctrl1 = (pPrt->PLinkMode == SK_LMODE_FULL ? PHY_CT_DUP_MD : 0);
  2308. /* Determine Master/Slave manually if not already done */
  2309. if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
  2310. Ctrl2 |= PHY_L_1000C_MSE; /* set it to Slave */
  2311. }
  2312. /*
  2313. * Do NOT enable Auto-negotiation here. This would hold
  2314. * the link down because no IDLES are transmitted
  2315. */
  2316. }
  2317. else {
  2318. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2319. ("InitPhyLone: with auto-negotiation Port %d\n", Port));
  2320. /* Set Auto-negotiation advertisement */
  2321. /* Set Full/half duplex capabilities */
  2322. switch (pPrt->PLinkMode) {
  2323. case SK_LMODE_AUTOHALF:
  2324. Ctrl2 |= PHY_L_1000C_AHD;
  2325. break;
  2326. case SK_LMODE_AUTOFULL:
  2327. Ctrl2 |= PHY_L_1000C_AFD;
  2328. break;
  2329. case SK_LMODE_AUTOBOTH:
  2330. Ctrl2 |= PHY_L_1000C_AFD | PHY_L_1000C_AHD;
  2331. break;
  2332. default:
  2333. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
  2334. SKERR_HWI_E015MSG);
  2335. }
  2336. switch (pPrt->PFlowCtrlMode) {
  2337. case SK_FLOW_MODE_NONE:
  2338. Ctrl3 |= PHY_L_P_NO_PAUSE;
  2339. break;
  2340. case SK_FLOW_MODE_LOC_SEND:
  2341. Ctrl3 |= PHY_L_P_ASYM_MD;
  2342. break;
  2343. case SK_FLOW_MODE_SYMMETRIC:
  2344. Ctrl3 |= PHY_L_P_SYM_MD;
  2345. break;
  2346. case SK_FLOW_MODE_SYM_OR_REM:
  2347. Ctrl3 |= PHY_L_P_BOTH_MD;
  2348. break;
  2349. default:
  2350. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
  2351. SKERR_HWI_E016MSG);
  2352. }
  2353. /* Restart Auto-negotiation */
  2354. Ctrl1 = PHY_CT_ANE | PHY_CT_RE_CFG;
  2355. }
  2356. /* Initialize LED register here ? */
  2357. /* No. Please do it in SkDgXmitLed() (if required) and swap
  2358. init order of LEDs and XMAC. (MAl) */
  2359. /* Write 1000Base-T Control Register */
  2360. SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_1000T_CTRL, Ctrl2);
  2361. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2362. ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
  2363. /* Write AutoNeg Advertisement Register */
  2364. SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_AUNE_ADV, Ctrl3);
  2365. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2366. ("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3));
  2367. if (DoLoop) {
  2368. /* Set the Phy Loopback bit, too */
  2369. Ctrl1 |= PHY_CT_LOOP;
  2370. }
  2371. /* Write to the Phy control register */
  2372. SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_CTRL, Ctrl1);
  2373. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2374. ("PHY Control Reg=0x%04X\n", Ctrl1));
  2375. } /* SkXmInitPhyLone */
  2376. /******************************************************************************
  2377. *
  2378. * SkXmInitPhyNat() - Initialize the National Phy registers
  2379. *
  2380. * Description: initializes all the National Phy registers
  2381. *
  2382. * Note:
  2383. *
  2384. * Returns:
  2385. * nothing
  2386. */
  2387. static void SkXmInitPhyNat(
  2388. SK_AC *pAC, /* adapter context */
  2389. SK_IOC IoC, /* IO context */
  2390. int Port, /* Port Index (MAC_1 + n) */
  2391. SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
  2392. {
  2393. /* todo: National */
  2394. } /* SkXmInitPhyNat */
  2395. #endif /* OTHER_PHY */
  2396. /******************************************************************************
  2397. *
  2398. * SkMacInitPhy() - Initialize the PHY registers
  2399. *
  2400. * Description: calls the Init PHY routines dep. on board type
  2401. *
  2402. * Note:
  2403. *
  2404. * Returns:
  2405. * nothing
  2406. */
  2407. void SkMacInitPhy(
  2408. SK_AC *pAC, /* adapter context */
  2409. SK_IOC IoC, /* IO context */
  2410. int Port, /* Port Index (MAC_1 + n) */
  2411. SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
  2412. {
  2413. SK_GEPORT *pPrt;
  2414. pPrt = &pAC->GIni.GP[Port];
  2415. switch (pPrt->PhyType) {
  2416. case SK_PHY_XMAC:
  2417. SkXmInitPhyXmac(pAC, IoC, Port, DoLoop);
  2418. break;
  2419. case SK_PHY_BCOM:
  2420. SkXmInitPhyBcom(pAC, IoC, Port, DoLoop);
  2421. break;
  2422. case SK_PHY_MARV_COPPER:
  2423. case SK_PHY_MARV_FIBER:
  2424. SkGmInitPhyMarv(pAC, IoC, Port, DoLoop);
  2425. break;
  2426. #ifdef OTHER_PHY
  2427. case SK_PHY_LONE:
  2428. SkXmInitPhyLone(pAC, IoC, Port, DoLoop);
  2429. break;
  2430. case SK_PHY_NAT:
  2431. SkXmInitPhyNat(pAC, IoC, Port, DoLoop);
  2432. break;
  2433. #endif /* OTHER_PHY */
  2434. }
  2435. } /* SkMacInitPhy */
  2436. #ifndef SK_DIAG
  2437. /******************************************************************************
  2438. *
  2439. * SkXmAutoNegLipaXmac() - Decides whether Link Partner could do auto-neg
  2440. *
  2441. * This function analyses the Interrupt status word. If any of the
  2442. * Auto-negotiating interrupt bits are set, the PLipaAutoNeg variable
  2443. * is set true.
  2444. */
  2445. void SkXmAutoNegLipaXmac(
  2446. SK_AC *pAC, /* adapter context */
  2447. SK_IOC IoC, /* IO context */
  2448. int Port, /* Port Index (MAC_1 + n) */
  2449. SK_U16 IStatus) /* Interrupt Status word to analyse */
  2450. {
  2451. SK_GEPORT *pPrt;
  2452. pPrt = &pAC->GIni.GP[Port];
  2453. if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO &&
  2454. (IStatus & (XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND)) != 0) {
  2455. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2456. ("AutoNegLipa: AutoNeg detected on Port %d, IStatus=0x%04x\n",
  2457. Port, IStatus));
  2458. pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
  2459. }
  2460. } /* SkXmAutoNegLipaXmac */
  2461. /******************************************************************************
  2462. *
  2463. * SkMacAutoNegLipaPhy() - Decides whether Link Partner could do auto-neg
  2464. *
  2465. * This function analyses the PHY status word.
  2466. * If any of the Auto-negotiating bits are set, the PLipaAutoNeg variable
  2467. * is set true.
  2468. */
  2469. void SkMacAutoNegLipaPhy(
  2470. SK_AC *pAC, /* adapter context */
  2471. SK_IOC IoC, /* IO context */
  2472. int Port, /* Port Index (MAC_1 + n) */
  2473. SK_U16 PhyStat) /* PHY Status word to analyse */
  2474. {
  2475. SK_GEPORT *pPrt;
  2476. pPrt = &pAC->GIni.GP[Port];
  2477. if (pPrt->PLipaAutoNeg != SK_LIPA_AUTO &&
  2478. (PhyStat & PHY_ST_AN_OVER) != 0) {
  2479. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2480. ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat=0x%04x\n",
  2481. Port, PhyStat));
  2482. pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
  2483. }
  2484. } /* SkMacAutoNegLipaPhy */
  2485. #endif /* SK_DIAG */
  2486. /******************************************************************************
  2487. *
  2488. * SkXmAutoNegDoneXmac() - Auto-negotiation handling
  2489. *
  2490. * Description:
  2491. * This function handles the auto-negotiation if the Done bit is set.
  2492. *
  2493. * Returns:
  2494. * SK_AND_OK o.k.
  2495. * SK_AND_DUP_CAP Duplex capability error happened
  2496. * SK_AND_OTHER Other error happened
  2497. */
  2498. static int SkXmAutoNegDoneXmac(
  2499. SK_AC *pAC, /* adapter context */
  2500. SK_IOC IoC, /* IO context */
  2501. int Port) /* Port Index (MAC_1 + n) */
  2502. {
  2503. SK_GEPORT *pPrt;
  2504. SK_U16 ResAb; /* Resolved Ability */
  2505. SK_U16 LPAb; /* Link Partner Ability */
  2506. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2507. ("AutoNegDoneXmac, Port %d\n",Port));
  2508. pPrt = &pAC->GIni.GP[Port];
  2509. /* Get PHY parameters */
  2510. SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LPAb);
  2511. SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb);
  2512. if ((LPAb & PHY_X_AN_RFB) != 0) {
  2513. /* At least one of the remote fault bit is set */
  2514. /* Error */
  2515. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2516. ("AutoNegFail: Remote fault bit set Port %d\n", Port));
  2517. pPrt->PAutoNegFail = SK_TRUE;
  2518. return(SK_AND_OTHER);
  2519. }
  2520. /* Check Duplex mismatch */
  2521. if ((ResAb & (PHY_X_RS_HD | PHY_X_RS_FD)) == PHY_X_RS_FD) {
  2522. pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL;
  2523. }
  2524. else if ((ResAb & (PHY_X_RS_HD | PHY_X_RS_FD)) == PHY_X_RS_HD) {
  2525. pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF;
  2526. }
  2527. else {
  2528. /* Error */
  2529. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2530. ("AutoNegFail: Duplex mode mismatch Port %d\n", Port));
  2531. pPrt->PAutoNegFail = SK_TRUE;
  2532. return(SK_AND_DUP_CAP);
  2533. }
  2534. /* Check PAUSE mismatch */
  2535. /* We are NOT using chapter 4.23 of the Xaqti manual */
  2536. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  2537. if ((pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC ||
  2538. pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) &&
  2539. (LPAb & PHY_X_P_SYM_MD) != 0) {
  2540. /* Symmetric PAUSE */
  2541. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
  2542. }
  2543. else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM &&
  2544. (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) {
  2545. /* Enable PAUSE receive, disable PAUSE transmit */
  2546. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
  2547. }
  2548. else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND &&
  2549. (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) {
  2550. /* Disable PAUSE receive, enable PAUSE transmit */
  2551. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
  2552. }
  2553. else {
  2554. /* PAUSE mismatch -> no PAUSE */
  2555. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
  2556. }
  2557. pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS;
  2558. return(SK_AND_OK);
  2559. } /* SkXmAutoNegDoneXmac */
  2560. /******************************************************************************
  2561. *
  2562. * SkXmAutoNegDoneBcom() - Auto-negotiation handling
  2563. *
  2564. * Description:
  2565. * This function handles the auto-negotiation if the Done bit is set.
  2566. *
  2567. * Returns:
  2568. * SK_AND_OK o.k.
  2569. * SK_AND_DUP_CAP Duplex capability error happened
  2570. * SK_AND_OTHER Other error happened
  2571. */
  2572. static int SkXmAutoNegDoneBcom(
  2573. SK_AC *pAC, /* adapter context */
  2574. SK_IOC IoC, /* IO context */
  2575. int Port) /* Port Index (MAC_1 + n) */
  2576. {
  2577. SK_GEPORT *pPrt;
  2578. SK_U16 LPAb; /* Link Partner Ability */
  2579. SK_U16 AuxStat; /* Auxiliary Status */
  2580. #if 0
  2581. 01-Sep-2000 RA;:;:
  2582. SK_U16 ResAb; /* Resolved Ability */
  2583. #endif /* 0 */
  2584. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2585. ("AutoNegDoneBcom, Port %d\n", Port));
  2586. pPrt = &pAC->GIni.GP[Port];
  2587. /* Get PHY parameters */
  2588. SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LPAb);
  2589. #if 0
  2590. 01-Sep-2000 RA;:;:
  2591. SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
  2592. #endif /* 0 */
  2593. SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &AuxStat);
  2594. if ((LPAb & PHY_B_AN_RF) != 0) {
  2595. /* Remote fault bit is set: Error */
  2596. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2597. ("AutoNegFail: Remote fault bit set Port %d\n", Port));
  2598. pPrt->PAutoNegFail = SK_TRUE;
  2599. return(SK_AND_OTHER);
  2600. }
  2601. /* Check Duplex mismatch */
  2602. if ((AuxStat & PHY_B_AS_AN_RES_MSK) == PHY_B_RES_1000FD) {
  2603. pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL;
  2604. }
  2605. else if ((AuxStat & PHY_B_AS_AN_RES_MSK) == PHY_B_RES_1000HD) {
  2606. pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF;
  2607. }
  2608. else {
  2609. /* Error */
  2610. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2611. ("AutoNegFail: Duplex mode mismatch Port %d\n", Port));
  2612. pPrt->PAutoNegFail = SK_TRUE;
  2613. return(SK_AND_DUP_CAP);
  2614. }
  2615. #if 0
  2616. 01-Sep-2000 RA;:;:
  2617. /* Check Master/Slave resolution */
  2618. if ((ResAb & PHY_B_1000S_MSF) != 0) {
  2619. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2620. ("Master/Slave Fault Port %d\n", Port));
  2621. pPrt->PAutoNegFail = SK_TRUE;
  2622. pPrt->PMSStatus = SK_MS_STAT_FAULT;
  2623. return(SK_AND_OTHER);
  2624. }
  2625. pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
  2626. SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
  2627. #endif /* 0 */
  2628. /* Check PAUSE mismatch */
  2629. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  2630. if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PAUSE_MSK) {
  2631. /* Symmetric PAUSE */
  2632. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
  2633. }
  2634. else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRR) {
  2635. /* Enable PAUSE receive, disable PAUSE transmit */
  2636. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
  2637. }
  2638. else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRT) {
  2639. /* Disable PAUSE receive, enable PAUSE transmit */
  2640. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
  2641. }
  2642. else {
  2643. /* PAUSE mismatch -> no PAUSE */
  2644. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
  2645. }
  2646. pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS;
  2647. return(SK_AND_OK);
  2648. } /* SkXmAutoNegDoneBcom */
  2649. /******************************************************************************
  2650. *
  2651. * SkGmAutoNegDoneMarv() - Auto-negotiation handling
  2652. *
  2653. * Description:
  2654. * This function handles the auto-negotiation if the Done bit is set.
  2655. *
  2656. * Returns:
  2657. * SK_AND_OK o.k.
  2658. * SK_AND_DUP_CAP Duplex capability error happened
  2659. * SK_AND_OTHER Other error happened
  2660. */
  2661. static int SkGmAutoNegDoneMarv(
  2662. SK_AC *pAC, /* adapter context */
  2663. SK_IOC IoC, /* IO context */
  2664. int Port) /* Port Index (MAC_1 + n) */
  2665. {
  2666. SK_GEPORT *pPrt;
  2667. SK_U16 LPAb; /* Link Partner Ability */
  2668. SK_U16 ResAb; /* Resolved Ability */
  2669. SK_U16 AuxStat; /* Auxiliary Status */
  2670. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2671. ("AutoNegDoneMarv, Port %d\n", Port));
  2672. pPrt = &pAC->GIni.GP[Port];
  2673. /* Get PHY parameters */
  2674. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LPAb);
  2675. if ((LPAb & PHY_M_AN_RF) != 0) {
  2676. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2677. ("AutoNegFail: Remote fault bit set Port %d\n", Port));
  2678. pPrt->PAutoNegFail = SK_TRUE;
  2679. return(SK_AND_OTHER);
  2680. }
  2681. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
  2682. /* Check Master/Slave resolution */
  2683. if ((ResAb & PHY_B_1000S_MSF) != 0) {
  2684. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2685. ("Master/Slave Fault Port %d\n", Port));
  2686. pPrt->PAutoNegFail = SK_TRUE;
  2687. pPrt->PMSStatus = SK_MS_STAT_FAULT;
  2688. return(SK_AND_OTHER);
  2689. }
  2690. pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
  2691. (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
  2692. /* Read PHY Specific Status */
  2693. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &AuxStat);
  2694. /* Check Speed & Duplex resolved */
  2695. if ((AuxStat & PHY_M_PS_SPDUP_RES) == 0) {
  2696. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2697. ("AutoNegFail: Speed & Duplex not resolved Port %d\n", Port));
  2698. pPrt->PAutoNegFail = SK_TRUE;
  2699. pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN;
  2700. return(SK_AND_DUP_CAP);
  2701. }
  2702. if ((AuxStat & PHY_M_PS_FULL_DUP) != 0) {
  2703. pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL;
  2704. }
  2705. else {
  2706. pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF;
  2707. }
  2708. /* Check PAUSE mismatch */
  2709. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  2710. if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_PAUSE_MSK) {
  2711. /* Symmetric PAUSE */
  2712. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
  2713. }
  2714. else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_RX_P_EN) {
  2715. /* Enable PAUSE receive, disable PAUSE transmit */
  2716. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
  2717. }
  2718. else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_TX_P_EN) {
  2719. /* Disable PAUSE receive, enable PAUSE transmit */
  2720. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
  2721. }
  2722. else {
  2723. /* PAUSE mismatch -> no PAUSE */
  2724. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
  2725. }
  2726. /* set used link speed */
  2727. switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
  2728. case (unsigned)PHY_M_PS_SPEED_1000:
  2729. pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_1000MBPS;
  2730. break;
  2731. case PHY_M_PS_SPEED_100:
  2732. pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_100MBPS;
  2733. break;
  2734. default:
  2735. pPrt->PLinkSpeedUsed = SK_LSPEED_STAT_10MBPS;
  2736. }
  2737. return(SK_AND_OK);
  2738. } /* SkGmAutoNegDoneMarv */
  2739. #ifdef OTHER_PHY
  2740. /******************************************************************************
  2741. *
  2742. * SkXmAutoNegDoneLone() - Auto-negotiation handling
  2743. *
  2744. * Description:
  2745. * This function handles the auto-negotiation if the Done bit is set.
  2746. *
  2747. * Returns:
  2748. * SK_AND_OK o.k.
  2749. * SK_AND_DUP_CAP Duplex capability error happened
  2750. * SK_AND_OTHER Other error happened
  2751. */
  2752. static int SkXmAutoNegDoneLone(
  2753. SK_AC *pAC, /* adapter context */
  2754. SK_IOC IoC, /* IO context */
  2755. int Port) /* Port Index (MAC_1 + n) */
  2756. {
  2757. SK_GEPORT *pPrt;
  2758. SK_U16 ResAb; /* Resolved Ability */
  2759. SK_U16 LPAb; /* Link Partner Ability */
  2760. SK_U16 QuickStat; /* Auxiliary Status */
  2761. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2762. ("AutoNegDoneLone, Port %d\n",Port));
  2763. pPrt = &pAC->GIni.GP[Port];
  2764. /* Get PHY parameters */
  2765. SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LPAb);
  2766. SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ResAb);
  2767. SkXmPhyRead(pAC, IoC, Port, PHY_LONE_Q_STAT, &QuickStat);
  2768. if ((LPAb & PHY_L_AN_RF) != 0) {
  2769. /* Remote fault bit is set */
  2770. /* Error */
  2771. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2772. ("AutoNegFail: Remote fault bit set Port %d\n", Port));
  2773. pPrt->PAutoNegFail = SK_TRUE;
  2774. return(SK_AND_OTHER);
  2775. }
  2776. /* Check Duplex mismatch */
  2777. if ((QuickStat & PHY_L_QS_DUP_MOD) != 0) {
  2778. pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL;
  2779. }
  2780. else {
  2781. pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF;
  2782. }
  2783. /* Check Master/Slave resolution */
  2784. if ((ResAb & PHY_L_1000S_MSF) != 0) {
  2785. /* Error */
  2786. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  2787. ("Master/Slave Fault Port %d\n", Port));
  2788. pPrt->PAutoNegFail = SK_TRUE;
  2789. pPrt->PMSStatus = SK_MS_STAT_FAULT;
  2790. return(SK_AND_OTHER);
  2791. }
  2792. else if (ResAb & PHY_L_1000S_MSR) {
  2793. pPrt->PMSStatus = SK_MS_STAT_MASTER;
  2794. }
  2795. else {
  2796. pPrt->PMSStatus = SK_MS_STAT_SLAVE;
  2797. }
  2798. /* Check PAUSE mismatch */
  2799. /* We are using IEEE 802.3z/D5.0 Table 37-4 */
  2800. /* we must manually resolve the abilities here */
  2801. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
  2802. switch (pPrt->PFlowCtrlMode) {
  2803. case SK_FLOW_MODE_NONE:
  2804. /* default */
  2805. break;
  2806. case SK_FLOW_MODE_LOC_SEND:
  2807. if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
  2808. (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) {
  2809. /* Disable PAUSE receive, enable PAUSE transmit */
  2810. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
  2811. }
  2812. break;
  2813. case SK_FLOW_MODE_SYMMETRIC:
  2814. if ((QuickStat & PHY_L_QS_PAUSE) != 0) {
  2815. /* Symmetric PAUSE */
  2816. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
  2817. }
  2818. break;
  2819. case SK_FLOW_MODE_SYM_OR_REM:
  2820. if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
  2821. PHY_L_QS_AS_PAUSE) {
  2822. /* Enable PAUSE receive, disable PAUSE transmit */
  2823. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
  2824. }
  2825. else if ((QuickStat & PHY_L_QS_PAUSE) != 0) {
  2826. /* Symmetric PAUSE */
  2827. pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
  2828. }
  2829. break;
  2830. default:
  2831. SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
  2832. SKERR_HWI_E016MSG);
  2833. }
  2834. return(SK_AND_OK);
  2835. } /* SkXmAutoNegDoneLone */
  2836. /******************************************************************************
  2837. *
  2838. * SkXmAutoNegDoneNat() - Auto-negotiation handling
  2839. *
  2840. * Description:
  2841. * This function handles the auto-negotiation if the Done bit is set.
  2842. *
  2843. * Returns:
  2844. * SK_AND_OK o.k.
  2845. * SK_AND_DUP_CAP Duplex capability error happened
  2846. * SK_AND_OTHER Other error happened
  2847. */
  2848. static int SkXmAutoNegDoneNat(
  2849. SK_AC *pAC, /* adapter context */
  2850. SK_IOC IoC, /* IO context */
  2851. int Port) /* Port Index (MAC_1 + n) */
  2852. {
  2853. /* todo: National */
  2854. return(SK_AND_OK);
  2855. } /* SkXmAutoNegDoneNat */
  2856. #endif /* OTHER_PHY */
  2857. /******************************************************************************
  2858. *
  2859. * SkMacAutoNegDone() - Auto-negotiation handling
  2860. *
  2861. * Description: calls the auto-negotiation done routines dep. on board type
  2862. *
  2863. * Returns:
  2864. * SK_AND_OK o.k.
  2865. * SK_AND_DUP_CAP Duplex capability error happened
  2866. * SK_AND_OTHER Other error happened
  2867. */
  2868. int SkMacAutoNegDone(
  2869. SK_AC *pAC, /* adapter context */
  2870. SK_IOC IoC, /* IO context */
  2871. int Port) /* Port Index (MAC_1 + n) */
  2872. {
  2873. SK_GEPORT *pPrt;
  2874. int Rtv;
  2875. pPrt = &pAC->GIni.GP[Port];
  2876. switch (pPrt->PhyType) {
  2877. case SK_PHY_XMAC:
  2878. Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port);
  2879. break;
  2880. case SK_PHY_BCOM:
  2881. Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port);
  2882. break;
  2883. case SK_PHY_MARV_COPPER:
  2884. case SK_PHY_MARV_FIBER:
  2885. Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port);
  2886. break;
  2887. #ifdef OTHER_PHY
  2888. case SK_PHY_LONE:
  2889. Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port);
  2890. break;
  2891. case SK_PHY_NAT:
  2892. Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port);
  2893. break;
  2894. #endif /* OTHER_PHY */
  2895. default:
  2896. return(SK_AND_OTHER);
  2897. }
  2898. if (Rtv != SK_AND_OK) {
  2899. return(Rtv);
  2900. }
  2901. /* We checked everything and may now enable the link */
  2902. pPrt->PAutoNegFail = SK_FALSE;
  2903. SkMacRxTxEnable(pAC, IoC, Port);
  2904. return(SK_AND_OK);
  2905. } /* SkMacAutoNegDone */
  2906. /******************************************************************************
  2907. *
  2908. * SkXmSetRxTxEn() - Special Set Rx/Tx Enable and some features in XMAC
  2909. *
  2910. * Description:
  2911. * sets MAC or PHY LoopBack and Duplex Mode in the MMU Command Reg.
  2912. * enables Rx/Tx
  2913. *
  2914. * Returns: N/A
  2915. */
  2916. static void SkXmSetRxTxEn(
  2917. SK_AC *pAC, /* Adapter Context */
  2918. SK_IOC IoC, /* IO context */
  2919. int Port, /* Port Index (MAC_1 + n) */
  2920. int Para) /* Parameter to set: MAC or PHY LoopBack, Duplex Mode */
  2921. {
  2922. SK_U16 Word;
  2923. XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
  2924. switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
  2925. case SK_MAC_LOOPB_ON:
  2926. Word |= XM_MMU_MAC_LB;
  2927. break;
  2928. case SK_MAC_LOOPB_OFF:
  2929. Word &= ~XM_MMU_MAC_LB;
  2930. break;
  2931. }
  2932. switch (Para & (SK_PHY_LOOPB_ON | SK_PHY_LOOPB_OFF)) {
  2933. case SK_PHY_LOOPB_ON:
  2934. Word |= XM_MMU_GMII_LOOP;
  2935. break;
  2936. case SK_PHY_LOOPB_OFF:
  2937. Word &= ~XM_MMU_GMII_LOOP;
  2938. break;
  2939. }
  2940. switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
  2941. case SK_PHY_FULLD_ON:
  2942. Word |= XM_MMU_GMII_FD;
  2943. break;
  2944. case SK_PHY_FULLD_OFF:
  2945. Word &= ~XM_MMU_GMII_FD;
  2946. break;
  2947. }
  2948. XM_OUT16(IoC, Port, XM_MMU_CMD, Word | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
  2949. /* dummy read to ensure writing */
  2950. XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
  2951. } /* SkXmSetRxTxEn */
  2952. /******************************************************************************
  2953. *
  2954. * SkGmSetRxTxEn() - Special Set Rx/Tx Enable and some features in GMAC
  2955. *
  2956. * Description:
  2957. * sets MAC LoopBack and Duplex Mode in the General Purpose Control Reg.
  2958. * enables Rx/Tx
  2959. *
  2960. * Returns: N/A
  2961. */
  2962. static void SkGmSetRxTxEn(
  2963. SK_AC *pAC, /* Adapter Context */
  2964. SK_IOC IoC, /* IO context */
  2965. int Port, /* Port Index (MAC_1 + n) */
  2966. int Para) /* Parameter to set: MAC LoopBack, Duplex Mode */
  2967. {
  2968. SK_U16 Ctrl;
  2969. GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl);
  2970. switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
  2971. case SK_MAC_LOOPB_ON:
  2972. Ctrl |= GM_GPCR_LOOP_ENA;
  2973. break;
  2974. case SK_MAC_LOOPB_OFF:
  2975. Ctrl &= ~GM_GPCR_LOOP_ENA;
  2976. break;
  2977. }
  2978. switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
  2979. case SK_PHY_FULLD_ON:
  2980. Ctrl |= GM_GPCR_DUP_FULL;
  2981. break;
  2982. case SK_PHY_FULLD_OFF:
  2983. Ctrl &= ~GM_GPCR_DUP_FULL;
  2984. break;
  2985. }
  2986. GM_OUT16(IoC, Port, GM_GP_CTRL, Ctrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  2987. /* dummy read to ensure writing */
  2988. GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl);
  2989. } /* SkGmSetRxTxEn */
  2990. /******************************************************************************
  2991. *
  2992. * SkMacSetRxTxEn() - Special Set Rx/Tx Enable and parameters
  2993. *
  2994. * Description: calls the Special Set Rx/Tx Enable routines dep. on board type
  2995. *
  2996. * Returns: N/A
  2997. */
  2998. void SkMacSetRxTxEn(
  2999. SK_AC *pAC, /* Adapter Context */
  3000. SK_IOC IoC, /* IO context */
  3001. int Port, /* Port Index (MAC_1 + n) */
  3002. int Para)
  3003. {
  3004. if (pAC->GIni.GIGenesis) {
  3005. SkXmSetRxTxEn(pAC, IoC, Port, Para);
  3006. }
  3007. else {
  3008. SkGmSetRxTxEn(pAC, IoC, Port, Para);
  3009. }
  3010. } /* SkMacSetRxTxEn */
  3011. /******************************************************************************
  3012. *
  3013. * SkMacRxTxEnable() - Enable Rx/Tx activity if port is up
  3014. *
  3015. * Description: enables Rx/Tx dep. on board type
  3016. *
  3017. * Returns:
  3018. * 0 o.k.
  3019. * != 0 Error happened
  3020. */
  3021. int SkMacRxTxEnable(
  3022. SK_AC *pAC, /* adapter context */
  3023. SK_IOC IoC, /* IO context */
  3024. int Port) /* Port Index (MAC_1 + n) */
  3025. {
  3026. SK_GEPORT *pPrt;
  3027. SK_U16 Reg; /* 16-bit register value */
  3028. SK_U16 IntMask; /* MAC interrupt mask */
  3029. SK_U16 SWord;
  3030. pPrt = &pAC->GIni.GP[Port];
  3031. if (!pPrt->PHWLinkUp) {
  3032. /* The Hardware link is NOT up */
  3033. return(0);
  3034. }
  3035. if ((pPrt->PLinkMode == SK_LMODE_AUTOHALF ||
  3036. pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
  3037. pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
  3038. pPrt->PAutoNegFail) {
  3039. /* Auto-negotiation is not done or failed */
  3040. return(0);
  3041. }
  3042. if (pAC->GIni.GIGenesis) {
  3043. /* set Duplex Mode and Pause Mode */
  3044. SkXmInitDupMd(pAC, IoC, Port);
  3045. SkXmInitPauseMd(pAC, IoC, Port);
  3046. /*
  3047. * Initialize the Interrupt Mask Register. Default IRQs are...
  3048. * - Link Asynchronous Event
  3049. * - Link Partner requests config
  3050. * - Auto Negotiation Done
  3051. * - Rx Counter Event Overflow
  3052. * - Tx Counter Event Overflow
  3053. * - Transmit FIFO Underrun
  3054. */
  3055. IntMask = XM_DEF_MSK;
  3056. #ifdef DEBUG
  3057. /* add IRQ for Receive FIFO Overflow */
  3058. IntMask &= ~XM_IS_RXF_OV;
  3059. #endif /* DEBUG */
  3060. if (pPrt->PhyType != SK_PHY_XMAC) {
  3061. /* disable GP0 interrupt bit */
  3062. IntMask |= XM_IS_INP_ASS;
  3063. }
  3064. XM_OUT16(IoC, Port, XM_IMSK, IntMask);
  3065. /* get MMU Command Reg. */
  3066. XM_IN16(IoC, Port, XM_MMU_CMD, &Reg);
  3067. if (pPrt->PhyType != SK_PHY_XMAC &&
  3068. (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
  3069. pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL)) {
  3070. /* set to Full Duplex */
  3071. Reg |= XM_MMU_GMII_FD;
  3072. }
  3073. switch (pPrt->PhyType) {
  3074. case SK_PHY_BCOM:
  3075. /*
  3076. * Workaround BCOM Errata (#10523) for all BCom Phys
  3077. * Enable Power Management after link up
  3078. */
  3079. SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
  3080. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
  3081. (SK_U16)(SWord & ~PHY_B_AC_DIS_PM));
  3082. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
  3083. break;
  3084. #ifdef OTHER_PHY
  3085. case SK_PHY_LONE:
  3086. SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_INT_ENAB, PHY_L_DEF_MSK);
  3087. break;
  3088. case SK_PHY_NAT:
  3089. /* todo National:
  3090. SkXmPhyWrite(pAC, IoC, Port, PHY_NAT_INT_MASK, PHY_N_DEF_MSK); */
  3091. /* no interrupts possible from National ??? */
  3092. break;
  3093. #endif /* OTHER_PHY */
  3094. }
  3095. /* enable Rx/Tx */
  3096. XM_OUT16(IoC, Port, XM_MMU_CMD, Reg | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
  3097. }
  3098. else {
  3099. /*
  3100. * Initialize the Interrupt Mask Register. Default IRQs are...
  3101. * - Rx Counter Event Overflow
  3102. * - Tx Counter Event Overflow
  3103. * - Transmit FIFO Underrun
  3104. */
  3105. IntMask = GMAC_DEF_MSK;
  3106. #ifdef DEBUG
  3107. /* add IRQ for Receive FIFO Overrun */
  3108. IntMask |= GM_IS_RX_FF_OR;
  3109. #endif /* DEBUG */
  3110. SK_OUT8(IoC, GMAC_IRQ_MSK, (SK_U8)IntMask);
  3111. /* get General Purpose Control */
  3112. GM_IN16(IoC, Port, GM_GP_CTRL, &Reg);
  3113. if (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
  3114. pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) {
  3115. /* set to Full Duplex */
  3116. Reg |= GM_GPCR_DUP_FULL;
  3117. }
  3118. /* enable Rx/Tx */
  3119. GM_OUT16(IoC, Port, GM_GP_CTRL, Reg | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  3120. #ifndef VCPU
  3121. /* Enable all PHY interrupts */
  3122. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  3123. #endif /* VCPU */
  3124. }
  3125. return(0);
  3126. } /* SkMacRxTxEnable */
  3127. /******************************************************************************
  3128. *
  3129. * SkMacRxTxDisable() - Disable Receiver and Transmitter
  3130. *
  3131. * Description: disables Rx/Tx dep. on board type
  3132. *
  3133. * Returns: N/A
  3134. */
  3135. void SkMacRxTxDisable(
  3136. SK_AC *pAC, /* Adapter Context */
  3137. SK_IOC IoC, /* IO context */
  3138. int Port) /* Port Index (MAC_1 + n) */
  3139. {
  3140. SK_U16 Word;
  3141. if (pAC->GIni.GIGenesis) {
  3142. XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
  3143. XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
  3144. /* dummy read to ensure writing */
  3145. XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
  3146. }
  3147. else {
  3148. GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
  3149. GM_OUT16(IoC, Port, GM_GP_CTRL, Word & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
  3150. /* dummy read to ensure writing */
  3151. GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
  3152. }
  3153. } /* SkMacRxTxDisable */
  3154. /******************************************************************************
  3155. *
  3156. * SkMacIrqDisable() - Disable IRQ from MAC
  3157. *
  3158. * Description: sets the IRQ-mask to disable IRQ dep. on board type
  3159. *
  3160. * Returns: N/A
  3161. */
  3162. void SkMacIrqDisable(
  3163. SK_AC *pAC, /* Adapter Context */
  3164. SK_IOC IoC, /* IO context */
  3165. int Port) /* Port Index (MAC_1 + n) */
  3166. {
  3167. SK_GEPORT *pPrt;
  3168. SK_U16 Word;
  3169. pPrt = &pAC->GIni.GP[Port];
  3170. if (pAC->GIni.GIGenesis) {
  3171. /* disable all XMAC IRQs */
  3172. XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
  3173. /* Disable all PHY interrupts */
  3174. switch (pPrt->PhyType) {
  3175. case SK_PHY_BCOM:
  3176. /* Make sure that PHY is initialized */
  3177. if (pPrt->PState != SK_PRT_RESET) {
  3178. /* NOT allowed if BCOM is in RESET state */
  3179. /* Workaround BCOM Errata (#10523) all BCom */
  3180. /* Disable Power Management if link is down */
  3181. SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Word);
  3182. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
  3183. (SK_U16)(Word | PHY_B_AC_DIS_PM));
  3184. SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK, 0xffff);
  3185. }
  3186. break;
  3187. #ifdef OTHER_PHY
  3188. case SK_PHY_LONE:
  3189. SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_INT_ENAB, 0);
  3190. break;
  3191. case SK_PHY_NAT:
  3192. /* todo: National
  3193. SkXmPhyWrite(pAC, IoC, Port, PHY_NAT_INT_MASK, 0xffff); */
  3194. break;
  3195. #endif /* OTHER_PHY */
  3196. }
  3197. }
  3198. else {
  3199. /* disable all GMAC IRQs */
  3200. SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
  3201. #ifndef VCPU
  3202. /* Disable all PHY interrupts */
  3203. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
  3204. #endif /* VCPU */
  3205. }
  3206. } /* SkMacIrqDisable */
  3207. #ifdef SK_DIAG
  3208. /******************************************************************************
  3209. *
  3210. * SkXmSendCont() - Enable / Disable Send Continuous Mode
  3211. *
  3212. * Description: enable / disable Send Continuous Mode on XMAC
  3213. *
  3214. * Returns:
  3215. * nothing
  3216. */
  3217. void SkXmSendCont(
  3218. SK_AC *pAC, /* adapter context */
  3219. SK_IOC IoC, /* IO context */
  3220. int Port, /* Port Index (MAC_1 + n) */
  3221. SK_BOOL Enable) /* Enable / Disable */
  3222. {
  3223. SK_U32 MdReg;
  3224. XM_IN32(IoC, Port, XM_MODE, &MdReg);
  3225. if (Enable) {
  3226. MdReg |= XM_MD_TX_CONT;
  3227. }
  3228. else {
  3229. MdReg &= ~XM_MD_TX_CONT;
  3230. }
  3231. /* setup Mode Register */
  3232. XM_OUT32(IoC, Port, XM_MODE, MdReg);
  3233. } /* SkXmSendCont*/
  3234. /******************************************************************************
  3235. *
  3236. * SkMacTimeStamp() - Enable / Disable Time Stamp
  3237. *
  3238. * Description: enable / disable Time Stamp generation for Rx packets
  3239. *
  3240. * Returns:
  3241. * nothing
  3242. */
  3243. void SkMacTimeStamp(
  3244. SK_AC *pAC, /* adapter context */
  3245. SK_IOC IoC, /* IO context */
  3246. int Port, /* Port Index (MAC_1 + n) */
  3247. SK_BOOL Enable) /* Enable / Disable */
  3248. {
  3249. SK_U32 MdReg;
  3250. SK_U8 TimeCtrl;
  3251. if (pAC->GIni.GIGenesis) {
  3252. XM_IN32(IoC, Port, XM_MODE, &MdReg);
  3253. if (Enable) {
  3254. MdReg |= XM_MD_ATS;
  3255. }
  3256. else {
  3257. MdReg &= ~XM_MD_ATS;
  3258. }
  3259. /* setup Mode Register */
  3260. XM_OUT32(IoC, Port, XM_MODE, MdReg);
  3261. }
  3262. else {
  3263. if (Enable) {
  3264. TimeCtrl = GMT_ST_START | GMT_ST_CLR_IRQ;
  3265. }
  3266. else {
  3267. TimeCtrl = GMT_ST_STOP | GMT_ST_CLR_IRQ;
  3268. }
  3269. /* Start/Stop Time Stamp Timer */
  3270. SK_OUT8(pAC, GMAC_TI_ST_CTRL, TimeCtrl);
  3271. }
  3272. } /* SkMacTimeStamp*/
  3273. #else /* SK_DIAG */
  3274. /******************************************************************************
  3275. *
  3276. * SkXmIrq() - Interrupt Service Routine
  3277. *
  3278. * Description: services an Interrupt Request of the XMAC
  3279. *
  3280. * Note:
  3281. * With an external PHY, some interrupt bits are not meaningfull any more:
  3282. * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE
  3283. * - LinkPartnerReqConfig (bit #10) XM_IS_LIPA_RC
  3284. * - Page Received (bit #9) XM_IS_RX_PAGE
  3285. * - NextPageLoadedForXmt (bit #8) XM_IS_TX_PAGE
  3286. * - AutoNegDone (bit #7) XM_IS_AND
  3287. * Also probably not valid any more is the GP0 input bit:
  3288. * - GPRegisterBit0set XM_IS_INP_ASS
  3289. *
  3290. * Returns:
  3291. * nothing
  3292. */
  3293. void SkXmIrq(
  3294. SK_AC *pAC, /* adapter context */
  3295. SK_IOC IoC, /* IO context */
  3296. int Port) /* Port Index (MAC_1 + n) */
  3297. {
  3298. SK_GEPORT *pPrt;
  3299. SK_EVPARA Para;
  3300. SK_U16 IStatus; /* Interrupt status read from the XMAC */
  3301. SK_U16 IStatus2;
  3302. pPrt = &pAC->GIni.GP[Port];
  3303. XM_IN16(IoC, Port, XM_ISRC, &IStatus);
  3304. /* LinkPartner Auto-negable? */
  3305. if (pPrt->PhyType == SK_PHY_XMAC) {
  3306. SkXmAutoNegLipaXmac(pAC, IoC, Port, IStatus);
  3307. }
  3308. else {
  3309. /* mask bits that are not used with ext. PHY */
  3310. IStatus &= ~(XM_IS_LNK_AE | XM_IS_LIPA_RC |
  3311. XM_IS_RX_PAGE | XM_IS_TX_PAGE |
  3312. XM_IS_AND | XM_IS_INP_ASS);
  3313. }
  3314. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
  3315. ("XmacIrq Port %d Isr 0x%04x\n", Port, IStatus));
  3316. if (!pPrt->PHWLinkUp) {
  3317. /* Spurious XMAC interrupt */
  3318. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
  3319. ("SkXmIrq: spurious interrupt on Port %d\n", Port));
  3320. return;
  3321. }
  3322. if ((IStatus & XM_IS_INP_ASS) != 0) {
  3323. /* Reread ISR Register if link is not in sync */
  3324. XM_IN16(IoC, Port, XM_ISRC, &IStatus2);
  3325. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
  3326. ("SkXmIrq: Link async. Double check Port %d 0x%04x 0x%04x\n",
  3327. Port, IStatus, IStatus2));
  3328. IStatus &= ~XM_IS_INP_ASS;
  3329. IStatus |= IStatus2;
  3330. }
  3331. if ((IStatus & XM_IS_LNK_AE) != 0) {
  3332. /* not used, GP0 is used instead */
  3333. }
  3334. if ((IStatus & XM_IS_TX_ABORT) != 0) {
  3335. /* not used */
  3336. }
  3337. if ((IStatus & XM_IS_FRC_INT) != 0) {
  3338. /* not used, use ASIC IRQ instead if needed */
  3339. }
  3340. if ((IStatus & (XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE)) != 0) {
  3341. SkHWLinkDown(pAC, IoC, Port);
  3342. /* Signal to RLMT */
  3343. Para.Para32[0] = (SK_U32)Port;
  3344. SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
  3345. /* Start workaround Errata #2 timer */
  3346. SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME,
  3347. SKGE_HWAC, SK_HWEV_WATIM, Para);
  3348. }
  3349. if ((IStatus & XM_IS_RX_PAGE) != 0) {
  3350. /* not used */
  3351. }
  3352. if ((IStatus & XM_IS_TX_PAGE) != 0) {
  3353. /* not used */
  3354. }
  3355. if ((IStatus & XM_IS_AND) != 0) {
  3356. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
  3357. ("SkXmIrq: AND on link that is up Port %d\n", Port));
  3358. }
  3359. if ((IStatus & XM_IS_TSC_OV) != 0) {
  3360. /* not used */
  3361. }
  3362. /* Combined Tx & Rx Counter Overflow SIRQ Event */
  3363. if ((IStatus & (XM_IS_RXC_OV | XM_IS_TXC_OV)) != 0) {
  3364. Para.Para32[0] = (SK_U32)Port;
  3365. Para.Para32[1] = (SK_U32)IStatus;
  3366. SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para);
  3367. }
  3368. if ((IStatus & XM_IS_RXF_OV) != 0) {
  3369. /* normal situation -> no effect */
  3370. #ifdef DEBUG
  3371. pPrt->PRxOverCnt++;
  3372. #endif /* DEBUG */
  3373. }
  3374. if ((IStatus & XM_IS_TXF_UR) != 0) {
  3375. /* may NOT happen -> error log */
  3376. SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E020, SKERR_SIRQ_E020MSG);
  3377. }
  3378. if ((IStatus & XM_IS_TX_COMP) != 0) {
  3379. /* not served here */
  3380. }
  3381. if ((IStatus & XM_IS_RX_COMP) != 0) {
  3382. /* not served here */
  3383. }
  3384. } /* SkXmIrq */
  3385. /******************************************************************************
  3386. *
  3387. * SkGmIrq() - Interrupt Service Routine
  3388. *
  3389. * Description: services an Interrupt Request of the GMAC
  3390. *
  3391. * Note:
  3392. *
  3393. * Returns:
  3394. * nothing
  3395. */
  3396. void SkGmIrq(
  3397. SK_AC *pAC, /* adapter context */
  3398. SK_IOC IoC, /* IO context */
  3399. int Port) /* Port Index (MAC_1 + n) */
  3400. {
  3401. SK_GEPORT *pPrt;
  3402. SK_EVPARA Para;
  3403. SK_U8 IStatus; /* Interrupt status */
  3404. pPrt = &pAC->GIni.GP[Port];
  3405. SK_IN8(IoC, GMAC_IRQ_SRC, &IStatus);
  3406. /* LinkPartner Auto-negable? */
  3407. SkMacAutoNegLipaPhy(pAC, IoC, Port, IStatus);
  3408. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
  3409. ("GmacIrq Port %d Isr 0x%04x\n", Port, IStatus));
  3410. /* Combined Tx & Rx Counter Overflow SIRQ Event */
  3411. if (IStatus & (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV)) {
  3412. /* these IRQs will be cleared by reading GMACs register */
  3413. Para.Para32[0] = (SK_U32)Port;
  3414. Para.Para32[1] = (SK_U32)IStatus;
  3415. SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para);
  3416. }
  3417. if (IStatus & GM_IS_RX_FF_OR) {
  3418. /* clear GMAC Rx FIFO Overrun IRQ */
  3419. SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FO);
  3420. #ifdef DEBUG
  3421. pPrt->PRxOverCnt++;
  3422. #endif /* DEBUG */
  3423. }
  3424. if (IStatus & GM_IS_TX_FF_UR) {
  3425. /* clear GMAC Tx FIFO Underrun IRQ */
  3426. SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FU);
  3427. /* may NOT happen -> error log */
  3428. SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E020, SKERR_SIRQ_E020MSG);
  3429. }
  3430. if (IStatus & GM_IS_TX_COMPL) {
  3431. /* not served here */
  3432. }
  3433. if (IStatus & GM_IS_RX_COMPL) {
  3434. /* not served here */
  3435. }
  3436. } /* SkGmIrq */
  3437. /******************************************************************************
  3438. *
  3439. * SkMacIrq() - Interrupt Service Routine for MAC
  3440. *
  3441. * Description: calls the Interrupt Service Routine dep. on board type
  3442. *
  3443. * Returns:
  3444. * nothing
  3445. */
  3446. void SkMacIrq(
  3447. SK_AC *pAC, /* adapter context */
  3448. SK_IOC IoC, /* IO context */
  3449. int Port) /* Port Index (MAC_1 + n) */
  3450. {
  3451. if (pAC->GIni.GIGenesis) {
  3452. /* IRQ from XMAC */
  3453. SkXmIrq(pAC, IoC, Port);
  3454. }
  3455. else {
  3456. /* IRQ from GMAC */
  3457. SkGmIrq(pAC, IoC, Port);
  3458. }
  3459. } /* SkMacIrq */
  3460. #endif /* !SK_DIAG */
  3461. /******************************************************************************
  3462. *
  3463. * SkXmUpdateStats() - Force the XMAC to output the current statistic
  3464. *
  3465. * Description:
  3466. * The XMAC holds its statistic internally. To obtain the current
  3467. * values a command must be sent so that the statistic data will
  3468. * be written to a predefined memory area on the adapter.
  3469. *
  3470. * Returns:
  3471. * 0: success
  3472. * 1: something went wrong
  3473. */
  3474. int SkXmUpdateStats(
  3475. SK_AC *pAC, /* adapter context */
  3476. SK_IOC IoC, /* IO context */
  3477. unsigned int Port) /* Port Index (MAC_1 + n) */
  3478. {
  3479. SK_GEPORT *pPrt;
  3480. SK_U16 StatReg;
  3481. int WaitIndex;
  3482. pPrt = &pAC->GIni.GP[Port];
  3483. WaitIndex = 0;
  3484. /* Send an update command to XMAC specified */
  3485. XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
  3486. /*
  3487. * It is an auto-clearing register. If the command bits
  3488. * went to zero again, the statistics are transferred.
  3489. * Normally the command should be executed immediately.
  3490. * But just to be sure we execute a loop.
  3491. */
  3492. do {
  3493. XM_IN16(IoC, Port, XM_STAT_CMD, &StatReg);
  3494. if (++WaitIndex > 10) {
  3495. SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E021, SKERR_HWI_E021MSG);
  3496. return(1);
  3497. }
  3498. } while ((StatReg & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) != 0);
  3499. return(0);
  3500. } /* SkXmUpdateStats */
  3501. /******************************************************************************
  3502. *
  3503. * SkGmUpdateStats() - Force the GMAC to output the current statistic
  3504. *
  3505. * Description:
  3506. * Empty function for GMAC. Statistic data is accessible in direct way.
  3507. *
  3508. * Returns:
  3509. * 0: success
  3510. * 1: something went wrong
  3511. */
  3512. int SkGmUpdateStats(
  3513. SK_AC *pAC, /* adapter context */
  3514. SK_IOC IoC, /* IO context */
  3515. unsigned int Port) /* Port Index (MAC_1 + n) */
  3516. {
  3517. return(0);
  3518. }
  3519. /******************************************************************************
  3520. *
  3521. * SkXmMacStatistic() - Get XMAC counter value
  3522. *
  3523. * Description:
  3524. * Gets the 32bit counter value. Except for the octet counters
  3525. * the lower 32bit are counted in hardware and the upper 32bit
  3526. * must be counted in software by monitoring counter overflow interrupts.
  3527. *
  3528. * Returns:
  3529. * 0: success
  3530. * 1: something went wrong
  3531. */
  3532. int SkXmMacStatistic(
  3533. SK_AC *pAC, /* adapter context */
  3534. SK_IOC IoC, /* IO context */
  3535. unsigned int Port, /* Port Index (MAC_1 + n) */
  3536. SK_U16 StatAddr, /* MIB counter base address */
  3537. SK_U32 *pVal) /* ptr to return statistic value */
  3538. {
  3539. if ((StatAddr < XM_TXF_OK) || (StatAddr > XM_RXF_MAX_SZ)) {
  3540. SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
  3541. return(1);
  3542. }
  3543. XM_IN32(IoC, Port, StatAddr, pVal);
  3544. return(0);
  3545. } /* SkXmMacStatistic */
  3546. /******************************************************************************
  3547. *
  3548. * SkGmMacStatistic() - Get GMAC counter value
  3549. *
  3550. * Description:
  3551. * Gets the 32bit counter value. Except for the octet counters
  3552. * the lower 32bit are counted in hardware and the upper 32bit
  3553. * must be counted in software by monitoring counter overflow interrupts.
  3554. *
  3555. * Returns:
  3556. * 0: success
  3557. * 1: something went wrong
  3558. */
  3559. int SkGmMacStatistic(
  3560. SK_AC *pAC, /* adapter context */
  3561. SK_IOC IoC, /* IO context */
  3562. unsigned int Port, /* Port Index (MAC_1 + n) */
  3563. SK_U16 StatAddr, /* MIB counter base address */
  3564. SK_U32 *pVal) /* ptr to return statistic value */
  3565. {
  3566. if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) {
  3567. SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
  3568. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  3569. ("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr));
  3570. return(1);
  3571. }
  3572. GM_IN32(IoC, Port, StatAddr, pVal);
  3573. return(0);
  3574. } /* SkGmMacStatistic */
  3575. /******************************************************************************
  3576. *
  3577. * SkXmResetCounter() - Clear MAC statistic counter
  3578. *
  3579. * Description:
  3580. * Force the XMAC to clear its statistic counter.
  3581. *
  3582. * Returns:
  3583. * 0: success
  3584. * 1: something went wrong
  3585. */
  3586. int SkXmResetCounter(
  3587. SK_AC *pAC, /* adapter context */
  3588. SK_IOC IoC, /* IO context */
  3589. unsigned int Port) /* Port Index (MAC_1 + n) */
  3590. {
  3591. XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC);
  3592. /* Clear two times according to Errata #3 */
  3593. XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC);
  3594. return(0);
  3595. } /* SkXmResetCounter */
  3596. /******************************************************************************
  3597. *
  3598. * SkGmResetCounter() - Clear MAC statistic counter
  3599. *
  3600. * Description:
  3601. * Force GMAC to clear its statistic counter.
  3602. *
  3603. * Returns:
  3604. * 0: success
  3605. * 1: something went wrong
  3606. */
  3607. int SkGmResetCounter(
  3608. SK_AC *pAC, /* adapter context */
  3609. SK_IOC IoC, /* IO context */
  3610. unsigned int Port) /* Port Index (MAC_1 + n) */
  3611. {
  3612. SK_U16 Reg; /* Phy Address Register */
  3613. SK_U16 Word;
  3614. int i;
  3615. GM_IN16(IoC, Port, GM_PHY_ADDR, &Reg);
  3616. #ifndef VCPU
  3617. /* set MIB Clear Counter Mode */
  3618. GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR);
  3619. /* read all MIB Counters with Clear Mode set */
  3620. for (i = 0; i < GM_MIB_CNT_SIZE; i++) {
  3621. /* the reset is performed only when the lower 16 bits are read */
  3622. GM_IN16(IoC, Port, GM_MIB_CNT_BASE + 8*i, &Word);
  3623. }
  3624. /* clear MIB Clear Counter Mode */
  3625. GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg);
  3626. #endif /* !VCPU */
  3627. return(0);
  3628. } /* SkGmResetCounter */
  3629. /******************************************************************************
  3630. *
  3631. * SkXmOverflowStatus() - Gets the status of counter overflow interrupt
  3632. *
  3633. * Description:
  3634. * Checks the source causing an counter overflow interrupt. On success the
  3635. * resulting counter overflow status is written to <pStatus>, whereas the
  3636. * upper dword stores the XMAC ReceiveCounterEvent register and the lower
  3637. * dword the XMAC TransmitCounterEvent register.
  3638. *
  3639. * Note:
  3640. * For XMAC the interrupt source is a self-clearing register, so the source
  3641. * must be checked only once. SIRQ module does another check to be sure
  3642. * that no interrupt get lost during process time.
  3643. *
  3644. * Returns:
  3645. * 0: success
  3646. * 1: something went wrong
  3647. */
  3648. int SkXmOverflowStatus(
  3649. SK_AC *pAC, /* adapter context */
  3650. SK_IOC IoC, /* IO context */
  3651. unsigned int Port, /* Port Index (MAC_1 + n) */
  3652. SK_U16 IStatus, /* Interupt Status from MAC */
  3653. SK_U64 *pStatus) /* ptr for return overflow status value */
  3654. {
  3655. SK_U64 Status; /* Overflow status */
  3656. SK_U32 RegVal;
  3657. SK_U32 *pRegVal = &RegVal;
  3658. Status = 0;
  3659. if ((IStatus & XM_IS_RXC_OV) != 0) {
  3660. XM_IN32(IoC, Port, XM_RX_CNT_EV, pRegVal);
  3661. Status |= (SK_U64)RegVal << 32;
  3662. }
  3663. if ((IStatus & XM_IS_TXC_OV) != 0) {
  3664. XM_IN32(IoC, Port, XM_TX_CNT_EV, pRegVal);
  3665. Status |= (SK_U64)RegVal;
  3666. }
  3667. *pStatus = Status;
  3668. return(0);
  3669. } /* SkXmOverflowStatus */
  3670. /******************************************************************************
  3671. *
  3672. * SkGmOverflowStatus() - Gets the status of counter overflow interrupt
  3673. *
  3674. * Description:
  3675. * Checks the source causing an counter overflow interrupt. On success the
  3676. * resulting counter overflow status is written to <pStatus>, whereas the
  3677. * the following bit coding is used:
  3678. * 63:56 - unused
  3679. * 55:48 - TxRx interrupt register bit7:0
  3680. * 32:47 - Rx interrupt register
  3681. * 31:24 - unused
  3682. * 23:16 - TxRx interrupt register bit15:8
  3683. * 15:0 - Tx interrupt register
  3684. *
  3685. * Returns:
  3686. * 0: success
  3687. * 1: something went wrong
  3688. */
  3689. int SkGmOverflowStatus(
  3690. SK_AC *pAC, /* adapter context */
  3691. SK_IOC IoC, /* IO context */
  3692. unsigned int Port, /* Port Index (MAC_1 + n) */
  3693. SK_U16 IStatus, /* Interupt Status from MAC */
  3694. SK_U64 *pStatus) /* ptr for return overflow status value */
  3695. {
  3696. SK_U64 Status; /* Overflow status */
  3697. SK_U16 RegVal;
  3698. Status = 0;
  3699. if ((IStatus & GM_IS_RX_CO_OV) != 0) {
  3700. /* this register is self-clearing after read */
  3701. GM_IN16(IoC, Port, GM_RX_IRQ_SRC, &RegVal);
  3702. Status |= (SK_U64)RegVal << 32;
  3703. }
  3704. if ((IStatus & GM_IS_TX_CO_OV) != 0) {
  3705. /* this register is self-clearing after read */
  3706. GM_IN16(IoC, Port, GM_TX_IRQ_SRC, &RegVal);
  3707. Status |= (SK_U64)RegVal;
  3708. }
  3709. /* this register is self-clearing after read */
  3710. GM_IN16(IoC, Port, GM_TR_IRQ_SRC, &RegVal);
  3711. /* Rx overflow interrupt register bits (LoByte)*/
  3712. Status |= (SK_U64)((SK_U8)RegVal) << 48;
  3713. /* Tx overflow interrupt register bits (HiByte)*/
  3714. Status |= (SK_U64)(RegVal >> 8) << 16;
  3715. *pStatus = Status;
  3716. return(0);
  3717. } /* SkGmOverflowStatus */
  3718. /******************************************************************************
  3719. *
  3720. * SkGmCableDiagStatus() - Starts / Gets status of cable diagnostic test
  3721. *
  3722. * Description:
  3723. * starts the cable diagnostic test if 'StartTest' is true
  3724. * gets the results if 'StartTest' is true
  3725. *
  3726. * NOTE: this test is meaningful only when link is down
  3727. *
  3728. * Returns:
  3729. * 0: success
  3730. * 1: no YUKON copper
  3731. * 2: test in progress
  3732. */
  3733. int SkGmCableDiagStatus(
  3734. SK_AC *pAC, /* adapter context */
  3735. SK_IOC IoC, /* IO context */
  3736. int Port, /* Port Index (MAC_1 + n) */
  3737. SK_BOOL StartTest) /* flag for start / get result */
  3738. {
  3739. int i;
  3740. SK_U16 RegVal;
  3741. SK_GEPORT *pPrt;
  3742. pPrt = &pAC->GIni.GP[Port];
  3743. if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
  3744. return(1);
  3745. }
  3746. if (StartTest) {
  3747. /* only start the cable test */
  3748. if ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4) {
  3749. /* apply TDR workaround from Marvell */
  3750. SkGmPhyWrite(pAC, IoC, Port, 29, 0x001e);
  3751. SkGmPhyWrite(pAC, IoC, Port, 30, 0xcc00);
  3752. SkGmPhyWrite(pAC, IoC, Port, 30, 0xc800);
  3753. SkGmPhyWrite(pAC, IoC, Port, 30, 0xc400);
  3754. SkGmPhyWrite(pAC, IoC, Port, 30, 0xc000);
  3755. SkGmPhyWrite(pAC, IoC, Port, 30, 0xc100);
  3756. }
  3757. /* set address to 0 for MDI[0] */
  3758. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
  3759. /* Read Cable Diagnostic Reg */
  3760. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
  3761. /* start Cable Diagnostic Test */
  3762. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CABLE_DIAG,
  3763. (SK_U16)(RegVal | PHY_M_CABD_ENA_TEST));
  3764. return(0);
  3765. }
  3766. /* Read Cable Diagnostic Reg */
  3767. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
  3768. SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
  3769. ("PHY Cable Diag.=0x%04X\n", RegVal));
  3770. if ((RegVal & PHY_M_CABD_ENA_TEST) != 0) {
  3771. /* test is running */
  3772. return(2);
  3773. }
  3774. /* get the test results */
  3775. for (i = 0; i < 4; i++) {
  3776. /* set address to i for MDI[i] */
  3777. SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i);
  3778. /* get Cable Diagnostic values */
  3779. SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
  3780. pPrt->PMdiPairLen[i] = (SK_U8)(RegVal & PHY_M_CABD_DIST_MSK);
  3781. pPrt->PMdiPairSts[i] = (SK_U8)((RegVal & PHY_M_CABD_STAT_MSK) >> 13);
  3782. }
  3783. return(0);
  3784. } /* SkGmCableDiagStatus */
  3785. /* End of file */