mipi_dsim.h 13 KB

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  1. /*
  2. * Copyright (C) 2012 Samsung Electronics
  3. *
  4. * Author: InKi Dae <inki.dae@samsung.com>
  5. * Author: Donghwa Lee <dh09.lee@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #ifndef _DSIM_H
  23. #define _DSIM_H
  24. #include <linux/list.h>
  25. #include <linux/fb.h>
  26. #define PANEL_NAME_SIZE (32)
  27. enum mipi_dsim_interface_type {
  28. DSIM_COMMAND,
  29. DSIM_VIDEO
  30. };
  31. enum mipi_dsim_virtual_ch_no {
  32. DSIM_VIRTUAL_CH_0,
  33. DSIM_VIRTUAL_CH_1,
  34. DSIM_VIRTUAL_CH_2,
  35. DSIM_VIRTUAL_CH_3
  36. };
  37. enum mipi_dsim_burst_mode_type {
  38. DSIM_NON_BURST_SYNC_EVENT,
  39. DSIM_BURST_SYNC_EVENT,
  40. DSIM_NON_BURST_SYNC_PULSE,
  41. DSIM_BURST,
  42. DSIM_NON_VIDEO_MODE
  43. };
  44. enum mipi_dsim_no_of_data_lane {
  45. DSIM_DATA_LANE_1,
  46. DSIM_DATA_LANE_2,
  47. DSIM_DATA_LANE_3,
  48. DSIM_DATA_LANE_4
  49. };
  50. enum mipi_dsim_byte_clk_src {
  51. DSIM_PLL_OUT_DIV8,
  52. DSIM_EXT_CLK_DIV8,
  53. DSIM_EXT_CLK_BYPASS
  54. };
  55. enum mipi_dsim_pixel_format {
  56. DSIM_CMD_3BPP,
  57. DSIM_CMD_8BPP,
  58. DSIM_CMD_12BPP,
  59. DSIM_CMD_16BPP,
  60. DSIM_VID_16BPP_565,
  61. DSIM_VID_18BPP_666PACKED,
  62. DSIM_18BPP_666LOOSELYPACKED,
  63. DSIM_24BPP_888
  64. };
  65. /* MIPI DSI Processor-to-Peripheral transaction types */
  66. enum {
  67. MIPI_DSI_V_SYNC_START = 0x01,
  68. MIPI_DSI_V_SYNC_END = 0x11,
  69. MIPI_DSI_H_SYNC_START = 0x21,
  70. MIPI_DSI_H_SYNC_END = 0x31,
  71. MIPI_DSI_COLOR_MODE_OFF = 0x02,
  72. MIPI_DSI_COLOR_MODE_ON = 0x12,
  73. MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
  74. MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
  75. MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
  76. MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
  77. MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
  78. MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
  79. MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
  80. MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
  81. MIPI_DSI_DCS_SHORT_WRITE = 0x05,
  82. MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
  83. MIPI_DSI_DCS_READ = 0x06,
  84. MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
  85. MIPI_DSI_END_OF_TRANSMISSION = 0x08,
  86. MIPI_DSI_NULL_PACKET = 0x09,
  87. MIPI_DSI_BLANKING_PACKET = 0x19,
  88. MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
  89. MIPI_DSI_DCS_LONG_WRITE = 0x39,
  90. MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
  91. MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
  92. MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
  93. MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
  94. MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
  95. MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
  96. MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
  97. MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
  98. MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
  99. MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
  100. };
  101. /*
  102. * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
  103. *
  104. * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
  105. * @eot_disable: enable or disable EoT packet in HS mode.
  106. * @auto_vertical_cnt: specifies auto vertical count mode.
  107. * in Video mode, the vertical line transition uses line counter
  108. * configured by VSA, VBP, and Vertical resolution.
  109. * If this bit is set to '1', the line counter does not use VSA and VBP
  110. * registers.(in command mode, this variable is ignored)
  111. * @hse: set horizontal sync event mode.
  112. * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
  113. * start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
  114. * this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
  115. * (in mommand mode, this variable is ignored)
  116. * @hfp: specifies HFP disable mode.
  117. * if this variable is set, DSI master ignores HFP area in VIDEO mode.
  118. * (in command mode, this variable is ignored)
  119. * @hbp: specifies HBP disable mode.
  120. * if this variable is set, DSI master ignores HBP area in VIDEO mode.
  121. * (in command mode, this variable is ignored)
  122. * @hsa: specifies HSA disable mode.
  123. * if this variable is set, DSI master ignores HSA area in VIDEO mode.
  124. * (in command mode, this variable is ignored)
  125. * @e_interface: specifies interface to be used.(CPU or RGB interface)
  126. * @e_virtual_ch: specifies virtual channel number that main or
  127. * sub diaplsy uses.
  128. * @e_pixel_format: specifies pixel stream format for main or sub display.
  129. * @e_burst_mode: selects Burst mode in Video mode.
  130. * in Non-burst mode, RGB data area is filled with RGB data and NULL
  131. * packets, according to input bandwidth of RGB interface.
  132. * In Burst mode, RGB data area is filled with RGB data only.
  133. * @e_no_data_lane: specifies data lane count to be used by Master.
  134. * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
  135. * DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
  136. * @pll_stable_time: specifies the PLL Timer for stability of the ganerated
  137. * clock(System clock cycle base)
  138. * if the timer value goes to 0x00000000, the clock stable bit of status
  139. * and interrupt register is set.
  140. * @esc_clk: specifies escape clock frequency for getting the escape clock
  141. * prescaler value.
  142. * @stop_holding_cnt: specifies the interval value between transmitting
  143. * read packet(or write "set_tear_on" command) and BTA request.
  144. * after transmitting read packet or write "set_tear_on" command,
  145. * BTA requests to D-PHY automatically. this counter value specifies
  146. * the interval between them.
  147. * @bta_timeout: specifies the timer for BTA.
  148. * this register specifies time out from BTA request to change
  149. * the direction with respect to Tx escape clock.
  150. * @rx_timeout: specifies the timer for LP Rx mode timeout.
  151. * this register specifies time out on how long RxValid deasserts,
  152. * after RxLpdt asserts with respect to Tx escape clock.
  153. * - RxValid specifies Rx data valid indicator.
  154. * - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
  155. * - RxValid and RxLpdt specifies signal from D-PHY.
  156. */
  157. struct mipi_dsim_config {
  158. unsigned char auto_flush;
  159. unsigned char eot_disable;
  160. unsigned char auto_vertical_cnt;
  161. unsigned char hse;
  162. unsigned char hfp;
  163. unsigned char hbp;
  164. unsigned char hsa;
  165. enum mipi_dsim_interface_type e_interface;
  166. enum mipi_dsim_virtual_ch_no e_virtual_ch;
  167. enum mipi_dsim_pixel_format e_pixel_format;
  168. enum mipi_dsim_burst_mode_type e_burst_mode;
  169. enum mipi_dsim_no_of_data_lane e_no_data_lane;
  170. enum mipi_dsim_byte_clk_src e_byte_clk;
  171. /*
  172. * ===========================================
  173. * | P | M | S | MHz |
  174. * -------------------------------------------
  175. * | 3 | 100 | 3 | 100 |
  176. * | 3 | 100 | 2 | 200 |
  177. * | 3 | 63 | 1 | 252 |
  178. * | 4 | 100 | 1 | 300 |
  179. * | 4 | 110 | 1 | 330 |
  180. * | 12 | 350 | 1 | 350 |
  181. * | 3 | 100 | 1 | 400 |
  182. * | 4 | 150 | 1 | 450 |
  183. * | 6 | 118 | 1 | 472 |
  184. * | 3 | 120 | 1 | 480 |
  185. * | 12 | 250 | 0 | 500 |
  186. * | 4 | 100 | 0 | 600 |
  187. * | 3 | 81 | 0 | 648 |
  188. * | 3 | 88 | 0 | 704 |
  189. * | 3 | 90 | 0 | 720 |
  190. * | 3 | 100 | 0 | 800 |
  191. * | 12 | 425 | 0 | 850 |
  192. * | 4 | 150 | 0 | 900 |
  193. * | 12 | 475 | 0 | 950 |
  194. * | 6 | 250 | 0 | 1000 |
  195. * -------------------------------------------
  196. */
  197. /*
  198. * pms could be calculated as the following.
  199. * M * 24 / P * 2 ^ S = MHz
  200. */
  201. unsigned char p;
  202. unsigned short m;
  203. unsigned char s;
  204. unsigned int pll_stable_time;
  205. unsigned long esc_clk;
  206. unsigned short stop_holding_cnt;
  207. unsigned char bta_timeout;
  208. unsigned short rx_timeout;
  209. };
  210. /*
  211. * struct mipi_dsim_device - global interface for mipi-dsi driver.
  212. *
  213. * @dsim_config: infomation for configuring mipi-dsi controller.
  214. * @master_ops: callbacks to mipi-dsi operations.
  215. * @dsim_lcd_dev: pointer to activated ddi device.
  216. * (it would be registered by mipi-dsi driver.)
  217. * @dsim_lcd_drv: pointer to activated_ddi driver.
  218. * (it would be registered by mipi-dsi driver.)
  219. * @state: specifies status of MIPI-DSI controller.
  220. * the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
  221. * @data_lane: specifiec enabled data lane number.
  222. * this variable would be set by driver according to e_no_data_lane
  223. * automatically.
  224. * @e_clk_src: select byte clock source.
  225. * @pd: pointer to MIPI-DSI driver platform data.
  226. */
  227. struct mipi_dsim_device {
  228. struct mipi_dsim_config *dsim_config;
  229. struct mipi_dsim_master_ops *master_ops;
  230. struct mipi_dsim_lcd_device *dsim_lcd_dev;
  231. struct mipi_dsim_lcd_driver *dsim_lcd_drv;
  232. unsigned int state;
  233. unsigned int data_lane;
  234. enum mipi_dsim_byte_clk_src e_clk_src;
  235. struct exynos_platform_mipi_dsim *pd;
  236. };
  237. /*
  238. * struct exynos_platform_mipi_dsim - interface to platform data
  239. * for mipi-dsi driver.
  240. *
  241. * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
  242. * lcd panel driver searched would be actived.
  243. * @dsim_config: pointer of structure for configuring mipi-dsi controller.
  244. * @lcd_panel_info: pointer for lcd panel specific structure.
  245. * this structure specifies width, height, timing and polarity and so on.
  246. * @lcd_power: callback pointer for enabling or disabling lcd power.
  247. * @mipi_power: callback pointer for enabling or disabling mipi power.
  248. * @phy_enable: pointer to a callback controlling D-PHY enable/reset
  249. */
  250. struct exynos_platform_mipi_dsim {
  251. char lcd_panel_name[PANEL_NAME_SIZE];
  252. struct mipi_dsim_config *dsim_config;
  253. void *lcd_panel_info;
  254. int (*lcd_power)(void);
  255. int (*mipi_power)(void);
  256. void (*phy_enable)(unsigned int dev_index, unsigned int enable);
  257. };
  258. /*
  259. * struct mipi_dsim_master_ops - callbacks to mipi-dsi operations.
  260. *
  261. * @cmd_write: transfer command to lcd panel at LP mode.
  262. * @cmd_read: read command from rx register.
  263. * @get_dsim_frame_done: get the status that all screen data have been
  264. * transferred to mipi-dsi.
  265. * @clear_dsim_frame_done: clear frame done status.
  266. * @get_fb_frame_done: get frame done status of display controller.
  267. * @trigger: trigger display controller.
  268. * - this one would be used only in case of CPU mode.
  269. */
  270. struct mipi_dsim_master_ops {
  271. int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
  272. unsigned int data0, unsigned int data1);
  273. int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
  274. unsigned int data0, unsigned int data1);
  275. int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
  276. int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
  277. int (*get_fb_frame_done)(void);
  278. void (*trigger)(struct fb_info *info);
  279. };
  280. /*
  281. * device structure for mipi-dsi based lcd panel.
  282. *
  283. * @name: name of the device to use with this device, or an
  284. * alias for that name.
  285. * @id: id of device to be registered.
  286. * @bus_id: bus id for identifing connected bus
  287. * and this bus id should be same as id of mipi_dsim_device.
  288. * @master: pointer to mipi-dsi master device object.
  289. * @platform_data: lcd panel specific platform data.
  290. */
  291. struct mipi_dsim_lcd_device {
  292. char *name;
  293. int id;
  294. int bus_id;
  295. struct mipi_dsim_device *master;
  296. void *platform_data;
  297. };
  298. /*
  299. * driver structure for mipi-dsi based lcd panel.
  300. *
  301. * this structure should be registered by lcd panel driver.
  302. * mipi-dsi driver seeks lcd panel registered through name field
  303. * and calls these callback functions in appropriate time.
  304. *
  305. * @name: name of the driver to use with this device, or an
  306. * alias for that name.
  307. * @id: id of driver to be registered.
  308. * this id would be used for finding device object registered.
  309. * @mipi_panel_init: callback pointer for initializing lcd panel based on mipi
  310. * dsi interface.
  311. * @mipi_display_on: callback pointer for lcd panel display on.
  312. */
  313. struct mipi_dsim_lcd_driver {
  314. char *name;
  315. int id;
  316. int (*mipi_panel_init)(struct mipi_dsim_device *dsim_dev);
  317. void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
  318. };
  319. int exynos_mipi_dsi_init(void);
  320. /*
  321. * register mipi_dsim_lcd_driver object defined by lcd panel driver
  322. * to mipi-dsi driver.
  323. */
  324. int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
  325. *lcd_drv);
  326. /*
  327. * register mipi_dsim_lcd_device to mipi-dsi master.
  328. */
  329. int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
  330. *lcd_dev);
  331. void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
  332. /* panel driver init based on mipi dsi interface */
  333. void s6e8ax0_init(void);
  334. #endif /* _DSIM_H */