load.c 4.0 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. /*
  25. * CPU test
  26. * Load instructions: lbz(x)(u), lhz(x)(u), lha(x)(u), lwz(x)(u)
  27. *
  28. * All operations are performed on a 16-byte array. The array
  29. * is 4-byte aligned. The base register points to offset 8.
  30. * The immediate offset (index register) ranges in [-8 ... +7].
  31. * The test cases are composed so that they do not
  32. * cause alignment exceptions.
  33. * The test contains a pre-built table describing all test cases.
  34. * The table entry contains:
  35. * the instruction opcode, the array contents, the value of the index
  36. * register and the expected value of the destination register.
  37. * After executing the instruction, the test verifies the
  38. * value of the destination register and the value of the base
  39. * register (it must change for "load with update" instructions).
  40. */
  41. #ifdef CONFIG_POST
  42. #include <post.h>
  43. #include "cpu_asm.h"
  44. #if CONFIG_POST & CFG_POST_CPU
  45. extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3);
  46. extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2);
  47. static struct cpu_post_load_s
  48. {
  49. ulong cmd;
  50. uint width;
  51. int update;
  52. int index;
  53. ulong offset;
  54. } cpu_post_load_table[] =
  55. {
  56. {
  57. OP_LWZ,
  58. 4,
  59. 0,
  60. 0,
  61. 4
  62. },
  63. {
  64. OP_LHA,
  65. 3,
  66. 0,
  67. 0,
  68. 2
  69. },
  70. {
  71. OP_LHZ,
  72. 2,
  73. 0,
  74. 0,
  75. 2
  76. },
  77. {
  78. OP_LBZ,
  79. 1,
  80. 0,
  81. 0,
  82. 1
  83. },
  84. {
  85. OP_LWZU,
  86. 4,
  87. 1,
  88. 0,
  89. 4
  90. },
  91. {
  92. OP_LHAU,
  93. 3,
  94. 1,
  95. 0,
  96. 2
  97. },
  98. {
  99. OP_LHZU,
  100. 2,
  101. 1,
  102. 0,
  103. 2
  104. },
  105. {
  106. OP_LBZU,
  107. 1,
  108. 1,
  109. 0,
  110. 1
  111. },
  112. {
  113. OP_LWZX,
  114. 4,
  115. 0,
  116. 1,
  117. 4
  118. },
  119. {
  120. OP_LHAX,
  121. 3,
  122. 0,
  123. 1,
  124. 2
  125. },
  126. {
  127. OP_LHZX,
  128. 2,
  129. 0,
  130. 1,
  131. 2
  132. },
  133. {
  134. OP_LBZX,
  135. 1,
  136. 0,
  137. 1,
  138. 1
  139. },
  140. {
  141. OP_LWZUX,
  142. 4,
  143. 1,
  144. 1,
  145. 4
  146. },
  147. {
  148. OP_LHAUX,
  149. 3,
  150. 1,
  151. 1,
  152. 2
  153. },
  154. {
  155. OP_LHZUX,
  156. 2,
  157. 1,
  158. 1,
  159. 2
  160. },
  161. {
  162. OP_LBZUX,
  163. 1,
  164. 1,
  165. 1,
  166. 1
  167. },
  168. };
  169. static unsigned int cpu_post_load_size =
  170. sizeof (cpu_post_load_table) / sizeof (struct cpu_post_load_s);
  171. int cpu_post_test_load (void)
  172. {
  173. int ret = 0;
  174. unsigned int i;
  175. for (i = 0; i < cpu_post_load_size && ret == 0; i++)
  176. {
  177. struct cpu_post_load_s *test = cpu_post_load_table + i;
  178. uchar data[16] =
  179. { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
  180. ulong base0 = (ulong) (data + 8);
  181. ulong base = base0;
  182. ulong value;
  183. if (test->index)
  184. {
  185. ulong code[] =
  186. {
  187. ASM_12(test->cmd, 5, 3, 4),
  188. ASM_BLR,
  189. };
  190. cpu_post_exec_22w (code, &base, test->offset, &value);
  191. }
  192. else
  193. {
  194. ulong code[] =
  195. {
  196. ASM_11I(test->cmd, 4, 3, test->offset),
  197. ASM_BLR,
  198. };
  199. cpu_post_exec_21w (code, &base, &value);
  200. }
  201. if (ret == 0)
  202. {
  203. if (test->update)
  204. ret = base == base0 + test->offset ? 0 : -1;
  205. else
  206. ret = base == base0 ? 0 : -1;
  207. }
  208. if (ret == 0)
  209. {
  210. switch (test->width)
  211. {
  212. case 1:
  213. ret = *(uchar *)(base0 + test->offset) == value ?
  214. 0 : -1;
  215. break;
  216. case 2:
  217. ret = *(ushort *)(base0 + test->offset) == value ?
  218. 0 : -1;
  219. break;
  220. case 3:
  221. ret = *(short *)(base0 + test->offset) == value ?
  222. 0 : -1;
  223. break;
  224. case 4:
  225. ret = *(ulong *)(base0 + test->offset) == value ?
  226. 0 : -1;
  227. break;
  228. }
  229. }
  230. if (ret != 0)
  231. {
  232. post_log ("Error at load test %d !\n", i);
  233. }
  234. }
  235. return ret;
  236. }
  237. #endif
  238. #endif