Página Principal Explorar Ajuda
Registe-se Iniciar Sessão
phyus
/
uboot-vybrid_public
8
0
Fork 0
Ficheiros Problemas 0 Pull Requests 0 Wiki
Árvore: 2c05fd1257
Ramos Etiquetas
uboot-vybrid_pu...
/
include
/
405gp_pci.h

405gp_pci.h 2.0 KB
Histórico Em bruto

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152 
  1. #ifndef _405GP_PCI_H
    2. 

  2. #define _405GP_PCI_H
    3. 

  3. 

  4. /*----------------------------------------------------------------------------+
    5. 

  5. | 405GP PCI core memory map defines.
    6. 

  6. +----------------------------------------------------------------------------*/
    7. 

  7. #define MIN_PCI_MEMADDR1    0x80000000
    8. 

  8. #define MIN_PCI_MEMADDR2    0x00000000
    9. 

  9. #define MIN_PLB_PCI_IOADDR  0xE8000000  /* PLB side of PCI I/O address space */
    10. 

  10. #define MIN_PCI_PCI_IOADDR  0x00000000  /* PCI side of PCI I/O address space */
    11. 

  11. #define MAX_PCI_DEVICES     32
    12. 

  12. 

  13. /*----------------------------------------------------------------------------+
    14. 

  14. | Defines for the 405GP PCI Config address and data registers followed by
    15. 

  15. | defines for the standard PCI device configuration header.
    16. 

  16. +----------------------------------------------------------------------------*/
    17. 

  17. #define PCICFGADR       0xEEC00000
    18. 

  18. #define PCICFGDATA      0xEEC00004
    19. 

  19. 

  20. #define PCIBUSNUM       0x40        /* 405GP specific parameters */
    21. 

  21. #define PCISUBBUSNUM    0x41
    22. 

  22. #define PCIDISCOUNT     0x42
    23. 

  23. #define PCIBRDGOPT1     0x4A
    24. 

  24. #define PCIBRDGOPT2     0x60
    25. 

  25. 

  26. /*----------------------------------------------------------------------------+
    27. 

  27. | Defines for 405GP PCI Master local configuration regs.
    28. 

  28. +----------------------------------------------------------------------------*/
    29. 

  29. #define PMM0LA          0xEF400000
    30. 

  30. #define PMM0MA          0xEF400004
    31. 

  31. #define PMM0PCILA       0xEF400008
    32. 

  32. #define PMM0PCIHA       0xEF40000C
    33. 

  33. #define PMM1LA          0xEF400010
    34. 

  34. #define PMM1MA          0xEF400014
    35. 

  35. #define PMM1PCILA       0xEF400018
    36. 

  36. #define PMM1PCIHA       0xEF40001C
    37. 

  37. #define PMM2LA          0xEF400020
    38. 

  38. #define PMM2MA          0xEF400024
    39. 

  39. #define PMM2PCILA       0xEF400028
    40. 

  40. #define PMM2PCIHA       0xEF40002C
    41. 

  41. 

  42. /*----------------------------------------------------------------------------+
    43. 

  43. | Defines for 405GP PCI Target local configuration regs.
    44. 

  44. +----------------------------------------------------------------------------*/
    45. 

  45. #define PTM1MS          0xEF400030
    46. 

  46. #define PTM1LA          0xEF400034
    47. 

  47. #define PTM2MS          0xEF400038
    48. 

  48. #define PTM2LA          0xEF40003C
    49. 

  49. 

  50. #define PCIDEVID_405GP 	0x0
    51. 

  51. 

  52. #endif
    53.