bcm570x.c 45 KB

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  1. /*
  2. * Broadcom BCM570x Ethernet Driver for U-Boot.
  3. * Support 5701, 5702, 5703, and 5704. Single instance driver.
  4. * Copyright (C) 2002 James F. Dougherty (jfd@broadcom.com)
  5. */
  6. #include <common.h>
  7. #if defined(CONFIG_CMD_NET) \
  8. && (!defined(CONFIG_NET_MULTI)) && defined(CONFIG_BCM570x)
  9. #ifdef CONFIG_BMW
  10. #include <mpc824x.h>
  11. #endif
  12. #include <net.h>
  13. #include "bcm570x_mm.h"
  14. #include "bcm570x_autoneg.h"
  15. #include <pci.h>
  16. #include <malloc.h>
  17. /*
  18. * PCI Registers and definitions.
  19. */
  20. #define PCI_CMD_MASK 0xffff0000 /* mask to save status bits */
  21. #define PCI_ANY_ID (~0)
  22. /*
  23. * PCI memory base for Ethernet device as well as device Interrupt.
  24. */
  25. #define BCM570X_MBAR 0x80100000
  26. #define BCM570X_ILINE 1
  27. #define SECOND_USEC 1000000
  28. #define MAX_PACKET_SIZE 1600
  29. #define MAX_UNITS 4
  30. /* Globals to this module */
  31. int initialized = 0;
  32. unsigned int ioBase = 0;
  33. volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */
  34. volatile PUM_DEVICE_BLOCK pUmDevice = NULL;
  35. /* Used to pass the full-duplex flag, etc. */
  36. int line_speed[MAX_UNITS] = {0,0,0,0};
  37. static int full_duplex[MAX_UNITS] = {1,1,1,1};
  38. static int rx_flow_control[MAX_UNITS] = {0,0,0,0};
  39. static int tx_flow_control[MAX_UNITS] = {0,0,0,0};
  40. static int auto_flow_control[MAX_UNITS] = {0,0,0,0};
  41. static int tx_checksum[MAX_UNITS] = {1,1,1,1};
  42. static int rx_checksum[MAX_UNITS] = {1,1,1,1};
  43. static int auto_speed[MAX_UNITS] = {1,1,1,1};
  44. #if JUMBO_FRAMES
  45. /* Jumbo MTU for interfaces. */
  46. static int mtu[MAX_UNITS] = {0,0,0,0};
  47. #endif
  48. /* Turn on Wake-on lan for a device unit */
  49. static int enable_wol[MAX_UNITS] = {0,0,0,0};
  50. #define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT
  51. static unsigned int tx_pkt_desc_cnt[MAX_UNITS] =
  52. {TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, TX_DESC_CNT};
  53. #define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT
  54. static unsigned int rx_std_desc_cnt[MAX_UNITS] =
  55. {RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT};
  56. static unsigned int rx_adaptive_coalesce[MAX_UNITS] = {1,1,1,1};
  57. #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
  58. #define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT
  59. static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] =
  60. {JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT};
  61. #endif
  62. #define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS
  63. static unsigned int rx_coalesce_ticks[MAX_UNITS] =
  64. {RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK};
  65. #define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES
  66. static unsigned int rx_max_coalesce_frames[MAX_UNITS] =
  67. {RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM};
  68. #define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS
  69. static unsigned int tx_coalesce_ticks[MAX_UNITS] =
  70. {TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK};
  71. #define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES
  72. static unsigned int tx_max_coalesce_frames[MAX_UNITS] =
  73. {TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM};
  74. #define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS
  75. static unsigned int stats_coalesce_ticks[MAX_UNITS] =
  76. {ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK};
  77. /*
  78. * Legitimate values for BCM570x device types
  79. */
  80. typedef enum {
  81. BCM5700VIGIL = 0,
  82. BCM5700A6,
  83. BCM5700T6,
  84. BCM5700A9,
  85. BCM5700T9,
  86. BCM5700,
  87. BCM5701A5,
  88. BCM5701T1,
  89. BCM5701T8,
  90. BCM5701A7,
  91. BCM5701A10,
  92. BCM5701A12,
  93. BCM5701,
  94. BCM5702,
  95. BCM5703,
  96. BCM5703A31,
  97. TC996T,
  98. TC996ST,
  99. TC996SSX,
  100. TC996SX,
  101. TC996BT,
  102. TC997T,
  103. TC997SX,
  104. TC1000T,
  105. TC940BR01,
  106. TC942BR01,
  107. NC6770,
  108. NC7760,
  109. NC7770,
  110. NC7780
  111. } board_t;
  112. /* Chip-Rev names for each device-type */
  113. static struct {
  114. char* name;
  115. } chip_rev[] = {
  116. {"BCM5700VIGIL"},
  117. {"BCM5700A6"},
  118. {"BCM5700T6"},
  119. {"BCM5700A9"},
  120. {"BCM5700T9"},
  121. {"BCM5700"},
  122. {"BCM5701A5"},
  123. {"BCM5701T1"},
  124. {"BCM5701T8"},
  125. {"BCM5701A7"},
  126. {"BCM5701A10"},
  127. {"BCM5701A12"},
  128. {"BCM5701"},
  129. {"BCM5702"},
  130. {"BCM5703"},
  131. {"BCM5703A31"},
  132. {"TC996T"},
  133. {"TC996ST"},
  134. {"TC996SSX"},
  135. {"TC996SX"},
  136. {"TC996BT"},
  137. {"TC997T"},
  138. {"TC997SX"},
  139. {"TC1000T"},
  140. {"TC940BR01"},
  141. {"TC942BR01"},
  142. {"NC6770"},
  143. {"NC7760"},
  144. {"NC7770"},
  145. {"NC7780"},
  146. {0}
  147. };
  148. /* indexed by board_t, above */
  149. static struct {
  150. char *name;
  151. } board_info[] = {
  152. { "Broadcom Vigil B5700 1000Base-T" },
  153. { "Broadcom BCM5700 1000Base-T" },
  154. { "Broadcom BCM5700 1000Base-SX" },
  155. { "Broadcom BCM5700 1000Base-SX" },
  156. { "Broadcom BCM5700 1000Base-T" },
  157. { "Broadcom BCM5700" },
  158. { "Broadcom BCM5701 1000Base-T" },
  159. { "Broadcom BCM5701 1000Base-T" },
  160. { "Broadcom BCM5701 1000Base-T" },
  161. { "Broadcom BCM5701 1000Base-SX" },
  162. { "Broadcom BCM5701 1000Base-T" },
  163. { "Broadcom BCM5701 1000Base-T" },
  164. { "Broadcom BCM5701" },
  165. { "Broadcom BCM5702 1000Base-T" },
  166. { "Broadcom BCM5703 1000Base-T" },
  167. { "Broadcom BCM5703 1000Base-SX" },
  168. { "3Com 3C996 10/100/1000 Server NIC" },
  169. { "3Com 3C996 10/100/1000 Server NIC" },
  170. { "3Com 3C996 Gigabit Fiber-SX Server NIC" },
  171. { "3Com 3C996 Gigabit Fiber-SX Server NIC" },
  172. { "3Com 3C996B Gigabit Server NIC" },
  173. { "3Com 3C997 Gigabit Server NIC" },
  174. { "3Com 3C997 Gigabit Fiber-SX Server NIC" },
  175. { "3Com 3C1000 Gigabit NIC" },
  176. { "3Com 3C940 Gigabit LOM (21X21)" },
  177. { "3Com 3C942 Gigabit LOM (31X31)" },
  178. { "Compaq NC6770 Gigabit Server Adapter" },
  179. { "Compaq NC7760 Gigabit Server Adapter" },
  180. { "Compaq NC7770 Gigabit Server Adapter" },
  181. { "Compaq NC7780 Gigabit Server Adapter" },
  182. { 0 },
  183. };
  184. /* PCI Devices which use the 570x chipset */
  185. struct pci_device_table {
  186. unsigned short vendor_id, device_id; /* Vendor/DeviceID */
  187. unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
  188. unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
  189. unsigned long board_id; /* Data private to the driver */
  190. int io_size, min_latency;
  191. } bcm570xDevices[] = {
  192. {0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL ,128,32},
  193. {0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6 ,128,32},
  194. {0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6 ,128,32},
  195. {0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9 ,128,32},
  196. {0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9 ,128,32},
  197. {0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700 ,128,32},
  198. {0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700 ,128,32},
  199. {0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700 ,128,32},
  200. {0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700 ,128,32},
  201. {0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T ,128,32},
  202. {0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST ,128,32},
  203. {0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX ,128,32},
  204. {0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T ,128,32},
  205. {0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX ,128,32},
  206. {0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01 ,128,32},
  207. {0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700 ,128,32},
  208. {0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5 ,128,32},
  209. {0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1 ,128,32},
  210. {0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8 ,128,32},
  211. {0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7 ,128,32},
  212. {0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10 ,128,32},
  213. {0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12 ,128,32},
  214. {0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770 ,128,32},
  215. {0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770 ,128,32},
  216. {0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780 ,128,32},
  217. {0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701 ,128,32},
  218. {0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX ,128,32},
  219. {0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT ,128,32},
  220. {0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T ,128,32},
  221. {0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01 ,128,32},
  222. {0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701 ,128,32},
  223. {0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32},
  224. {0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32},
  225. {0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32},
  226. {0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32},
  227. {0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32},
  228. {0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32},
  229. {0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32},
  230. {0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32},
  231. {0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32},
  232. {0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32},
  233. {0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32},
  234. {0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780 ,128,32},
  235. {0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32},
  236. {0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32},
  237. {0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32},
  238. {0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32},
  239. {0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32},
  240. {0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32},
  241. {0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780 ,128,32},
  242. {0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32}
  243. };
  244. #define n570xDevices (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0]))
  245. /*
  246. * Allocate a packet buffer from the bcm570x packet pool.
  247. */
  248. void *
  249. bcm570xPktAlloc(int u, int pksize)
  250. {
  251. return malloc(pksize);
  252. }
  253. /*
  254. * Free a packet previously allocated from the bcm570x packet
  255. * buffer pool.
  256. */
  257. void
  258. bcm570xPktFree(int u, void *p)
  259. {
  260. free(p);
  261. }
  262. int
  263. bcm570xReplenishRxBuffers(PUM_DEVICE_BLOCK pUmDevice)
  264. {
  265. PLM_PACKET pPacket;
  266. PUM_PACKET pUmPacket;
  267. void *skb;
  268. int queue_rx = 0;
  269. int ret = 0;
  270. while ((pUmPacket = (PUM_PACKET)
  271. QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) != 0) {
  272. pPacket = (PLM_PACKET) pUmPacket;
  273. /* reuse an old skb */
  274. if (pUmPacket->skbuff) {
  275. QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
  276. queue_rx = 1;
  277. continue;
  278. }
  279. if ( ( skb = bcm570xPktAlloc(pUmDevice->index,
  280. pPacket->u.Rx.RxBufferSize + 2)) == 0) {
  281. QQ_PushHead(&pUmDevice->rx_out_of_buf_q.Container,pPacket);
  282. printf("NOTICE: Out of RX memory.\n");
  283. ret = 1;
  284. break;
  285. }
  286. pUmPacket->skbuff = skb;
  287. QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
  288. queue_rx = 1;
  289. }
  290. if (queue_rx) {
  291. LM_QueueRxPackets(pDevice);
  292. }
  293. return ret;
  294. }
  295. /*
  296. * Probe, Map, and Init 570x device.
  297. */
  298. int eth_init(bd_t *bis)
  299. {
  300. int i, rv, devFound = FALSE;
  301. pci_dev_t devbusfn;
  302. unsigned short status;
  303. /* Find PCI device, if it exists, configure ... */
  304. for( i = 0; i < n570xDevices; i++){
  305. devbusfn = pci_find_device(bcm570xDevices[i].vendor_id,
  306. bcm570xDevices[i].device_id, 0);
  307. if(devbusfn == -1) {
  308. continue; /* No device of that vendor/device ID */
  309. } else {
  310. /* Set ILINE */
  311. pci_write_config_byte(devbusfn,
  312. PCI_INTERRUPT_LINE, BCM570X_ILINE);
  313. /*
  314. * 0x10 - 0x14 define one 64-bit MBAR.
  315. * 0x14 is the higher-order address bits of the BAR.
  316. */
  317. pci_write_config_dword(devbusfn,
  318. PCI_BASE_ADDRESS_1, 0);
  319. ioBase = BCM570X_MBAR;
  320. pci_write_config_dword(devbusfn,
  321. PCI_BASE_ADDRESS_0, ioBase);
  322. /*
  323. * Enable PCI memory, IO, and Master -- don't
  324. * reset any status bits in doing so.
  325. */
  326. pci_read_config_word(devbusfn,
  327. PCI_COMMAND, &status);
  328. status |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
  329. pci_write_config_word(devbusfn,
  330. PCI_COMMAND, status);
  331. printf("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n",
  332. board_info[bcm570xDevices[i].board_id].name,
  333. PCI_BUS(devbusfn),
  334. PCI_DEV(devbusfn),
  335. PCI_FUNC(devbusfn),
  336. ioBase);
  337. /* Allocate once, but always clear on init */
  338. if (!pDevice) {
  339. pDevice = malloc(sizeof(UM_DEVICE_BLOCK));
  340. pUmDevice = (PUM_DEVICE_BLOCK)pDevice;
  341. memset(pDevice, 0x0, sizeof(UM_DEVICE_BLOCK));
  342. }
  343. /* Configure pci dev structure */
  344. pUmDevice->pdev = devbusfn;
  345. pUmDevice->index = 0;
  346. pUmDevice->tx_pkt = 0;
  347. pUmDevice->rx_pkt = 0;
  348. devFound = TRUE;
  349. break;
  350. }
  351. }
  352. if(!devFound){
  353. printf("eth_init: FAILURE: no BCM570x Ethernet devices found.\n");
  354. return -1;
  355. }
  356. /* Setup defaults for chip */
  357. pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
  358. if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
  359. pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
  360. } else {
  361. if (rx_checksum[i]) {
  362. pDevice->TaskToOffload |=
  363. LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
  364. LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
  365. }
  366. if (tx_checksum[i]) {
  367. pDevice->TaskToOffload |=
  368. LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
  369. LM_TASK_OFFLOAD_TX_UDP_CHECKSUM;
  370. pDevice->NoTxPseudoHdrChksum = TRUE;
  371. }
  372. }
  373. /* Set Device PCI Memory base address */
  374. pDevice->pMappedMemBase = (PLM_UINT8) ioBase;
  375. /* Pull down adapter info */
  376. if ((rv = LM_GetAdapterInfo(pDevice)) != LM_STATUS_SUCCESS) {
  377. printf("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv );
  378. return -2;
  379. }
  380. /* Lock not needed */
  381. pUmDevice->do_global_lock = 0;
  382. if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) {
  383. /* The 5700 chip works best without interleaved register */
  384. /* accesses on certain machines. */
  385. pUmDevice->do_global_lock = 1;
  386. }
  387. /* Setup timer delays */
  388. if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) {
  389. pDevice->UseTaggedStatus = TRUE;
  390. pUmDevice->timer_interval = CFG_HZ;
  391. }
  392. else {
  393. pUmDevice->timer_interval = CFG_HZ / 50;
  394. }
  395. /* Grab name .... */
  396. pUmDevice->name =
  397. (char*)malloc(strlen(board_info[bcm570xDevices[i].board_id].name)+1);
  398. strcpy(pUmDevice->name,board_info[bcm570xDevices[i].board_id].name);
  399. memcpy(pDevice->NodeAddress, bis->bi_enetaddr, 6);
  400. LM_SetMacAddress(pDevice, bis->bi_enetaddr);
  401. /* Init queues .. */
  402. QQ_InitQueue(&pUmDevice->rx_out_of_buf_q.Container,
  403. MAX_RX_PACKET_DESC_COUNT);
  404. pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0;
  405. /* delay for 4 seconds */
  406. pUmDevice->delayed_link_ind =
  407. (4 * CFG_HZ) / pUmDevice->timer_interval;
  408. pUmDevice->adaptive_expiry =
  409. CFG_HZ / pUmDevice->timer_interval;
  410. /* Sometimes we get spurious ints. after reset when link is down. */
  411. /* This field tells the isr to service the int. even if there is */
  412. /* no status block update. */
  413. pUmDevice->adapter_just_inited =
  414. (3 * CFG_HZ) / pUmDevice->timer_interval;
  415. /* Initialize 570x */
  416. if (LM_InitializeAdapter(pDevice) != LM_STATUS_SUCCESS) {
  417. printf("ERROR: Adapter initialization failed.\n");
  418. return ERROR;
  419. }
  420. /* Enable chip ISR */
  421. LM_EnableInterrupt(pDevice);
  422. /* Clear MC table */
  423. LM_MulticastClear(pDevice);
  424. /* Enable Multicast */
  425. LM_SetReceiveMask(pDevice,
  426. pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST);
  427. pUmDevice->opened = 1;
  428. pUmDevice->tx_full = 0;
  429. pUmDevice->tx_pkt = 0;
  430. pUmDevice->rx_pkt = 0;
  431. printf("eth%d: %s @0x%lx,",
  432. pDevice->index, pUmDevice->name, (unsigned long)ioBase);
  433. printf( "node addr ");
  434. for (i = 0; i < 6; i++) {
  435. printf("%2.2x", pDevice->NodeAddress[i]);
  436. }
  437. printf("\n");
  438. printf("eth%d: ", pDevice->index);
  439. printf("%s with ",
  440. chip_rev[bcm570xDevices[i].board_id].name);
  441. if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID)
  442. printf("Broadcom BCM5400 Copper ");
  443. else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
  444. printf("Broadcom BCM5401 Copper ");
  445. else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID)
  446. printf("Broadcom BCM5411 Copper ");
  447. else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID)
  448. printf("Broadcom BCM5701 Integrated Copper ");
  449. else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID)
  450. printf("Broadcom BCM5703 Integrated Copper ");
  451. else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID)
  452. printf("Broadcom BCM8002 SerDes ");
  453. else if (pDevice->EnableTbi)
  454. printf("Agilent HDMP-1636 SerDes ");
  455. else
  456. printf("Unknown ");
  457. printf("transceiver found\n");
  458. printf("eth%d: %s, MTU: %d,",
  459. pDevice->index, pDevice->BusSpeedStr, 1500);
  460. if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) &&
  461. rx_checksum[i])
  462. printf("Rx Checksum ON\n");
  463. else
  464. printf("Rx Checksum OFF\n");
  465. initialized++;
  466. return 0;
  467. }
  468. /* Ethernet Interrupt service routine */
  469. void
  470. eth_isr(void)
  471. {
  472. LM_UINT32 oldtag, newtag;
  473. int i;
  474. pUmDevice->interrupt = 1;
  475. if (pDevice->UseTaggedStatus) {
  476. if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) ||
  477. pUmDevice->adapter_just_inited) {
  478. MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
  479. oldtag = pDevice->pStatusBlkVirt->StatusTag;
  480. for (i = 0; ; i++) {
  481. pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED;
  482. LM_ServiceInterrupts(pDevice);
  483. newtag = pDevice->pStatusBlkVirt->StatusTag;
  484. if ((newtag == oldtag) || (i > 50)) {
  485. MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24);
  486. if (pDevice->UndiFix) {
  487. REG_WR(pDevice, Grc.LocalCtrl,
  488. pDevice->GrcLocalCtrl | 0x2);
  489. }
  490. break;
  491. }
  492. oldtag = newtag;
  493. }
  494. }
  495. }
  496. else {
  497. while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
  498. unsigned int dummy;
  499. pDevice->pMemView->Mailbox.Interrupt[0].Low = 1;
  500. pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED;
  501. LM_ServiceInterrupts(pDevice);
  502. pDevice->pMemView->Mailbox.Interrupt[0].Low = 0;
  503. dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low;
  504. }
  505. }
  506. /* Allocate new RX buffers */
  507. if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) {
  508. bcm570xReplenishRxBuffers(pUmDevice);
  509. }
  510. /* Queue packets */
  511. if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) {
  512. LM_QueueRxPackets(pDevice);
  513. }
  514. if (pUmDevice->tx_queued) {
  515. pUmDevice->tx_queued = 0;
  516. }
  517. if(pUmDevice->tx_full){
  518. if(pDevice->LinkStatus != LM_STATUS_LINK_DOWN){
  519. printf("NOTICE: tx was previously blocked, restarting MUX\n");
  520. pUmDevice->tx_full = 0;
  521. }
  522. }
  523. pUmDevice->interrupt = 0;
  524. }
  525. int
  526. eth_send(volatile void *packet, int length)
  527. {
  528. int status = 0;
  529. #if ET_DEBUG
  530. unsigned char* ptr = (unsigned char*)packet;
  531. #endif
  532. PLM_PACKET pPacket;
  533. PUM_PACKET pUmPacket;
  534. /* Link down, return */
  535. while(pDevice->LinkStatus == LM_STATUS_LINK_DOWN) {
  536. #if 0
  537. printf("eth%d: link down - check cable or link partner.\n",
  538. pUmDevice->index);
  539. #endif
  540. eth_isr();
  541. /* Wait to see link for one-half a second before sending ... */
  542. udelay(1500000);
  543. }
  544. /* Clear sent flag */
  545. pUmDevice->tx_pkt = 0;
  546. /* Previously blocked */
  547. if(pUmDevice->tx_full){
  548. printf("eth%d: tx blocked.\n", pUmDevice->index);
  549. return 0;
  550. }
  551. pPacket = (PLM_PACKET)
  552. QQ_PopHead(&pDevice->TxPacketFreeQ.Container);
  553. if (pPacket == 0) {
  554. pUmDevice->tx_full = 1;
  555. printf("bcm570xEndSend: TX full!\n");
  556. return 0;
  557. }
  558. if (pDevice->SendBdLeft.counter == 0) {
  559. pUmDevice->tx_full = 1;
  560. printf("bcm570xEndSend: no more TX descriptors!\n");
  561. QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
  562. return 0;
  563. }
  564. if (length <= 0){
  565. printf("eth: bad packet size: %d\n", length);
  566. goto out;
  567. }
  568. /* Get packet buffers and fragment list */
  569. pUmPacket = (PUM_PACKET) pPacket;
  570. /* Single DMA Descriptor transmit.
  571. * Fragments may be provided, but one DMA descriptor max is
  572. * used to send the packet.
  573. */
  574. if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) {
  575. if (pUmPacket->skbuff == NULL){
  576. /* Packet was discarded */
  577. printf("TX: failed (1)\n");
  578. status = 1;
  579. } else{
  580. printf("TX: failed (2)\n");
  581. status = 2;
  582. }
  583. QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
  584. return status;
  585. }
  586. /* Copy packet to DMA buffer */
  587. memset(pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE);
  588. memcpy((void*)pUmPacket->skbuff, (void*)packet, length);
  589. pPacket->PacketSize = length;
  590. pPacket->Flags |= SND_BD_FLAG_END|SND_BD_FLAG_COAL_NOW;
  591. pPacket->u.Tx.FragCount = 1;
  592. /* We've already provided a frame ready for transmission */
  593. pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM;
  594. if ( LM_SendPacket(pDevice, pPacket) == LM_STATUS_FAILURE){
  595. /*
  596. * A lower level send failure will push the packet descriptor back
  597. * in the free queue, so just deal with the VxWorks clusters.
  598. */
  599. if (pUmPacket->skbuff == NULL){
  600. printf("TX failed (1)!\n");
  601. /* Packet was discarded */
  602. status = 3;
  603. } else {
  604. /* A resource problem ... */
  605. printf("TX failed (2)!\n");
  606. status = 4;
  607. }
  608. if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) == 0) {
  609. printf("TX: emptyQ!\n");
  610. pUmDevice->tx_full = 1;
  611. }
  612. }
  613. while(pUmDevice->tx_pkt == 0){
  614. /* Service TX */
  615. eth_isr();
  616. }
  617. #if ET_DEBUG
  618. printf("eth_send: 0x%x, %d bytes\n"
  619. "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n",
  620. (int)pPacket, length,
  621. ptr[0],ptr[1],ptr[2],ptr[3],ptr[4],ptr[5],
  622. ptr[6],ptr[7],ptr[8],ptr[9],ptr[10],ptr[11],ptr[12],
  623. ptr[13],ptr[14],ptr[15]);
  624. #endif
  625. pUmDevice->tx_pkt = 0;
  626. QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
  627. /* Done with send */
  628. out:
  629. return status;
  630. }
  631. /* Ethernet receive */
  632. int
  633. eth_rx(void)
  634. {
  635. PLM_PACKET pPacket = NULL;
  636. PUM_PACKET pUmPacket = NULL;
  637. void *skb;
  638. int size=0;
  639. while(TRUE) {
  640. bcm570x_service_isr:
  641. /* Pull down packet if it is there */
  642. eth_isr();
  643. /* Indicate RX packets called */
  644. if(pUmDevice->rx_pkt){
  645. /* printf("eth_rx: got a packet...\n"); */
  646. pUmDevice->rx_pkt = 0;
  647. } else {
  648. /* printf("eth_rx: waiting for packet...\n"); */
  649. goto bcm570x_service_isr;
  650. }
  651. pPacket = (PLM_PACKET)
  652. QQ_PopHead(&pDevice->RxPacketReceivedQ.Container);
  653. if (pPacket == 0){
  654. printf("eth_rx: empty packet!\n");
  655. goto bcm570x_service_isr;
  656. }
  657. pUmPacket = (PUM_PACKET) pPacket;
  658. #if ET_DEBUG
  659. printf("eth_rx: packet @0x%x\n",
  660. (int)pPacket);
  661. #endif
  662. /* If the packet generated an error, reuse buffer */
  663. if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) ||
  664. ((size = pPacket->PacketSize) > pDevice->RxMtu)) {
  665. /* reuse skb */
  666. QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
  667. printf("eth_rx: error in packet dma!\n");
  668. goto bcm570x_service_isr;
  669. }
  670. /* Set size and address */
  671. skb = pUmPacket->skbuff;
  672. size = pPacket->PacketSize;
  673. /* Pass the packet up to the protocol
  674. * layers.
  675. */
  676. NetReceive(skb, size);
  677. /* Free packet buffer */
  678. bcm570xPktFree (pUmDevice->index, skb);
  679. pUmPacket->skbuff = NULL;
  680. /* Reuse SKB */
  681. QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
  682. return 0; /* Got a packet, bail ... */
  683. }
  684. return size;
  685. }
  686. /* Shut down device */
  687. void
  688. eth_halt(void)
  689. {
  690. int i;
  691. if ( initialized)
  692. if (pDevice && pUmDevice && pUmDevice->opened){
  693. printf("\neth%d:%s,", pUmDevice->index, pUmDevice->name);
  694. printf("HALT,");
  695. /* stop device */
  696. LM_Halt(pDevice);
  697. printf("POWER DOWN,");
  698. LM_SetPowerState(pDevice, LM_POWER_STATE_D3);
  699. /* Free the memory allocated by the device in tigon3 */
  700. for (i = 0; i < pUmDevice->mem_list_num; i++) {
  701. if (pUmDevice->mem_list[i]) {
  702. /* sanity check */
  703. if (pUmDevice->dma_list[i]) { /* cache-safe memory */
  704. free(pUmDevice->mem_list[i]);
  705. } else {
  706. free(pUmDevice->mem_list[i]); /* normal memory */
  707. }
  708. }
  709. }
  710. pUmDevice->opened = 0;
  711. free(pDevice);
  712. pDevice = NULL;
  713. pUmDevice = NULL;
  714. initialized = 0;
  715. printf("done - offline.\n");
  716. }
  717. }
  718. /*
  719. *
  720. * Middle Module: Interface between the HW driver (tigon3 modules) and
  721. * the native (SENS) driver. These routines implement the system
  722. * interface for tigon3 on VxWorks.
  723. */
  724. /* Middle module dependency - size of a packet descriptor */
  725. int MM_Packet_Desc_Size = sizeof(UM_PACKET);
  726. LM_STATUS
  727. MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice,
  728. LM_UINT32 Offset,
  729. LM_UINT32 *pValue32)
  730. {
  731. UM_DEVICE_BLOCK *pUmDevice;
  732. pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
  733. pci_read_config_dword(pUmDevice->pdev,
  734. Offset, (u32 *) pValue32);
  735. return LM_STATUS_SUCCESS;
  736. }
  737. LM_STATUS
  738. MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice,
  739. LM_UINT32 Offset,
  740. LM_UINT32 Value32)
  741. {
  742. UM_DEVICE_BLOCK *pUmDevice;
  743. pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
  744. pci_write_config_dword(pUmDevice->pdev,
  745. Offset, Value32);
  746. return LM_STATUS_SUCCESS;
  747. }
  748. LM_STATUS
  749. MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice,
  750. LM_UINT32 Offset,
  751. LM_UINT16 *pValue16)
  752. {
  753. UM_DEVICE_BLOCK *pUmDevice;
  754. pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
  755. pci_read_config_word(pUmDevice->pdev,
  756. Offset, (u16*) pValue16);
  757. return LM_STATUS_SUCCESS;
  758. }
  759. LM_STATUS
  760. MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice,
  761. LM_UINT32 Offset,
  762. LM_UINT16 Value16)
  763. {
  764. UM_DEVICE_BLOCK *pUmDevice;
  765. pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
  766. pci_write_config_word(pUmDevice->pdev,
  767. Offset, Value16);
  768. return LM_STATUS_SUCCESS;
  769. }
  770. LM_STATUS
  771. MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
  772. PLM_VOID *pMemoryBlockVirt,
  773. PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
  774. LM_BOOL Cached)
  775. {
  776. PLM_VOID pvirt;
  777. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  778. dma_addr_t mapping;
  779. pvirt = malloc(BlockSize);
  780. mapping = (dma_addr_t)(pvirt);
  781. if (!pvirt)
  782. return LM_STATUS_FAILURE;
  783. pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
  784. pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping;
  785. pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
  786. memset(pvirt, 0, BlockSize);
  787. *pMemoryBlockVirt = (PLM_VOID) pvirt;
  788. MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping);
  789. return LM_STATUS_SUCCESS;
  790. }
  791. LM_STATUS
  792. MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
  793. PLM_VOID *pMemoryBlockVirt)
  794. {
  795. PLM_VOID pvirt;
  796. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  797. pvirt = malloc(BlockSize);
  798. if (!pvirt)
  799. return LM_STATUS_FAILURE;
  800. pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
  801. pUmDevice->dma_list[pUmDevice->mem_list_num] = 0;
  802. pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
  803. memset(pvirt, 0, BlockSize);
  804. *pMemoryBlockVirt = pvirt;
  805. return LM_STATUS_SUCCESS;
  806. }
  807. LM_STATUS
  808. MM_MapMemBase(PLM_DEVICE_BLOCK pDevice)
  809. {
  810. printf("BCM570x PCI Memory base address @0x%x\n",
  811. (unsigned int)pDevice->pMappedMemBase);
  812. return LM_STATUS_SUCCESS;
  813. }
  814. LM_STATUS
  815. MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice)
  816. {
  817. int i;
  818. void* skb;
  819. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  820. PUM_PACKET pUmPacket = NULL;
  821. PLM_PACKET pPacket = NULL;
  822. for (i = 0; i < pDevice->RxPacketDescCnt; i++) {
  823. pPacket = QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
  824. pUmPacket = (PUM_PACKET) pPacket;
  825. if (pPacket == 0) {
  826. printf("MM_InitializeUmPackets: Bad RxPacketFreeQ\n");
  827. }
  828. skb = bcm570xPktAlloc(pUmDevice->index,
  829. pPacket->u.Rx.RxBufferSize + 2);
  830. if (skb == 0) {
  831. pUmPacket->skbuff = 0;
  832. QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket);
  833. printf("MM_InitializeUmPackets: out of buffer.\n");
  834. continue;
  835. }
  836. pUmPacket->skbuff = skb;
  837. QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
  838. }
  839. pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8;
  840. return LM_STATUS_SUCCESS;
  841. }
  842. LM_STATUS
  843. MM_GetConfig(PLM_DEVICE_BLOCK pDevice)
  844. {
  845. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  846. int index = pDevice->index;
  847. if (auto_speed[index] == 0)
  848. pDevice->DisableAutoNeg = TRUE;
  849. else
  850. pDevice->DisableAutoNeg = FALSE;
  851. if (line_speed[index] == 0) {
  852. pDevice->RequestedMediaType =
  853. LM_REQUESTED_MEDIA_TYPE_AUTO;
  854. pDevice->DisableAutoNeg = FALSE;
  855. }
  856. else {
  857. if (line_speed[index] == 1000) {
  858. if (pDevice->EnableTbi) {
  859. pDevice->RequestedMediaType =
  860. LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX;
  861. }
  862. else if (full_duplex[index]) {
  863. pDevice->RequestedMediaType =
  864. LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX;
  865. }
  866. else {
  867. pDevice->RequestedMediaType =
  868. LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS;
  869. }
  870. if (!pDevice->EnableTbi)
  871. pDevice->DisableAutoNeg = FALSE;
  872. }
  873. else if (line_speed[index] == 100) {
  874. if (full_duplex[index]) {
  875. pDevice->RequestedMediaType =
  876. LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX;
  877. }
  878. else {
  879. pDevice->RequestedMediaType =
  880. LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS;
  881. }
  882. }
  883. else if (line_speed[index] == 10) {
  884. if (full_duplex[index]) {
  885. pDevice->RequestedMediaType =
  886. LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX;
  887. }
  888. else {
  889. pDevice->RequestedMediaType =
  890. LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
  891. }
  892. }
  893. else {
  894. pDevice->RequestedMediaType =
  895. LM_REQUESTED_MEDIA_TYPE_AUTO;
  896. pDevice->DisableAutoNeg = FALSE;
  897. }
  898. }
  899. pDevice->FlowControlCap = 0;
  900. if (rx_flow_control[index] != 0) {
  901. pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
  902. }
  903. if (tx_flow_control[index] != 0) {
  904. pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
  905. }
  906. if ((auto_flow_control[index] != 0) &&
  907. (pDevice->DisableAutoNeg == FALSE)) {
  908. pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE;
  909. if ((tx_flow_control[index] == 0) &&
  910. (rx_flow_control[index] == 0)) {
  911. pDevice->FlowControlCap |=
  912. LM_FLOW_CONTROL_TRANSMIT_PAUSE |
  913. LM_FLOW_CONTROL_RECEIVE_PAUSE;
  914. }
  915. }
  916. /* Default MTU for now */
  917. pUmDevice->mtu = 1500;
  918. #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
  919. if (pUmDevice->mtu > 1500) {
  920. pDevice->RxMtu = pUmDevice->mtu;
  921. pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
  922. }
  923. else {
  924. pDevice->RxJumboDescCnt = 0;
  925. }
  926. pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index];
  927. #else
  928. pDevice->RxMtu = pUmDevice->mtu;
  929. #endif
  930. if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) {
  931. pDevice->UseTaggedStatus = TRUE;
  932. pUmDevice->timer_interval = CFG_HZ;
  933. }
  934. else {
  935. pUmDevice->timer_interval = CFG_HZ/50;
  936. }
  937. pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index];
  938. pDevice->RxStdDescCnt = rx_std_desc_cnt[index];
  939. /* Note: adaptive coalescence really isn't adaptive in this driver */
  940. pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index];
  941. if (!pUmDevice->rx_adaptive_coalesce) {
  942. pDevice->RxCoalescingTicks = rx_coalesce_ticks[index];
  943. if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS)
  944. pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS;
  945. pUmDevice->rx_curr_coalesce_ticks =pDevice->RxCoalescingTicks;
  946. pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index];
  947. if (pDevice->RxMaxCoalescedFrames>MAX_RX_MAX_COALESCED_FRAMES)
  948. pDevice->RxMaxCoalescedFrames =
  949. MAX_RX_MAX_COALESCED_FRAMES;
  950. pUmDevice->rx_curr_coalesce_frames =
  951. pDevice->RxMaxCoalescedFrames;
  952. pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index];
  953. if (pDevice->StatsCoalescingTicks>MAX_STATS_COALESCING_TICKS)
  954. pDevice->StatsCoalescingTicks=
  955. MAX_STATS_COALESCING_TICKS;
  956. }
  957. else {
  958. pUmDevice->rx_curr_coalesce_frames =
  959. DEFAULT_RX_MAX_COALESCED_FRAMES;
  960. pUmDevice->rx_curr_coalesce_ticks =
  961. DEFAULT_RX_COALESCING_TICKS;
  962. }
  963. pDevice->TxCoalescingTicks = tx_coalesce_ticks[index];
  964. if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS)
  965. pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS;
  966. pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index];
  967. if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES)
  968. pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES;
  969. if (enable_wol[index]) {
  970. pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET;
  971. pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET;
  972. }
  973. pDevice->NicSendBd = TRUE;
  974. /* Don't update status blocks during interrupt */
  975. pDevice->RxCoalescingTicksDuringInt = 0;
  976. pDevice->TxCoalescingTicksDuringInt = 0;
  977. return LM_STATUS_SUCCESS;
  978. }
  979. LM_STATUS
  980. MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
  981. {
  982. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  983. printf("Start TX DMA: dev=%d packet @0x%x\n",
  984. (int)pUmDevice->index, (unsigned int)pPacket);
  985. return LM_STATUS_SUCCESS;
  986. }
  987. LM_STATUS
  988. MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
  989. {
  990. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  991. printf("Complete TX DMA: dev=%d packet @0x%x\n",
  992. (int)pUmDevice->index, (unsigned int)pPacket);
  993. return LM_STATUS_SUCCESS;
  994. }
  995. LM_STATUS
  996. MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status)
  997. {
  998. char buf[128];
  999. char lcd[4];
  1000. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  1001. LM_FLOW_CONTROL flow_control;
  1002. pUmDevice->delayed_link_ind = 0;
  1003. memset(lcd, 0x0, 4);
  1004. if (Status == LM_STATUS_LINK_DOWN) {
  1005. sprintf(buf,"eth%d: %s: NIC Link is down\n",
  1006. pUmDevice->index,pUmDevice->name);
  1007. lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?';
  1008. } else if (Status == LM_STATUS_LINK_ACTIVE) {
  1009. sprintf(buf,"eth%d:%s: ", pUmDevice->index, pUmDevice->name);
  1010. if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS){
  1011. strcat(buf,"1000 Mbps ");
  1012. lcd[0] = '1';lcd[1]='G';lcd[2]='B';
  1013. } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS){
  1014. strcat(buf,"100 Mbps ");
  1015. lcd[0] = '1';lcd[1]='0';lcd[2]='0';
  1016. } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS){
  1017. strcat(buf,"10 Mbps ");
  1018. lcd[0] = '1';lcd[1]='0';lcd[2]=' ';
  1019. }
  1020. if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL){
  1021. strcat(buf, "full duplex");
  1022. lcd[3] = 'F';
  1023. } else {
  1024. strcat(buf, "half duplex");
  1025. lcd[3] = 'H';
  1026. }
  1027. strcat(buf, " link up");
  1028. flow_control = pDevice->FlowControl &
  1029. (LM_FLOW_CONTROL_RECEIVE_PAUSE |
  1030. LM_FLOW_CONTROL_TRANSMIT_PAUSE);
  1031. if (flow_control) {
  1032. if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
  1033. strcat(buf,", receive ");
  1034. if (flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
  1035. strcat(buf," & transmit ");
  1036. }
  1037. else {
  1038. strcat(buf,", transmit ");
  1039. }
  1040. strcat(buf,"flow control ON");
  1041. } else {
  1042. strcat(buf, ", flow control OFF");
  1043. }
  1044. strcat(buf,"\n");
  1045. printf("%s",buf);
  1046. }
  1047. #if 0
  1048. sysLedDsply(lcd[0],lcd[1],lcd[2],lcd[3]);
  1049. #endif
  1050. return LM_STATUS_SUCCESS;
  1051. }
  1052. LM_STATUS
  1053. MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
  1054. {
  1055. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  1056. PUM_PACKET pUmPacket;
  1057. void *skb;
  1058. pUmPacket = (PUM_PACKET) pPacket;
  1059. if ((skb = pUmPacket->skbuff))
  1060. bcm570xPktFree(pUmDevice->index, skb);
  1061. pUmPacket->skbuff = 0;
  1062. return LM_STATUS_SUCCESS;
  1063. }
  1064. unsigned long
  1065. MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo)
  1066. {
  1067. return get_timer(0);
  1068. }
  1069. /*
  1070. * Transform an MBUF chain into a single MBUF.
  1071. * This routine will fail if the amount of data in the
  1072. * chain overflows a transmit buffer. In that case,
  1073. * the incoming MBUF chain will be freed. This routine can
  1074. * also fail by not being able to allocate a new MBUF (including
  1075. * cluster and mbuf headers). In that case the failure is
  1076. * non-fatal. The incoming cluster chain is not freed, giving
  1077. * the caller the choice of whether to try a retransmit later.
  1078. */
  1079. LM_STATUS
  1080. MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
  1081. {
  1082. PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
  1083. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  1084. void *skbnew;
  1085. int len = 0;
  1086. if (len == 0)
  1087. return (LM_STATUS_SUCCESS);
  1088. if (len > MAX_PACKET_SIZE){
  1089. printf ("eth%d: xmit frame discarded, too big!, size = %d\n",
  1090. pUmDevice->index, len);
  1091. return (LM_STATUS_FAILURE);
  1092. }
  1093. skbnew = bcm570xPktAlloc(pUmDevice->index, MAX_PACKET_SIZE);
  1094. if (skbnew == NULL) {
  1095. pUmDevice->tx_full = 1;
  1096. printf ("eth%d: out of transmit buffers", pUmDevice->index);
  1097. return (LM_STATUS_FAILURE);
  1098. }
  1099. /* New packet values */
  1100. pUmPacket->skbuff = skbnew;
  1101. pUmPacket->lm_packet.u.Tx.FragCount = 1;
  1102. return (LM_STATUS_SUCCESS);
  1103. }
  1104. LM_STATUS
  1105. MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice)
  1106. {
  1107. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  1108. pUmDevice->rx_pkt = 1;
  1109. return LM_STATUS_SUCCESS;
  1110. }
  1111. LM_STATUS
  1112. MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice)
  1113. {
  1114. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  1115. PLM_PACKET pPacket;
  1116. PUM_PACKET pUmPacket;
  1117. void *skb;
  1118. while ( TRUE ) {
  1119. pPacket = (PLM_PACKET)
  1120. QQ_PopHead(&pDevice->TxPacketXmittedQ.Container);
  1121. if (pPacket == 0)
  1122. break;
  1123. pUmPacket = (PUM_PACKET) pPacket;
  1124. skb = (void*)pUmPacket->skbuff;
  1125. /*
  1126. * Free MBLK if we transmitted a fragmented packet or a
  1127. * non-fragmented packet straight from the VxWorks
  1128. * buffer pool. If packet was copied to a local transmit
  1129. * buffer, then there's no MBUF to free, just free
  1130. * the transmit buffer back to the cluster pool.
  1131. */
  1132. if (skb)
  1133. bcm570xPktFree (pUmDevice->index, skb);
  1134. pUmPacket->skbuff = 0;
  1135. QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
  1136. pUmDevice->tx_pkt = 1;
  1137. }
  1138. if (pUmDevice->tx_full) {
  1139. if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) >=
  1140. (QQ_GetSize(&pDevice->TxPacketFreeQ.Container) >> 1))
  1141. pUmDevice->tx_full = 0;
  1142. }
  1143. return LM_STATUS_SUCCESS;
  1144. }
  1145. /*
  1146. * Scan an MBUF chain until we reach fragment number "frag"
  1147. * Return its length and physical address.
  1148. */
  1149. void MM_MapTxDma
  1150. (
  1151. PLM_DEVICE_BLOCK pDevice,
  1152. struct _LM_PACKET *pPacket,
  1153. T3_64BIT_HOST_ADDR *paddr,
  1154. LM_UINT32 *len,
  1155. int frag)
  1156. {
  1157. PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
  1158. *len = pPacket->PacketSize;
  1159. MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff);
  1160. }
  1161. /*
  1162. * Convert an mbuf address, a CPU local virtual address,
  1163. * to a physical address as seen from a PCI device. Store the
  1164. * result at paddr.
  1165. */
  1166. void MM_MapRxDma(
  1167. PLM_DEVICE_BLOCK pDevice,
  1168. struct _LM_PACKET *pPacket,
  1169. T3_64BIT_HOST_ADDR *paddr)
  1170. {
  1171. PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
  1172. MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff);
  1173. }
  1174. void
  1175. MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr)
  1176. {
  1177. #if (BITS_PER_LONG == 64)
  1178. paddr->High = ((unsigned long) addr) >> 32;
  1179. paddr->Low = ((unsigned long) addr) & 0xffffffff;
  1180. #else
  1181. paddr->High = 0;
  1182. paddr->Low = (unsigned long) addr;
  1183. #endif
  1184. }
  1185. void
  1186. MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr)
  1187. {
  1188. unsigned long baddr = (unsigned long) addr;
  1189. #if (BITS_PER_LONG == 64)
  1190. set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32);
  1191. #else
  1192. set_64bit_addr(paddr, baddr, 0);
  1193. #endif
  1194. }
  1195. /*
  1196. * This combination of `inline' and `extern' has almost the effect of a
  1197. * macro. The way to use it is to put a function definition in a header
  1198. * file with these keywords, and put another copy of the definition
  1199. * (lacking `inline' and `extern') in a library file. The definition in
  1200. * the header file will cause most calls to the function to be inlined.
  1201. * If any uses of the function remain, they will refer to the single copy
  1202. * in the library.
  1203. */
  1204. void
  1205. atomic_set(atomic_t* entry, int val)
  1206. {
  1207. entry->counter = val;
  1208. }
  1209. int
  1210. atomic_read(atomic_t* entry)
  1211. {
  1212. return entry->counter;
  1213. }
  1214. void
  1215. atomic_inc(atomic_t* entry)
  1216. {
  1217. if(entry)
  1218. entry->counter++;
  1219. }
  1220. void
  1221. atomic_dec(atomic_t* entry)
  1222. {
  1223. if(entry)
  1224. entry->counter--;
  1225. }
  1226. void
  1227. atomic_sub(int a, atomic_t* entry)
  1228. {
  1229. if(entry)
  1230. entry->counter -= a;
  1231. }
  1232. void
  1233. atomic_add(int a, atomic_t* entry)
  1234. {
  1235. if(entry)
  1236. entry->counter += a;
  1237. }
  1238. /******************************************************************************/
  1239. /* Description: */
  1240. /* */
  1241. /* Return: */
  1242. /******************************************************************************/
  1243. void
  1244. QQ_InitQueue(
  1245. PQQ_CONTAINER pQueue,
  1246. unsigned int QueueSize) {
  1247. pQueue->Head = 0;
  1248. pQueue->Tail = 0;
  1249. pQueue->Size = QueueSize+1;
  1250. atomic_set(&pQueue->EntryCnt, 0);
  1251. } /* QQ_InitQueue */
  1252. /******************************************************************************/
  1253. /* Description: */
  1254. /* */
  1255. /* Return: */
  1256. /******************************************************************************/
  1257. char
  1258. QQ_Full(
  1259. PQQ_CONTAINER pQueue) {
  1260. unsigned int NewHead;
  1261. NewHead = (pQueue->Head + 1) % pQueue->Size;
  1262. return(NewHead == pQueue->Tail);
  1263. } /* QQ_Full */
  1264. /******************************************************************************/
  1265. /* Description: */
  1266. /* */
  1267. /* Return: */
  1268. /******************************************************************************/
  1269. char
  1270. QQ_Empty(
  1271. PQQ_CONTAINER pQueue) {
  1272. return(pQueue->Head == pQueue->Tail);
  1273. } /* QQ_Empty */
  1274. /******************************************************************************/
  1275. /* Description: */
  1276. /* */
  1277. /* Return: */
  1278. /******************************************************************************/
  1279. unsigned int
  1280. QQ_GetSize(
  1281. PQQ_CONTAINER pQueue) {
  1282. return pQueue->Size;
  1283. } /* QQ_GetSize */
  1284. /******************************************************************************/
  1285. /* Description: */
  1286. /* */
  1287. /* Return: */
  1288. /******************************************************************************/
  1289. unsigned int
  1290. QQ_GetEntryCnt(
  1291. PQQ_CONTAINER pQueue) {
  1292. return atomic_read(&pQueue->EntryCnt);
  1293. } /* QQ_GetEntryCnt */
  1294. /******************************************************************************/
  1295. /* Description: */
  1296. /* */
  1297. /* Return: */
  1298. /* TRUE entry was added successfully. */
  1299. /* FALSE queue is full. */
  1300. /******************************************************************************/
  1301. char
  1302. QQ_PushHead(
  1303. PQQ_CONTAINER pQueue,
  1304. PQQ_ENTRY pEntry) {
  1305. unsigned int Head;
  1306. Head = (pQueue->Head + 1) % pQueue->Size;
  1307. #if !defined(QQ_NO_OVERFLOW_CHECK)
  1308. if(Head == pQueue->Tail) {
  1309. return 0;
  1310. } /* if */
  1311. #endif /* QQ_NO_OVERFLOW_CHECK */
  1312. pQueue->Array[pQueue->Head] = pEntry;
  1313. wmb();
  1314. pQueue->Head = Head;
  1315. atomic_inc(&pQueue->EntryCnt);
  1316. return -1;
  1317. } /* QQ_PushHead */
  1318. /******************************************************************************/
  1319. /* Description: */
  1320. /* */
  1321. /* Return: */
  1322. /* TRUE entry was added successfully. */
  1323. /* FALSE queue is full. */
  1324. /******************************************************************************/
  1325. char
  1326. QQ_PushTail(
  1327. PQQ_CONTAINER pQueue,
  1328. PQQ_ENTRY pEntry) {
  1329. unsigned int Tail;
  1330. Tail = pQueue->Tail;
  1331. if(Tail == 0) {
  1332. Tail = pQueue->Size;
  1333. } /* if */
  1334. Tail--;
  1335. #if !defined(QQ_NO_OVERFLOW_CHECK)
  1336. if(Tail == pQueue->Head) {
  1337. return 0;
  1338. } /* if */
  1339. #endif /* QQ_NO_OVERFLOW_CHECK */
  1340. pQueue->Array[Tail] = pEntry;
  1341. wmb();
  1342. pQueue->Tail = Tail;
  1343. atomic_inc(&pQueue->EntryCnt);
  1344. return -1;
  1345. } /* QQ_PushTail */
  1346. /******************************************************************************/
  1347. /* Description: */
  1348. /* */
  1349. /* Return: */
  1350. /******************************************************************************/
  1351. PQQ_ENTRY
  1352. QQ_PopHead(
  1353. PQQ_CONTAINER pQueue) {
  1354. unsigned int Head;
  1355. PQQ_ENTRY Entry;
  1356. Head = pQueue->Head;
  1357. #if !defined(QQ_NO_UNDERFLOW_CHECK)
  1358. if(Head == pQueue->Tail) {
  1359. return (PQQ_ENTRY) 0;
  1360. } /* if */
  1361. #endif /* QQ_NO_UNDERFLOW_CHECK */
  1362. if(Head == 0) {
  1363. Head = pQueue->Size;
  1364. } /* if */
  1365. Head--;
  1366. Entry = pQueue->Array[Head];
  1367. membar();
  1368. pQueue->Head = Head;
  1369. atomic_dec(&pQueue->EntryCnt);
  1370. return Entry;
  1371. } /* QQ_PopHead */
  1372. /******************************************************************************/
  1373. /* Description: */
  1374. /* */
  1375. /* Return: */
  1376. /******************************************************************************/
  1377. PQQ_ENTRY
  1378. QQ_PopTail(
  1379. PQQ_CONTAINER pQueue) {
  1380. unsigned int Tail;
  1381. PQQ_ENTRY Entry;
  1382. Tail = pQueue->Tail;
  1383. #if !defined(QQ_NO_UNDERFLOW_CHECK)
  1384. if(Tail == pQueue->Head) {
  1385. return (PQQ_ENTRY) 0;
  1386. } /* if */
  1387. #endif /* QQ_NO_UNDERFLOW_CHECK */
  1388. Entry = pQueue->Array[Tail];
  1389. membar();
  1390. pQueue->Tail = (Tail + 1) % pQueue->Size;
  1391. atomic_dec(&pQueue->EntryCnt);
  1392. return Entry;
  1393. } /* QQ_PopTail */
  1394. /******************************************************************************/
  1395. /* Description: */
  1396. /* */
  1397. /* Return: */
  1398. /******************************************************************************/
  1399. PQQ_ENTRY
  1400. QQ_GetHead(
  1401. PQQ_CONTAINER pQueue,
  1402. unsigned int Idx)
  1403. {
  1404. if(Idx >= atomic_read(&pQueue->EntryCnt))
  1405. {
  1406. return (PQQ_ENTRY) 0;
  1407. }
  1408. if(pQueue->Head > Idx)
  1409. {
  1410. Idx = pQueue->Head - Idx;
  1411. }
  1412. else
  1413. {
  1414. Idx = pQueue->Size - (Idx - pQueue->Head);
  1415. }
  1416. Idx--;
  1417. return pQueue->Array[Idx];
  1418. }
  1419. /******************************************************************************/
  1420. /* Description: */
  1421. /* */
  1422. /* Return: */
  1423. /******************************************************************************/
  1424. PQQ_ENTRY
  1425. QQ_GetTail(
  1426. PQQ_CONTAINER pQueue,
  1427. unsigned int Idx)
  1428. {
  1429. if(Idx >= atomic_read(&pQueue->EntryCnt))
  1430. {
  1431. return (PQQ_ENTRY) 0;
  1432. }
  1433. Idx += pQueue->Tail;
  1434. if(Idx >= pQueue->Size)
  1435. {
  1436. Idx = Idx - pQueue->Size;
  1437. }
  1438. return pQueue->Array[Idx];
  1439. }
  1440. #endif