cpu.c 6.8 KB

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  1. /*
  2. * (C) Copyright 2000-2006
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
  25. *
  26. * written or collected and sometimes rewritten by
  27. * Magnus Damm <damm@bitsmart.com>
  28. *
  29. * modified by
  30. * Wolfgang Denk <wd@denx.de>
  31. *
  32. * modified for 8260 by
  33. * Murray Jensen <Murray.Jensen@cmst.csiro.au>
  34. *
  35. * added 8260 masks by
  36. * Marius Groeger <mag@sysgo.de>
  37. *
  38. * added HiP7 (824x/827x/8280) processors support by
  39. * Yuli Barcohen <yuli@arabellasw.com>
  40. */
  41. #include <common.h>
  42. #include <watchdog.h>
  43. #include <command.h>
  44. #include <mpc8260.h>
  45. #include <asm/processor.h>
  46. #include <asm/cpm_8260.h>
  47. DECLARE_GLOBAL_DATA_PTR;
  48. #if defined(CONFIG_GET_CPU_STR_F)
  49. extern int get_cpu_str_f (char *buf);
  50. #endif
  51. int checkcpu (void)
  52. {
  53. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  54. ulong clock = gd->cpu_clk;
  55. uint pvr = get_pvr ();
  56. uint immr, rev, m, k;
  57. char buf[32];
  58. puts ("CPU: ");
  59. switch (pvr) {
  60. case PVR_8260:
  61. case PVR_8260_HIP3:
  62. k = 3;
  63. break;
  64. case PVR_8260_HIP4:
  65. k = 4;
  66. break;
  67. case PVR_8260_HIP7R1:
  68. case PVR_8260_HIP7RA:
  69. case PVR_8260_HIP7:
  70. k = 7;
  71. break;
  72. default:
  73. return -1; /* whoops! not an MPC8260 */
  74. }
  75. rev = pvr & 0xff;
  76. immr = immap->im_memctl.memc_immr;
  77. if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
  78. return -1; /* whoops! someone moved the IMMR */
  79. #if defined(CONFIG_GET_CPU_STR_F)
  80. get_cpu_str_f (buf);
  81. printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
  82. #else
  83. printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
  84. #endif
  85. /*
  86. * the bottom 16 bits of the immr are the Part Number and Mask Number
  87. * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
  88. * RISC Microcode Revision Number (13-10).
  89. * For the 8260, Motorola doesn't include the Microcode Revision
  90. * in the mask.
  91. */
  92. m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
  93. k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
  94. switch (m) {
  95. case 0x0000:
  96. puts ("0.2 2J24M");
  97. break;
  98. case 0x0010:
  99. puts ("A.0 K22A");
  100. break;
  101. case 0x0011:
  102. puts ("A.1 1K22A-XC");
  103. break;
  104. case 0x0001:
  105. puts ("B.1 1K23A");
  106. break;
  107. case 0x0021:
  108. puts ("B.2 2K23A-XC");
  109. break;
  110. case 0x0023:
  111. puts ("B.3 3K23A");
  112. break;
  113. case 0x0024:
  114. puts ("C.2 6K23A");
  115. break;
  116. case 0x0060:
  117. puts ("A.0(A) 2K25A");
  118. break;
  119. case 0x0062:
  120. puts ("B.1 4K25A");
  121. break;
  122. case 0x0064:
  123. puts ("C.0 5K25A");
  124. break;
  125. case 0x0A00:
  126. puts ("0.0 0K49M");
  127. break;
  128. case 0x0A01:
  129. puts ("0.1 1K49M");
  130. break;
  131. case 0x0A10:
  132. puts ("1.0 1K49M");
  133. break;
  134. case 0x0C00:
  135. puts ("0.0 0K50M");
  136. break;
  137. case 0x0C10:
  138. puts ("1.0 1K50M");
  139. break;
  140. case 0x0D00:
  141. puts ("0.0 0K50M");
  142. break;
  143. case 0x0D10:
  144. puts ("1.0 1K50M");
  145. break;
  146. default:
  147. printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
  148. break;
  149. }
  150. printf (") at %s MHz\n", strmhz (buf, clock));
  151. return 0;
  152. }
  153. /* ------------------------------------------------------------------------- */
  154. /* configures a UPM by writing into the UPM RAM array */
  155. /* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
  156. /* NOTE: the physical address chosen must not overlap into any other area */
  157. /* mapped by the memory controller because bank 11 has the lowest priority */
  158. void upmconfig (uint upm, uint * table, uint size)
  159. {
  160. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  161. volatile memctl8260_t *memctl = &immap->im_memctl;
  162. volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */
  163. uint i;
  164. /* first set up bank 11 to reference the correct UPM at a dummy address */
  165. memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */
  166. switch (upm) {
  167. case UPMA:
  168. memctl->memc_br11 =
  169. ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
  170. BRx_V;
  171. memctl->memc_mamr = MxMR_OP_WARR;
  172. break;
  173. case UPMB:
  174. memctl->memc_br11 =
  175. ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
  176. BRx_V;
  177. memctl->memc_mbmr = MxMR_OP_WARR;
  178. break;
  179. case UPMC:
  180. memctl->memc_br11 =
  181. ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
  182. BRx_V;
  183. memctl->memc_mcmr = MxMR_OP_WARR;
  184. break;
  185. default:
  186. panic ("upmconfig passed invalid UPM number (%u)\n", upm);
  187. break;
  188. }
  189. /*
  190. * at this point, the dummy address is set up to access the selected UPM,
  191. * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
  192. *
  193. * now we simply load the mdr with each word and poke the dummy address.
  194. * the MAD is incremented on each access.
  195. */
  196. for (i = 0; i < size; i++) {
  197. memctl->memc_mdr = table[i];
  198. *dummy = 0;
  199. }
  200. /* now kill bank 11 */
  201. memctl->memc_br11 = 0;
  202. }
  203. /* ------------------------------------------------------------------------- */
  204. #if !defined(CONFIG_HAVE_OWN_RESET)
  205. int
  206. do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  207. {
  208. ulong msr, addr;
  209. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  210. immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
  211. /* Interrupts and MMU off */
  212. __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
  213. msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
  214. __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
  215. /*
  216. * Trying to execute the next instruction at a non-existing address
  217. * should cause a machine check, resulting in reset
  218. */
  219. #ifdef CFG_RESET_ADDRESS
  220. addr = CFG_RESET_ADDRESS;
  221. #else
  222. /*
  223. * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
  224. * - sizeof (ulong) is usually a valid address. Better pick an address
  225. * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
  226. */
  227. addr = CFG_MONITOR_BASE - sizeof (ulong);
  228. #endif
  229. ((void (*)(void)) addr) ();
  230. return 1;
  231. }
  232. #endif /* CONFIG_HAVE_OWN_RESET */
  233. /* ------------------------------------------------------------------------- */
  234. /*
  235. * Get timebase clock frequency (like cpu_clk in Hz)
  236. *
  237. */
  238. unsigned long get_tbclk (void)
  239. {
  240. ulong tbclk;
  241. tbclk = (gd->bus_clk + 3L) / 4L;
  242. return (tbclk);
  243. }
  244. /* ------------------------------------------------------------------------- */
  245. #if defined(CONFIG_WATCHDOG)
  246. void watchdog_reset (void)
  247. {
  248. int re_enable = disable_interrupts ();
  249. reset_8260_watchdog ((immap_t *) CFG_IMMR);
  250. if (re_enable)
  251. enable_interrupts ();
  252. }
  253. #endif /* CONFIG_WATCHDOG */
  254. /* ------------------------------------------------------------------------- */