bcm570x.c 45 KB

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  1. /*
  2. * Broadcom BCM570x Ethernet Driver for U-Boot.
  3. * Support 5701, 5702, 5703, and 5704. Single instance driver.
  4. * Copyright (C) 2002 James F. Dougherty (jfd@broadcom.com)
  5. */
  6. #include <common.h>
  7. #ifdef CONFIG_BMW
  8. #include <mpc824x.h>
  9. #endif
  10. #include <net.h>
  11. #include "bcm570x_mm.h"
  12. #include "bcm570x_autoneg.h"
  13. #include <pci.h>
  14. #include <malloc.h>
  15. /*
  16. * PCI Registers and definitions.
  17. */
  18. #define PCI_CMD_MASK 0xffff0000 /* mask to save status bits */
  19. #define PCI_ANY_ID (~0)
  20. /*
  21. * PCI memory base for Ethernet device as well as device Interrupt.
  22. */
  23. #define BCM570X_MBAR 0x80100000
  24. #define BCM570X_ILINE 1
  25. #define SECOND_USEC 1000000
  26. #define MAX_PACKET_SIZE 1600
  27. #define MAX_UNITS 4
  28. /* Globals to this module */
  29. int initialized = 0;
  30. unsigned int ioBase = 0;
  31. volatile PLM_DEVICE_BLOCK pDevice = NULL; /* 570x softc */
  32. volatile PUM_DEVICE_BLOCK pUmDevice = NULL;
  33. /* Used to pass the full-duplex flag, etc. */
  34. int line_speed[MAX_UNITS] = { 0, 0, 0, 0 };
  35. static int full_duplex[MAX_UNITS] = { 1, 1, 1, 1 };
  36. static int rx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
  37. static int tx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
  38. static int auto_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
  39. static int tx_checksum[MAX_UNITS] = { 1, 1, 1, 1 };
  40. static int rx_checksum[MAX_UNITS] = { 1, 1, 1, 1 };
  41. static int auto_speed[MAX_UNITS] = { 1, 1, 1, 1 };
  42. #if JUMBO_FRAMES
  43. /* Jumbo MTU for interfaces. */
  44. static int mtu[MAX_UNITS] = { 0, 0, 0, 0 };
  45. #endif
  46. /* Turn on Wake-on lan for a device unit */
  47. static int enable_wol[MAX_UNITS] = { 0, 0, 0, 0 };
  48. #define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT
  49. static unsigned int tx_pkt_desc_cnt[MAX_UNITS] =
  50. { TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT };
  51. #define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT
  52. static unsigned int rx_std_desc_cnt[MAX_UNITS] =
  53. { RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT };
  54. static unsigned int rx_adaptive_coalesce[MAX_UNITS] = { 1, 1, 1, 1 };
  55. #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
  56. #define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT
  57. static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] =
  58. { JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT };
  59. #endif
  60. #define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS
  61. static unsigned int rx_coalesce_ticks[MAX_UNITS] =
  62. { RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK };
  63. #define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES
  64. static unsigned int rx_max_coalesce_frames[MAX_UNITS] =
  65. { RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM };
  66. #define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS
  67. static unsigned int tx_coalesce_ticks[MAX_UNITS] =
  68. { TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK };
  69. #define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES
  70. static unsigned int tx_max_coalesce_frames[MAX_UNITS] =
  71. { TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM };
  72. #define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS
  73. static unsigned int stats_coalesce_ticks[MAX_UNITS] =
  74. { ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK };
  75. /*
  76. * Legitimate values for BCM570x device types
  77. */
  78. typedef enum {
  79. BCM5700VIGIL = 0,
  80. BCM5700A6,
  81. BCM5700T6,
  82. BCM5700A9,
  83. BCM5700T9,
  84. BCM5700,
  85. BCM5701A5,
  86. BCM5701T1,
  87. BCM5701T8,
  88. BCM5701A7,
  89. BCM5701A10,
  90. BCM5701A12,
  91. BCM5701,
  92. BCM5702,
  93. BCM5703,
  94. BCM5703A31,
  95. TC996T,
  96. TC996ST,
  97. TC996SSX,
  98. TC996SX,
  99. TC996BT,
  100. TC997T,
  101. TC997SX,
  102. TC1000T,
  103. TC940BR01,
  104. TC942BR01,
  105. NC6770,
  106. NC7760,
  107. NC7770,
  108. NC7780
  109. } board_t;
  110. /* Chip-Rev names for each device-type */
  111. static struct {
  112. char *name;
  113. } chip_rev[] = {
  114. {
  115. "BCM5700VIGIL"}, {
  116. "BCM5700A6"}, {
  117. "BCM5700T6"}, {
  118. "BCM5700A9"}, {
  119. "BCM5700T9"}, {
  120. "BCM5700"}, {
  121. "BCM5701A5"}, {
  122. "BCM5701T1"}, {
  123. "BCM5701T8"}, {
  124. "BCM5701A7"}, {
  125. "BCM5701A10"}, {
  126. "BCM5701A12"}, {
  127. "BCM5701"}, {
  128. "BCM5702"}, {
  129. "BCM5703"}, {
  130. "BCM5703A31"}, {
  131. "TC996T"}, {
  132. "TC996ST"}, {
  133. "TC996SSX"}, {
  134. "TC996SX"}, {
  135. "TC996BT"}, {
  136. "TC997T"}, {
  137. "TC997SX"}, {
  138. "TC1000T"}, {
  139. "TC940BR01"}, {
  140. "TC942BR01"}, {
  141. "NC6770"}, {
  142. "NC7760"}, {
  143. "NC7770"}, {
  144. "NC7780"}, {
  145. 0}
  146. };
  147. /* indexed by board_t, above */
  148. static struct {
  149. char *name;
  150. } board_info[] = {
  151. {
  152. "Broadcom Vigil B5700 1000Base-T"}, {
  153. "Broadcom BCM5700 1000Base-T"}, {
  154. "Broadcom BCM5700 1000Base-SX"}, {
  155. "Broadcom BCM5700 1000Base-SX"}, {
  156. "Broadcom BCM5700 1000Base-T"}, {
  157. "Broadcom BCM5700"}, {
  158. "Broadcom BCM5701 1000Base-T"}, {
  159. "Broadcom BCM5701 1000Base-T"}, {
  160. "Broadcom BCM5701 1000Base-T"}, {
  161. "Broadcom BCM5701 1000Base-SX"}, {
  162. "Broadcom BCM5701 1000Base-T"}, {
  163. "Broadcom BCM5701 1000Base-T"}, {
  164. "Broadcom BCM5701"}, {
  165. "Broadcom BCM5702 1000Base-T"}, {
  166. "Broadcom BCM5703 1000Base-T"}, {
  167. "Broadcom BCM5703 1000Base-SX"}, {
  168. "3Com 3C996 10/100/1000 Server NIC"}, {
  169. "3Com 3C996 10/100/1000 Server NIC"}, {
  170. "3Com 3C996 Gigabit Fiber-SX Server NIC"}, {
  171. "3Com 3C996 Gigabit Fiber-SX Server NIC"}, {
  172. "3Com 3C996B Gigabit Server NIC"}, {
  173. "3Com 3C997 Gigabit Server NIC"}, {
  174. "3Com 3C997 Gigabit Fiber-SX Server NIC"}, {
  175. "3Com 3C1000 Gigabit NIC"}, {
  176. "3Com 3C940 Gigabit LOM (21X21)"}, {
  177. "3Com 3C942 Gigabit LOM (31X31)"}, {
  178. "Compaq NC6770 Gigabit Server Adapter"}, {
  179. "Compaq NC7760 Gigabit Server Adapter"}, {
  180. "Compaq NC7770 Gigabit Server Adapter"}, {
  181. "Compaq NC7780 Gigabit Server Adapter"}, {
  182. 0},};
  183. /* PCI Devices which use the 570x chipset */
  184. struct pci_device_table {
  185. unsigned short vendor_id, device_id; /* Vendor/DeviceID */
  186. unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
  187. unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
  188. unsigned long board_id; /* Data private to the driver */
  189. int io_size, min_latency;
  190. } bcm570xDevices[] = {
  191. {
  192. 0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL, 128, 32}, {
  193. 0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6, 128, 32}, {
  194. 0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6, 128, 32}, {
  195. 0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9, 128, 32}, {
  196. 0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9, 128, 32}, {
  197. 0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700, 128, 32}, {
  198. 0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700, 128, 32}, {
  199. 0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700, 128, 32}, {
  200. 0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700, 128, 32}, {
  201. 0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T, 128, 32}, {
  202. 0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST, 128, 32}, {
  203. 0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX, 128, 32}, {
  204. 0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T, 128, 32}, {
  205. 0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX, 128, 32}, {
  206. 0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01, 128, 32}, {
  207. 0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700, 128, 32}, {
  208. 0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5, 128, 32}, {
  209. 0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1, 128, 32}, {
  210. 0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8, 128, 32}, {
  211. 0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7, 128, 32}, {
  212. 0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10, 128, 32}, {
  213. 0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12, 128, 32}, {
  214. 0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770, 128, 32}, {
  215. 0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770, 128, 32}, {
  216. 0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780, 128, 32}, {
  217. 0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701, 128, 32}, {
  218. 0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX, 128, 32}, {
  219. 0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT, 128, 32}, {
  220. 0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T, 128, 32}, {
  221. 0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01, 128, 32}, {
  222. 0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701, 128, 32}, {
  223. 0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, {
  224. 0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, {
  225. 0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, {
  226. 0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, {
  227. 0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, {
  228. 0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, {
  229. 0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, {
  230. 0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, {
  231. 0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, {
  232. 0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, {
  233. 0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, {
  234. 0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, {
  235. 0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32}, {
  236. 0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, {
  237. 0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, {
  238. 0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, {
  239. 0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, {
  240. 0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, {
  241. 0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, {
  242. 0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32}
  243. };
  244. #define n570xDevices (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0]))
  245. /*
  246. * Allocate a packet buffer from the bcm570x packet pool.
  247. */
  248. void *bcm570xPktAlloc (int u, int pksize)
  249. {
  250. return malloc (pksize);
  251. }
  252. /*
  253. * Free a packet previously allocated from the bcm570x packet
  254. * buffer pool.
  255. */
  256. void bcm570xPktFree (int u, void *p)
  257. {
  258. free (p);
  259. }
  260. int bcm570xReplenishRxBuffers (PUM_DEVICE_BLOCK pUmDevice)
  261. {
  262. PLM_PACKET pPacket;
  263. PUM_PACKET pUmPacket;
  264. void *skb;
  265. int queue_rx = 0;
  266. int ret = 0;
  267. while ((pUmPacket = (PUM_PACKET)
  268. QQ_PopHead (&pUmDevice->rx_out_of_buf_q.Container)) != 0) {
  269. pPacket = (PLM_PACKET) pUmPacket;
  270. /* reuse an old skb */
  271. if (pUmPacket->skbuff) {
  272. QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
  273. pPacket);
  274. queue_rx = 1;
  275. continue;
  276. }
  277. if ((skb = bcm570xPktAlloc (pUmDevice->index,
  278. pPacket->u.Rx.RxBufferSize + 2)) ==
  279. 0) {
  280. QQ_PushHead (&pUmDevice->rx_out_of_buf_q.Container,
  281. pPacket);
  282. printf ("NOTICE: Out of RX memory.\n");
  283. ret = 1;
  284. break;
  285. }
  286. pUmPacket->skbuff = skb;
  287. QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
  288. queue_rx = 1;
  289. }
  290. if (queue_rx) {
  291. LM_QueueRxPackets (pDevice);
  292. }
  293. return ret;
  294. }
  295. /*
  296. * Probe, Map, and Init 570x device.
  297. */
  298. int eth_init (bd_t * bis)
  299. {
  300. int i, rv, devFound = FALSE;
  301. pci_dev_t devbusfn;
  302. unsigned short status;
  303. /* Find PCI device, if it exists, configure ... */
  304. for (i = 0; i < n570xDevices; i++) {
  305. devbusfn = pci_find_device (bcm570xDevices[i].vendor_id,
  306. bcm570xDevices[i].device_id, 0);
  307. if (devbusfn == -1) {
  308. continue; /* No device of that vendor/device ID */
  309. } else {
  310. /* Set ILINE */
  311. pci_write_config_byte (devbusfn,
  312. PCI_INTERRUPT_LINE,
  313. BCM570X_ILINE);
  314. /*
  315. * 0x10 - 0x14 define one 64-bit MBAR.
  316. * 0x14 is the higher-order address bits of the BAR.
  317. */
  318. pci_write_config_dword (devbusfn,
  319. PCI_BASE_ADDRESS_1, 0);
  320. ioBase = BCM570X_MBAR;
  321. pci_write_config_dword (devbusfn,
  322. PCI_BASE_ADDRESS_0, ioBase);
  323. /*
  324. * Enable PCI memory, IO, and Master -- don't
  325. * reset any status bits in doing so.
  326. */
  327. pci_read_config_word (devbusfn, PCI_COMMAND, &status);
  328. status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  329. pci_write_config_word (devbusfn, PCI_COMMAND, status);
  330. printf
  331. ("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n",
  332. board_info[bcm570xDevices[i].board_id].name,
  333. PCI_BUS (devbusfn), PCI_DEV (devbusfn),
  334. PCI_FUNC (devbusfn), ioBase);
  335. /* Allocate once, but always clear on init */
  336. if (!pDevice) {
  337. pDevice = malloc (sizeof (UM_DEVICE_BLOCK));
  338. pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  339. memset (pDevice, 0x0, sizeof (UM_DEVICE_BLOCK));
  340. }
  341. /* Configure pci dev structure */
  342. pUmDevice->pdev = devbusfn;
  343. pUmDevice->index = 0;
  344. pUmDevice->tx_pkt = 0;
  345. pUmDevice->rx_pkt = 0;
  346. devFound = TRUE;
  347. break;
  348. }
  349. }
  350. if (!devFound) {
  351. printf
  352. ("eth_init: FAILURE: no BCM570x Ethernet devices found.\n");
  353. return -1;
  354. }
  355. /* Setup defaults for chip */
  356. pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
  357. if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
  358. pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
  359. } else {
  360. if (rx_checksum[i]) {
  361. pDevice->TaskToOffload |=
  362. LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
  363. LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
  364. }
  365. if (tx_checksum[i]) {
  366. pDevice->TaskToOffload |=
  367. LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
  368. LM_TASK_OFFLOAD_TX_UDP_CHECKSUM;
  369. pDevice->NoTxPseudoHdrChksum = TRUE;
  370. }
  371. }
  372. /* Set Device PCI Memory base address */
  373. pDevice->pMappedMemBase = (PLM_UINT8) ioBase;
  374. /* Pull down adapter info */
  375. if ((rv = LM_GetAdapterInfo (pDevice)) != LM_STATUS_SUCCESS) {
  376. printf ("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv);
  377. return -2;
  378. }
  379. /* Lock not needed */
  380. pUmDevice->do_global_lock = 0;
  381. if (T3_ASIC_REV (pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) {
  382. /* The 5700 chip works best without interleaved register */
  383. /* accesses on certain machines. */
  384. pUmDevice->do_global_lock = 1;
  385. }
  386. /* Setup timer delays */
  387. if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
  388. pDevice->UseTaggedStatus = TRUE;
  389. pUmDevice->timer_interval = CONFIG_SYS_HZ;
  390. } else {
  391. pUmDevice->timer_interval = CONFIG_SYS_HZ / 50;
  392. }
  393. /* Grab name .... */
  394. pUmDevice->name =
  395. (char *)malloc (strlen (board_info[bcm570xDevices[i].board_id].name)
  396. + 1);
  397. strcpy (pUmDevice->name, board_info[bcm570xDevices[i].board_id].name);
  398. eth_getenv_enetaddr("ethaddr", pDevice->NodeAddress);
  399. LM_SetMacAddress (pDevice);
  400. /* Init queues .. */
  401. QQ_InitQueue (&pUmDevice->rx_out_of_buf_q.Container,
  402. MAX_RX_PACKET_DESC_COUNT);
  403. pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0;
  404. /* delay for 4 seconds */
  405. pUmDevice->delayed_link_ind = (4 * CONFIG_SYS_HZ) / pUmDevice->timer_interval;
  406. pUmDevice->adaptive_expiry = CONFIG_SYS_HZ / pUmDevice->timer_interval;
  407. /* Sometimes we get spurious ints. after reset when link is down. */
  408. /* This field tells the isr to service the int. even if there is */
  409. /* no status block update. */
  410. pUmDevice->adapter_just_inited =
  411. (3 * CONFIG_SYS_HZ) / pUmDevice->timer_interval;
  412. /* Initialize 570x */
  413. if (LM_InitializeAdapter (pDevice) != LM_STATUS_SUCCESS) {
  414. printf ("ERROR: Adapter initialization failed.\n");
  415. return ERROR;
  416. }
  417. /* Enable chip ISR */
  418. LM_EnableInterrupt (pDevice);
  419. /* Clear MC table */
  420. LM_MulticastClear (pDevice);
  421. /* Enable Multicast */
  422. LM_SetReceiveMask (pDevice,
  423. pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST);
  424. pUmDevice->opened = 1;
  425. pUmDevice->tx_full = 0;
  426. pUmDevice->tx_pkt = 0;
  427. pUmDevice->rx_pkt = 0;
  428. printf ("eth%d: %s @0x%lx,",
  429. pDevice->index, pUmDevice->name, (unsigned long)ioBase);
  430. printf ("node addr ");
  431. for (i = 0; i < 6; i++) {
  432. printf ("%2.2x", pDevice->NodeAddress[i]);
  433. }
  434. printf ("\n");
  435. printf ("eth%d: ", pDevice->index);
  436. printf ("%s with ", chip_rev[bcm570xDevices[i].board_id].name);
  437. if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID)
  438. printf ("Broadcom BCM5400 Copper ");
  439. else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
  440. printf ("Broadcom BCM5401 Copper ");
  441. else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID)
  442. printf ("Broadcom BCM5411 Copper ");
  443. else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID)
  444. printf ("Broadcom BCM5701 Integrated Copper ");
  445. else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID)
  446. printf ("Broadcom BCM5703 Integrated Copper ");
  447. else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID)
  448. printf ("Broadcom BCM8002 SerDes ");
  449. else if (pDevice->EnableTbi)
  450. printf ("Agilent HDMP-1636 SerDes ");
  451. else
  452. printf ("Unknown ");
  453. printf ("transceiver found\n");
  454. printf ("eth%d: %s, MTU: %d,",
  455. pDevice->index, pDevice->BusSpeedStr, 1500);
  456. if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && rx_checksum[i])
  457. printf ("Rx Checksum ON\n");
  458. else
  459. printf ("Rx Checksum OFF\n");
  460. initialized++;
  461. return 0;
  462. }
  463. /* Ethernet Interrupt service routine */
  464. void eth_isr (void)
  465. {
  466. LM_UINT32 oldtag, newtag;
  467. int i;
  468. pUmDevice->interrupt = 1;
  469. if (pDevice->UseTaggedStatus) {
  470. if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) ||
  471. pUmDevice->adapter_just_inited) {
  472. MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1);
  473. oldtag = pDevice->pStatusBlkVirt->StatusTag;
  474. for (i = 0;; i++) {
  475. pDevice->pStatusBlkVirt->Status &=
  476. ~STATUS_BLOCK_UPDATED;
  477. LM_ServiceInterrupts (pDevice);
  478. newtag = pDevice->pStatusBlkVirt->StatusTag;
  479. if ((newtag == oldtag) || (i > 50)) {
  480. MB_REG_WR (pDevice,
  481. Mailbox.Interrupt[0].Low,
  482. newtag << 24);
  483. if (pDevice->UndiFix) {
  484. REG_WR (pDevice, Grc.LocalCtrl,
  485. pDevice->
  486. GrcLocalCtrl | 0x2);
  487. }
  488. break;
  489. }
  490. oldtag = newtag;
  491. }
  492. }
  493. } else {
  494. while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
  495. unsigned int dummy;
  496. pDevice->pMemView->Mailbox.Interrupt[0].Low = 1;
  497. pDevice->pStatusBlkVirt->Status &=
  498. ~STATUS_BLOCK_UPDATED;
  499. LM_ServiceInterrupts (pDevice);
  500. pDevice->pMemView->Mailbox.Interrupt[0].Low = 0;
  501. dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low;
  502. }
  503. }
  504. /* Allocate new RX buffers */
  505. if (QQ_GetEntryCnt (&pUmDevice->rx_out_of_buf_q.Container)) {
  506. bcm570xReplenishRxBuffers (pUmDevice);
  507. }
  508. /* Queue packets */
  509. if (QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container)) {
  510. LM_QueueRxPackets (pDevice);
  511. }
  512. if (pUmDevice->tx_queued) {
  513. pUmDevice->tx_queued = 0;
  514. }
  515. if (pUmDevice->tx_full) {
  516. if (pDevice->LinkStatus != LM_STATUS_LINK_DOWN) {
  517. printf
  518. ("NOTICE: tx was previously blocked, restarting MUX\n");
  519. pUmDevice->tx_full = 0;
  520. }
  521. }
  522. pUmDevice->interrupt = 0;
  523. }
  524. int eth_send (volatile void *packet, int length)
  525. {
  526. int status = 0;
  527. #if ET_DEBUG
  528. unsigned char *ptr = (unsigned char *)packet;
  529. #endif
  530. PLM_PACKET pPacket;
  531. PUM_PACKET pUmPacket;
  532. /* Link down, return */
  533. while (pDevice->LinkStatus == LM_STATUS_LINK_DOWN) {
  534. #if 0
  535. printf ("eth%d: link down - check cable or link partner.\n",
  536. pUmDevice->index);
  537. #endif
  538. eth_isr ();
  539. /* Wait to see link for one-half a second before sending ... */
  540. udelay (1500000);
  541. }
  542. /* Clear sent flag */
  543. pUmDevice->tx_pkt = 0;
  544. /* Previously blocked */
  545. if (pUmDevice->tx_full) {
  546. printf ("eth%d: tx blocked.\n", pUmDevice->index);
  547. return 0;
  548. }
  549. pPacket = (PLM_PACKET)
  550. QQ_PopHead (&pDevice->TxPacketFreeQ.Container);
  551. if (pPacket == 0) {
  552. pUmDevice->tx_full = 1;
  553. printf ("bcm570xEndSend: TX full!\n");
  554. return 0;
  555. }
  556. if (pDevice->SendBdLeft.counter == 0) {
  557. pUmDevice->tx_full = 1;
  558. printf ("bcm570xEndSend: no more TX descriptors!\n");
  559. QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
  560. return 0;
  561. }
  562. if (length <= 0) {
  563. printf ("eth: bad packet size: %d\n", length);
  564. goto out;
  565. }
  566. /* Get packet buffers and fragment list */
  567. pUmPacket = (PUM_PACKET) pPacket;
  568. /* Single DMA Descriptor transmit.
  569. * Fragments may be provided, but one DMA descriptor max is
  570. * used to send the packet.
  571. */
  572. if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) {
  573. if (pUmPacket->skbuff == NULL) {
  574. /* Packet was discarded */
  575. printf ("TX: failed (1)\n");
  576. status = 1;
  577. } else {
  578. printf ("TX: failed (2)\n");
  579. status = 2;
  580. }
  581. QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
  582. return status;
  583. }
  584. /* Copy packet to DMA buffer */
  585. memset (pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE);
  586. memcpy ((void *)pUmPacket->skbuff, (void *)packet, length);
  587. pPacket->PacketSize = length;
  588. pPacket->Flags |= SND_BD_FLAG_END | SND_BD_FLAG_COAL_NOW;
  589. pPacket->u.Tx.FragCount = 1;
  590. /* We've already provided a frame ready for transmission */
  591. pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM;
  592. if (LM_SendPacket (pDevice, pPacket) == LM_STATUS_FAILURE) {
  593. /*
  594. * A lower level send failure will push the packet descriptor back
  595. * in the free queue, so just deal with the VxWorks clusters.
  596. */
  597. if (pUmPacket->skbuff == NULL) {
  598. printf ("TX failed (1)!\n");
  599. /* Packet was discarded */
  600. status = 3;
  601. } else {
  602. /* A resource problem ... */
  603. printf ("TX failed (2)!\n");
  604. status = 4;
  605. }
  606. if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) == 0) {
  607. printf ("TX: emptyQ!\n");
  608. pUmDevice->tx_full = 1;
  609. }
  610. }
  611. while (pUmDevice->tx_pkt == 0) {
  612. /* Service TX */
  613. eth_isr ();
  614. }
  615. #if ET_DEBUG
  616. printf ("eth_send: 0x%x, %d bytes\n"
  617. "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n",
  618. (int)pPacket, length,
  619. ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5],
  620. ptr[6], ptr[7], ptr[8], ptr[9], ptr[10], ptr[11], ptr[12],
  621. ptr[13], ptr[14], ptr[15]);
  622. #endif
  623. pUmDevice->tx_pkt = 0;
  624. QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
  625. /* Done with send */
  626. out:
  627. return status;
  628. }
  629. /* Ethernet receive */
  630. int eth_rx (void)
  631. {
  632. PLM_PACKET pPacket = NULL;
  633. PUM_PACKET pUmPacket = NULL;
  634. void *skb;
  635. int size = 0;
  636. while (TRUE) {
  637. bcm570x_service_isr:
  638. /* Pull down packet if it is there */
  639. eth_isr ();
  640. /* Indicate RX packets called */
  641. if (pUmDevice->rx_pkt) {
  642. /* printf("eth_rx: got a packet...\n"); */
  643. pUmDevice->rx_pkt = 0;
  644. } else {
  645. /* printf("eth_rx: waiting for packet...\n"); */
  646. goto bcm570x_service_isr;
  647. }
  648. pPacket = (PLM_PACKET)
  649. QQ_PopHead (&pDevice->RxPacketReceivedQ.Container);
  650. if (pPacket == 0) {
  651. printf ("eth_rx: empty packet!\n");
  652. goto bcm570x_service_isr;
  653. }
  654. pUmPacket = (PUM_PACKET) pPacket;
  655. #if ET_DEBUG
  656. printf ("eth_rx: packet @0x%x\n", (int)pPacket);
  657. #endif
  658. /* If the packet generated an error, reuse buffer */
  659. if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) ||
  660. ((size = pPacket->PacketSize) > pDevice->RxMtu)) {
  661. /* reuse skb */
  662. QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
  663. pPacket);
  664. printf ("eth_rx: error in packet dma!\n");
  665. goto bcm570x_service_isr;
  666. }
  667. /* Set size and address */
  668. skb = pUmPacket->skbuff;
  669. size = pPacket->PacketSize;
  670. /* Pass the packet up to the protocol
  671. * layers.
  672. */
  673. NetReceive (skb, size);
  674. /* Free packet buffer */
  675. bcm570xPktFree (pUmDevice->index, skb);
  676. pUmPacket->skbuff = NULL;
  677. /* Reuse SKB */
  678. QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
  679. return 0; /* Got a packet, bail ... */
  680. }
  681. return size;
  682. }
  683. /* Shut down device */
  684. void eth_halt (void)
  685. {
  686. int i;
  687. if (initialized)
  688. if (pDevice && pUmDevice && pUmDevice->opened) {
  689. printf ("\neth%d:%s,", pUmDevice->index,
  690. pUmDevice->name);
  691. printf ("HALT,");
  692. /* stop device */
  693. LM_Halt (pDevice);
  694. printf ("POWER DOWN,");
  695. LM_SetPowerState (pDevice, LM_POWER_STATE_D3);
  696. /* Free the memory allocated by the device in tigon3 */
  697. for (i = 0; i < pUmDevice->mem_list_num; i++) {
  698. if (pUmDevice->mem_list[i]) {
  699. /* sanity check */
  700. if (pUmDevice->dma_list[i]) { /* cache-safe memory */
  701. free (pUmDevice->mem_list[i]);
  702. } else {
  703. free (pUmDevice->mem_list[i]); /* normal memory */
  704. }
  705. }
  706. }
  707. pUmDevice->opened = 0;
  708. free (pDevice);
  709. pDevice = NULL;
  710. pUmDevice = NULL;
  711. initialized = 0;
  712. printf ("done - offline.\n");
  713. }
  714. }
  715. /*
  716. *
  717. * Middle Module: Interface between the HW driver (tigon3 modules) and
  718. * the native (SENS) driver. These routines implement the system
  719. * interface for tigon3 on VxWorks.
  720. */
  721. /* Middle module dependency - size of a packet descriptor */
  722. int MM_Packet_Desc_Size = sizeof (UM_PACKET);
  723. LM_STATUS
  724. MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice,
  725. LM_UINT32 Offset, LM_UINT32 * pValue32)
  726. {
  727. UM_DEVICE_BLOCK *pUmDevice;
  728. pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
  729. pci_read_config_dword (pUmDevice->pdev, Offset, (u32 *) pValue32);
  730. return LM_STATUS_SUCCESS;
  731. }
  732. LM_STATUS
  733. MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 Value32)
  734. {
  735. UM_DEVICE_BLOCK *pUmDevice;
  736. pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
  737. pci_write_config_dword (pUmDevice->pdev, Offset, Value32);
  738. return LM_STATUS_SUCCESS;
  739. }
  740. LM_STATUS
  741. MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice,
  742. LM_UINT32 Offset, LM_UINT16 * pValue16)
  743. {
  744. UM_DEVICE_BLOCK *pUmDevice;
  745. pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
  746. pci_read_config_word (pUmDevice->pdev, Offset, (u16 *) pValue16);
  747. return LM_STATUS_SUCCESS;
  748. }
  749. LM_STATUS
  750. MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT16 Value16)
  751. {
  752. UM_DEVICE_BLOCK *pUmDevice;
  753. pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
  754. pci_write_config_word (pUmDevice->pdev, Offset, Value16);
  755. return LM_STATUS_SUCCESS;
  756. }
  757. LM_STATUS
  758. MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
  759. PLM_VOID * pMemoryBlockVirt,
  760. PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, LM_BOOL Cached)
  761. {
  762. PLM_VOID pvirt;
  763. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  764. dma_addr_t mapping;
  765. pvirt = malloc (BlockSize);
  766. mapping = (dma_addr_t) (pvirt);
  767. if (!pvirt)
  768. return LM_STATUS_FAILURE;
  769. pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
  770. pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping;
  771. pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
  772. memset (pvirt, 0, BlockSize);
  773. *pMemoryBlockVirt = (PLM_VOID) pvirt;
  774. MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping);
  775. return LM_STATUS_SUCCESS;
  776. }
  777. LM_STATUS
  778. MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
  779. PLM_VOID * pMemoryBlockVirt)
  780. {
  781. PLM_VOID pvirt;
  782. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  783. pvirt = malloc (BlockSize);
  784. if (!pvirt)
  785. return LM_STATUS_FAILURE;
  786. pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
  787. pUmDevice->dma_list[pUmDevice->mem_list_num] = 0;
  788. pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
  789. memset (pvirt, 0, BlockSize);
  790. *pMemoryBlockVirt = pvirt;
  791. return LM_STATUS_SUCCESS;
  792. }
  793. LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice)
  794. {
  795. printf ("BCM570x PCI Memory base address @0x%x\n",
  796. (unsigned int)pDevice->pMappedMemBase);
  797. return LM_STATUS_SUCCESS;
  798. }
  799. LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice)
  800. {
  801. int i;
  802. void *skb;
  803. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  804. PUM_PACKET pUmPacket = NULL;
  805. PLM_PACKET pPacket = NULL;
  806. for (i = 0; i < pDevice->RxPacketDescCnt; i++) {
  807. pPacket = QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
  808. pUmPacket = (PUM_PACKET) pPacket;
  809. if (pPacket == 0) {
  810. printf ("MM_InitializeUmPackets: Bad RxPacketFreeQ\n");
  811. }
  812. skb = bcm570xPktAlloc (pUmDevice->index,
  813. pPacket->u.Rx.RxBufferSize + 2);
  814. if (skb == 0) {
  815. pUmPacket->skbuff = 0;
  816. QQ_PushTail (&pUmDevice->rx_out_of_buf_q.Container,
  817. pPacket);
  818. printf ("MM_InitializeUmPackets: out of buffer.\n");
  819. continue;
  820. }
  821. pUmPacket->skbuff = skb;
  822. QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
  823. }
  824. pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8;
  825. return LM_STATUS_SUCCESS;
  826. }
  827. LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice)
  828. {
  829. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  830. int index = pDevice->index;
  831. if (auto_speed[index] == 0)
  832. pDevice->DisableAutoNeg = TRUE;
  833. else
  834. pDevice->DisableAutoNeg = FALSE;
  835. if (line_speed[index] == 0) {
  836. pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
  837. pDevice->DisableAutoNeg = FALSE;
  838. } else {
  839. if (line_speed[index] == 1000) {
  840. if (pDevice->EnableTbi) {
  841. pDevice->RequestedMediaType =
  842. LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX;
  843. } else if (full_duplex[index]) {
  844. pDevice->RequestedMediaType =
  845. LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX;
  846. } else {
  847. pDevice->RequestedMediaType =
  848. LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS;
  849. }
  850. if (!pDevice->EnableTbi)
  851. pDevice->DisableAutoNeg = FALSE;
  852. } else if (line_speed[index] == 100) {
  853. if (full_duplex[index]) {
  854. pDevice->RequestedMediaType =
  855. LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX;
  856. } else {
  857. pDevice->RequestedMediaType =
  858. LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS;
  859. }
  860. } else if (line_speed[index] == 10) {
  861. if (full_duplex[index]) {
  862. pDevice->RequestedMediaType =
  863. LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX;
  864. } else {
  865. pDevice->RequestedMediaType =
  866. LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
  867. }
  868. } else {
  869. pDevice->RequestedMediaType =
  870. LM_REQUESTED_MEDIA_TYPE_AUTO;
  871. pDevice->DisableAutoNeg = FALSE;
  872. }
  873. }
  874. pDevice->FlowControlCap = 0;
  875. if (rx_flow_control[index] != 0) {
  876. pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
  877. }
  878. if (tx_flow_control[index] != 0) {
  879. pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
  880. }
  881. if ((auto_flow_control[index] != 0) &&
  882. (pDevice->DisableAutoNeg == FALSE)) {
  883. pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE;
  884. if ((tx_flow_control[index] == 0) &&
  885. (rx_flow_control[index] == 0)) {
  886. pDevice->FlowControlCap |=
  887. LM_FLOW_CONTROL_TRANSMIT_PAUSE |
  888. LM_FLOW_CONTROL_RECEIVE_PAUSE;
  889. }
  890. }
  891. /* Default MTU for now */
  892. pUmDevice->mtu = 1500;
  893. #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
  894. if (pUmDevice->mtu > 1500) {
  895. pDevice->RxMtu = pUmDevice->mtu;
  896. pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
  897. } else {
  898. pDevice->RxJumboDescCnt = 0;
  899. }
  900. pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index];
  901. #else
  902. pDevice->RxMtu = pUmDevice->mtu;
  903. #endif
  904. if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
  905. pDevice->UseTaggedStatus = TRUE;
  906. pUmDevice->timer_interval = CONFIG_SYS_HZ;
  907. } else {
  908. pUmDevice->timer_interval = CONFIG_SYS_HZ / 50;
  909. }
  910. pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index];
  911. pDevice->RxStdDescCnt = rx_std_desc_cnt[index];
  912. /* Note: adaptive coalescence really isn't adaptive in this driver */
  913. pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index];
  914. if (!pUmDevice->rx_adaptive_coalesce) {
  915. pDevice->RxCoalescingTicks = rx_coalesce_ticks[index];
  916. if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS)
  917. pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS;
  918. pUmDevice->rx_curr_coalesce_ticks = pDevice->RxCoalescingTicks;
  919. pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index];
  920. if (pDevice->RxMaxCoalescedFrames > MAX_RX_MAX_COALESCED_FRAMES)
  921. pDevice->RxMaxCoalescedFrames =
  922. MAX_RX_MAX_COALESCED_FRAMES;
  923. pUmDevice->rx_curr_coalesce_frames =
  924. pDevice->RxMaxCoalescedFrames;
  925. pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index];
  926. if (pDevice->StatsCoalescingTicks > MAX_STATS_COALESCING_TICKS)
  927. pDevice->StatsCoalescingTicks =
  928. MAX_STATS_COALESCING_TICKS;
  929. } else {
  930. pUmDevice->rx_curr_coalesce_frames =
  931. DEFAULT_RX_MAX_COALESCED_FRAMES;
  932. pUmDevice->rx_curr_coalesce_ticks = DEFAULT_RX_COALESCING_TICKS;
  933. }
  934. pDevice->TxCoalescingTicks = tx_coalesce_ticks[index];
  935. if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS)
  936. pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS;
  937. pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index];
  938. if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES)
  939. pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES;
  940. if (enable_wol[index]) {
  941. pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET;
  942. pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET;
  943. }
  944. pDevice->NicSendBd = TRUE;
  945. /* Don't update status blocks during interrupt */
  946. pDevice->RxCoalescingTicksDuringInt = 0;
  947. pDevice->TxCoalescingTicksDuringInt = 0;
  948. return LM_STATUS_SUCCESS;
  949. }
  950. LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
  951. {
  952. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  953. printf ("Start TX DMA: dev=%d packet @0x%x\n",
  954. (int)pUmDevice->index, (unsigned int)pPacket);
  955. return LM_STATUS_SUCCESS;
  956. }
  957. LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
  958. {
  959. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  960. printf ("Complete TX DMA: dev=%d packet @0x%x\n",
  961. (int)pUmDevice->index, (unsigned int)pPacket);
  962. return LM_STATUS_SUCCESS;
  963. }
  964. LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status)
  965. {
  966. char buf[128];
  967. char lcd[4];
  968. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  969. LM_FLOW_CONTROL flow_control;
  970. pUmDevice->delayed_link_ind = 0;
  971. memset (lcd, 0x0, 4);
  972. if (Status == LM_STATUS_LINK_DOWN) {
  973. sprintf (buf, "eth%d: %s: NIC Link is down\n",
  974. pUmDevice->index, pUmDevice->name);
  975. lcd[0] = 'L';
  976. lcd[1] = 'N';
  977. lcd[2] = 'K';
  978. lcd[3] = '?';
  979. } else if (Status == LM_STATUS_LINK_ACTIVE) {
  980. sprintf (buf, "eth%d:%s: ", pUmDevice->index, pUmDevice->name);
  981. if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) {
  982. strcat (buf, "1000 Mbps ");
  983. lcd[0] = '1';
  984. lcd[1] = 'G';
  985. lcd[2] = 'B';
  986. } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS) {
  987. strcat (buf, "100 Mbps ");
  988. lcd[0] = '1';
  989. lcd[1] = '0';
  990. lcd[2] = '0';
  991. } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) {
  992. strcat (buf, "10 Mbps ");
  993. lcd[0] = '1';
  994. lcd[1] = '0';
  995. lcd[2] = ' ';
  996. }
  997. if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) {
  998. strcat (buf, "full duplex");
  999. lcd[3] = 'F';
  1000. } else {
  1001. strcat (buf, "half duplex");
  1002. lcd[3] = 'H';
  1003. }
  1004. strcat (buf, " link up");
  1005. flow_control = pDevice->FlowControl &
  1006. (LM_FLOW_CONTROL_RECEIVE_PAUSE |
  1007. LM_FLOW_CONTROL_TRANSMIT_PAUSE);
  1008. if (flow_control) {
  1009. if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
  1010. strcat (buf, ", receive ");
  1011. if (flow_control &
  1012. LM_FLOW_CONTROL_TRANSMIT_PAUSE)
  1013. strcat (buf, " & transmit ");
  1014. } else {
  1015. strcat (buf, ", transmit ");
  1016. }
  1017. strcat (buf, "flow control ON");
  1018. } else {
  1019. strcat (buf, ", flow control OFF");
  1020. }
  1021. strcat (buf, "\n");
  1022. printf ("%s", buf);
  1023. }
  1024. #if 0
  1025. sysLedDsply (lcd[0], lcd[1], lcd[2], lcd[3]);
  1026. #endif
  1027. return LM_STATUS_SUCCESS;
  1028. }
  1029. LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
  1030. {
  1031. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  1032. PUM_PACKET pUmPacket;
  1033. void *skb;
  1034. pUmPacket = (PUM_PACKET) pPacket;
  1035. if ((skb = pUmPacket->skbuff))
  1036. bcm570xPktFree (pUmDevice->index, skb);
  1037. pUmPacket->skbuff = 0;
  1038. return LM_STATUS_SUCCESS;
  1039. }
  1040. unsigned long MM_AnGetCurrentTime_us (PAN_STATE_INFO pAnInfo)
  1041. {
  1042. return get_timer (0);
  1043. }
  1044. /*
  1045. * Transform an MBUF chain into a single MBUF.
  1046. * This routine will fail if the amount of data in the
  1047. * chain overflows a transmit buffer. In that case,
  1048. * the incoming MBUF chain will be freed. This routine can
  1049. * also fail by not being able to allocate a new MBUF (including
  1050. * cluster and mbuf headers). In that case the failure is
  1051. * non-fatal. The incoming cluster chain is not freed, giving
  1052. * the caller the choice of whether to try a retransmit later.
  1053. */
  1054. LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
  1055. {
  1056. PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
  1057. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  1058. void *skbnew;
  1059. int len = 0;
  1060. if (len == 0)
  1061. return (LM_STATUS_SUCCESS);
  1062. if (len > MAX_PACKET_SIZE) {
  1063. printf ("eth%d: xmit frame discarded, too big!, size = %d\n",
  1064. pUmDevice->index, len);
  1065. return (LM_STATUS_FAILURE);
  1066. }
  1067. skbnew = bcm570xPktAlloc (pUmDevice->index, MAX_PACKET_SIZE);
  1068. if (skbnew == NULL) {
  1069. pUmDevice->tx_full = 1;
  1070. printf ("eth%d: out of transmit buffers", pUmDevice->index);
  1071. return (LM_STATUS_FAILURE);
  1072. }
  1073. /* New packet values */
  1074. pUmPacket->skbuff = skbnew;
  1075. pUmPacket->lm_packet.u.Tx.FragCount = 1;
  1076. return (LM_STATUS_SUCCESS);
  1077. }
  1078. LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice)
  1079. {
  1080. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  1081. pUmDevice->rx_pkt = 1;
  1082. return LM_STATUS_SUCCESS;
  1083. }
  1084. LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice)
  1085. {
  1086. PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
  1087. PLM_PACKET pPacket;
  1088. PUM_PACKET pUmPacket;
  1089. void *skb;
  1090. while (TRUE) {
  1091. pPacket = (PLM_PACKET)
  1092. QQ_PopHead (&pDevice->TxPacketXmittedQ.Container);
  1093. if (pPacket == 0)
  1094. break;
  1095. pUmPacket = (PUM_PACKET) pPacket;
  1096. skb = (void *)pUmPacket->skbuff;
  1097. /*
  1098. * Free MBLK if we transmitted a fragmented packet or a
  1099. * non-fragmented packet straight from the VxWorks
  1100. * buffer pool. If packet was copied to a local transmit
  1101. * buffer, then there's no MBUF to free, just free
  1102. * the transmit buffer back to the cluster pool.
  1103. */
  1104. if (skb)
  1105. bcm570xPktFree (pUmDevice->index, skb);
  1106. pUmPacket->skbuff = 0;
  1107. QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket);
  1108. pUmDevice->tx_pkt = 1;
  1109. }
  1110. if (pUmDevice->tx_full) {
  1111. if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) >=
  1112. (QQ_GetSize (&pDevice->TxPacketFreeQ.Container) >> 1))
  1113. pUmDevice->tx_full = 0;
  1114. }
  1115. return LM_STATUS_SUCCESS;
  1116. }
  1117. /*
  1118. * Scan an MBUF chain until we reach fragment number "frag"
  1119. * Return its length and physical address.
  1120. */
  1121. void MM_MapTxDma
  1122. (PLM_DEVICE_BLOCK pDevice,
  1123. struct _LM_PACKET *pPacket,
  1124. T3_64BIT_HOST_ADDR * paddr, LM_UINT32 * len, int frag) {
  1125. PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
  1126. *len = pPacket->PacketSize;
  1127. MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff);
  1128. }
  1129. /*
  1130. * Convert an mbuf address, a CPU local virtual address,
  1131. * to a physical address as seen from a PCI device. Store the
  1132. * result at paddr.
  1133. */
  1134. void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice,
  1135. struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr)
  1136. {
  1137. PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
  1138. MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff);
  1139. }
  1140. void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr)
  1141. {
  1142. #if (BITS_PER_LONG == 64)
  1143. paddr->High = ((unsigned long)addr) >> 32;
  1144. paddr->Low = ((unsigned long)addr) & 0xffffffff;
  1145. #else
  1146. paddr->High = 0;
  1147. paddr->Low = (unsigned long)addr;
  1148. #endif
  1149. }
  1150. void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr)
  1151. {
  1152. unsigned long baddr = (unsigned long)addr;
  1153. #if (BITS_PER_LONG == 64)
  1154. set_64bit_addr (paddr, baddr & 0xffffffff, baddr >> 32);
  1155. #else
  1156. set_64bit_addr (paddr, baddr, 0);
  1157. #endif
  1158. }
  1159. /*
  1160. * This combination of `inline' and `extern' has almost the effect of a
  1161. * macro. The way to use it is to put a function definition in a header
  1162. * file with these keywords, and put another copy of the definition
  1163. * (lacking `inline' and `extern') in a library file. The definition in
  1164. * the header file will cause most calls to the function to be inlined.
  1165. * If any uses of the function remain, they will refer to the single copy
  1166. * in the library.
  1167. */
  1168. void atomic_set (atomic_t * entry, int val)
  1169. {
  1170. entry->counter = val;
  1171. }
  1172. int atomic_read (atomic_t * entry)
  1173. {
  1174. return entry->counter;
  1175. }
  1176. void atomic_inc (atomic_t * entry)
  1177. {
  1178. if (entry)
  1179. entry->counter++;
  1180. }
  1181. void atomic_dec (atomic_t * entry)
  1182. {
  1183. if (entry)
  1184. entry->counter--;
  1185. }
  1186. void atomic_sub (int a, atomic_t * entry)
  1187. {
  1188. if (entry)
  1189. entry->counter -= a;
  1190. }
  1191. void atomic_add (int a, atomic_t * entry)
  1192. {
  1193. if (entry)
  1194. entry->counter += a;
  1195. }
  1196. /******************************************************************************/
  1197. /* Description: */
  1198. /* */
  1199. /* Return: */
  1200. /******************************************************************************/
  1201. void QQ_InitQueue (PQQ_CONTAINER pQueue, unsigned int QueueSize)
  1202. {
  1203. pQueue->Head = 0;
  1204. pQueue->Tail = 0;
  1205. pQueue->Size = QueueSize + 1;
  1206. atomic_set (&pQueue->EntryCnt, 0);
  1207. } /* QQ_InitQueue */
  1208. /******************************************************************************/
  1209. /* Description: */
  1210. /* */
  1211. /* Return: */
  1212. /******************************************************************************/
  1213. char QQ_Full (PQQ_CONTAINER pQueue)
  1214. {
  1215. unsigned int NewHead;
  1216. NewHead = (pQueue->Head + 1) % pQueue->Size;
  1217. return (NewHead == pQueue->Tail);
  1218. } /* QQ_Full */
  1219. /******************************************************************************/
  1220. /* Description: */
  1221. /* */
  1222. /* Return: */
  1223. /******************************************************************************/
  1224. char QQ_Empty (PQQ_CONTAINER pQueue)
  1225. {
  1226. return (pQueue->Head == pQueue->Tail);
  1227. } /* QQ_Empty */
  1228. /******************************************************************************/
  1229. /* Description: */
  1230. /* */
  1231. /* Return: */
  1232. /******************************************************************************/
  1233. unsigned int QQ_GetSize (PQQ_CONTAINER pQueue)
  1234. {
  1235. return pQueue->Size;
  1236. } /* QQ_GetSize */
  1237. /******************************************************************************/
  1238. /* Description: */
  1239. /* */
  1240. /* Return: */
  1241. /******************************************************************************/
  1242. unsigned int QQ_GetEntryCnt (PQQ_CONTAINER pQueue)
  1243. {
  1244. return atomic_read (&pQueue->EntryCnt);
  1245. } /* QQ_GetEntryCnt */
  1246. /******************************************************************************/
  1247. /* Description: */
  1248. /* */
  1249. /* Return: */
  1250. /* TRUE entry was added successfully. */
  1251. /* FALSE queue is full. */
  1252. /******************************************************************************/
  1253. char QQ_PushHead (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry)
  1254. {
  1255. unsigned int Head;
  1256. Head = (pQueue->Head + 1) % pQueue->Size;
  1257. #if !defined(QQ_NO_OVERFLOW_CHECK)
  1258. if (Head == pQueue->Tail) {
  1259. return 0;
  1260. } /* if */
  1261. #endif /* QQ_NO_OVERFLOW_CHECK */
  1262. pQueue->Array[pQueue->Head] = pEntry;
  1263. wmb ();
  1264. pQueue->Head = Head;
  1265. atomic_inc (&pQueue->EntryCnt);
  1266. return -1;
  1267. } /* QQ_PushHead */
  1268. /******************************************************************************/
  1269. /* Description: */
  1270. /* */
  1271. /* Return: */
  1272. /* TRUE entry was added successfully. */
  1273. /* FALSE queue is full. */
  1274. /******************************************************************************/
  1275. char QQ_PushTail (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry)
  1276. {
  1277. unsigned int Tail;
  1278. Tail = pQueue->Tail;
  1279. if (Tail == 0) {
  1280. Tail = pQueue->Size;
  1281. } /* if */
  1282. Tail--;
  1283. #if !defined(QQ_NO_OVERFLOW_CHECK)
  1284. if (Tail == pQueue->Head) {
  1285. return 0;
  1286. } /* if */
  1287. #endif /* QQ_NO_OVERFLOW_CHECK */
  1288. pQueue->Array[Tail] = pEntry;
  1289. wmb ();
  1290. pQueue->Tail = Tail;
  1291. atomic_inc (&pQueue->EntryCnt);
  1292. return -1;
  1293. } /* QQ_PushTail */
  1294. /******************************************************************************/
  1295. /* Description: */
  1296. /* */
  1297. /* Return: */
  1298. /******************************************************************************/
  1299. PQQ_ENTRY QQ_PopHead (PQQ_CONTAINER pQueue)
  1300. {
  1301. unsigned int Head;
  1302. PQQ_ENTRY Entry;
  1303. Head = pQueue->Head;
  1304. #if !defined(QQ_NO_UNDERFLOW_CHECK)
  1305. if (Head == pQueue->Tail) {
  1306. return (PQQ_ENTRY) 0;
  1307. } /* if */
  1308. #endif /* QQ_NO_UNDERFLOW_CHECK */
  1309. if (Head == 0) {
  1310. Head = pQueue->Size;
  1311. } /* if */
  1312. Head--;
  1313. Entry = pQueue->Array[Head];
  1314. membar ();
  1315. pQueue->Head = Head;
  1316. atomic_dec (&pQueue->EntryCnt);
  1317. return Entry;
  1318. } /* QQ_PopHead */
  1319. /******************************************************************************/
  1320. /* Description: */
  1321. /* */
  1322. /* Return: */
  1323. /******************************************************************************/
  1324. PQQ_ENTRY QQ_PopTail (PQQ_CONTAINER pQueue)
  1325. {
  1326. unsigned int Tail;
  1327. PQQ_ENTRY Entry;
  1328. Tail = pQueue->Tail;
  1329. #if !defined(QQ_NO_UNDERFLOW_CHECK)
  1330. if (Tail == pQueue->Head) {
  1331. return (PQQ_ENTRY) 0;
  1332. } /* if */
  1333. #endif /* QQ_NO_UNDERFLOW_CHECK */
  1334. Entry = pQueue->Array[Tail];
  1335. membar ();
  1336. pQueue->Tail = (Tail + 1) % pQueue->Size;
  1337. atomic_dec (&pQueue->EntryCnt);
  1338. return Entry;
  1339. } /* QQ_PopTail */
  1340. /******************************************************************************/
  1341. /* Description: */
  1342. /* */
  1343. /* Return: */
  1344. /******************************************************************************/
  1345. PQQ_ENTRY QQ_GetHead (PQQ_CONTAINER pQueue, unsigned int Idx)
  1346. {
  1347. if (Idx >= atomic_read (&pQueue->EntryCnt)) {
  1348. return (PQQ_ENTRY) 0;
  1349. }
  1350. if (pQueue->Head > Idx) {
  1351. Idx = pQueue->Head - Idx;
  1352. } else {
  1353. Idx = pQueue->Size - (Idx - pQueue->Head);
  1354. }
  1355. Idx--;
  1356. return pQueue->Array[Idx];
  1357. }
  1358. /******************************************************************************/
  1359. /* Description: */
  1360. /* */
  1361. /* Return: */
  1362. /******************************************************************************/
  1363. PQQ_ENTRY QQ_GetTail (PQQ_CONTAINER pQueue, unsigned int Idx)
  1364. {
  1365. if (Idx >= atomic_read (&pQueue->EntryCnt)) {
  1366. return (PQQ_ENTRY) 0;
  1367. }
  1368. Idx += pQueue->Tail;
  1369. if (Idx >= pQueue->Size) {
  1370. Idx = Idx - pQueue->Size;
  1371. }
  1372. return pQueue->Array[Idx];
  1373. }