ahci.c 19 KB

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  1. /*
  2. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  3. * Author: Jason Jin<Jason.jin@freescale.com>
  4. * Zhang Wei<wei.zhang@freescale.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. *
  24. * with the reference on libata and ahci drvier in kernel
  25. *
  26. */
  27. #include <common.h>
  28. #include <command.h>
  29. #include <pci.h>
  30. #include <asm/processor.h>
  31. #include <asm/errno.h>
  32. #include <asm/io.h>
  33. #include <malloc.h>
  34. #include <scsi.h>
  35. #include <ata.h>
  36. #include <linux/ctype.h>
  37. #include <ahci.h>
  38. struct ahci_probe_ent *probe_ent = NULL;
  39. hd_driveid_t *ataid[AHCI_MAX_PORTS];
  40. #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
  41. /*
  42. * Some controllers limit number of blocks they can read at once. Contemporary
  43. * SSD devices work much faster if the read size is aligned to a power of 2.
  44. * Let's set default to 128 and allowing to be overwritten if needed.
  45. */
  46. #ifndef MAX_SATA_BLOCKS_READ
  47. #define MAX_SATA_BLOCKS_READ 0x80
  48. #endif
  49. static inline u32 ahci_port_base(u32 base, u32 port)
  50. {
  51. return base + 0x100 + (port * 0x80);
  52. }
  53. static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
  54. unsigned int port_idx)
  55. {
  56. base = ahci_port_base(base, port_idx);
  57. port->cmd_addr = base;
  58. port->scr_addr = base + PORT_SCR;
  59. }
  60. #define msleep(a) udelay(a * 1000)
  61. #define ssleep(a) msleep(a * 1000)
  62. static int waiting_for_cmd_completed(volatile u8 *offset,
  63. int timeout_msec,
  64. u32 sign)
  65. {
  66. int i;
  67. u32 status;
  68. for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
  69. msleep(1);
  70. return (i < timeout_msec) ? 0 : -1;
  71. }
  72. static int ahci_host_init(struct ahci_probe_ent *probe_ent)
  73. {
  74. #ifndef CONFIG_SCSI_AHCI_PLAT
  75. pci_dev_t pdev = probe_ent->dev;
  76. u16 tmp16;
  77. unsigned short vendor;
  78. #endif
  79. volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
  80. u32 tmp, cap_save;
  81. int i, j;
  82. volatile u8 *port_mmio;
  83. debug("ahci_host_init: start\n");
  84. cap_save = readl(mmio + HOST_CAP);
  85. cap_save &= ((1 << 28) | (1 << 17));
  86. cap_save |= (1 << 27);
  87. /* global controller reset */
  88. tmp = readl(mmio + HOST_CTL);
  89. if ((tmp & HOST_RESET) == 0)
  90. writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
  91. /* reset must complete within 1 second, or
  92. * the hardware should be considered fried.
  93. */
  94. ssleep(1);
  95. tmp = readl(mmio + HOST_CTL);
  96. if (tmp & HOST_RESET) {
  97. debug("controller reset failed (0x%x)\n", tmp);
  98. return -1;
  99. }
  100. writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
  101. writel(cap_save, mmio + HOST_CAP);
  102. writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
  103. #ifndef CONFIG_SCSI_AHCI_PLAT
  104. pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
  105. if (vendor == PCI_VENDOR_ID_INTEL) {
  106. u16 tmp16;
  107. pci_read_config_word(pdev, 0x92, &tmp16);
  108. tmp16 |= 0xf;
  109. pci_write_config_word(pdev, 0x92, tmp16);
  110. }
  111. #endif
  112. probe_ent->cap = readl(mmio + HOST_CAP);
  113. probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
  114. probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
  115. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  116. probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
  117. if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
  118. probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
  119. for (i = 0; i < probe_ent->n_ports; i++) {
  120. probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
  121. port_mmio = (u8 *) probe_ent->port[i].port_mmio;
  122. ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
  123. /* make sure port is not active */
  124. tmp = readl(port_mmio + PORT_CMD);
  125. if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  126. PORT_CMD_FIS_RX | PORT_CMD_START)) {
  127. tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  128. PORT_CMD_FIS_RX | PORT_CMD_START);
  129. writel_with_flush(tmp, port_mmio + PORT_CMD);
  130. /* spec says 500 msecs for each bit, so
  131. * this is slightly incorrect.
  132. */
  133. msleep(500);
  134. }
  135. writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
  136. j = 0;
  137. while (j < 100) {
  138. msleep(10);
  139. tmp = readl(port_mmio + PORT_SCR_STAT);
  140. if ((tmp & 0xf) == 0x3)
  141. break;
  142. j++;
  143. }
  144. tmp = readl(port_mmio + PORT_SCR_ERR);
  145. debug("PORT_SCR_ERR 0x%x\n", tmp);
  146. writel(tmp, port_mmio + PORT_SCR_ERR);
  147. /* ack any pending irq events for this port */
  148. tmp = readl(port_mmio + PORT_IRQ_STAT);
  149. debug("PORT_IRQ_STAT 0x%x\n", tmp);
  150. if (tmp)
  151. writel(tmp, port_mmio + PORT_IRQ_STAT);
  152. writel(1 << i, mmio + HOST_IRQ_STAT);
  153. /* set irq mask (enables interrupts) */
  154. writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
  155. /*register linkup ports */
  156. tmp = readl(port_mmio + PORT_SCR_STAT);
  157. debug("Port %d status: 0x%x\n", i, tmp);
  158. if ((tmp & 0xf) == 0x03)
  159. probe_ent->link_port_map |= (0x01 << i);
  160. }
  161. tmp = readl(mmio + HOST_CTL);
  162. debug("HOST_CTL 0x%x\n", tmp);
  163. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  164. tmp = readl(mmio + HOST_CTL);
  165. debug("HOST_CTL 0x%x\n", tmp);
  166. #ifndef CONFIG_SCSI_AHCI_PLAT
  167. pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
  168. tmp |= PCI_COMMAND_MASTER;
  169. pci_write_config_word(pdev, PCI_COMMAND, tmp16);
  170. #endif
  171. return 0;
  172. }
  173. static void ahci_print_info(struct ahci_probe_ent *probe_ent)
  174. {
  175. #ifndef CONFIG_SCSI_AHCI_PLAT
  176. pci_dev_t pdev = probe_ent->dev;
  177. u16 cc;
  178. #endif
  179. volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
  180. u32 vers, cap, impl, speed;
  181. const char *speed_s;
  182. const char *scc_s;
  183. vers = readl(mmio + HOST_VERSION);
  184. cap = probe_ent->cap;
  185. impl = probe_ent->port_map;
  186. speed = (cap >> 20) & 0xf;
  187. if (speed == 1)
  188. speed_s = "1.5";
  189. else if (speed == 2)
  190. speed_s = "3";
  191. else
  192. speed_s = "?";
  193. #ifdef CONFIG_SCSI_AHCI_PLAT
  194. scc_s = "SATA";
  195. #else
  196. pci_read_config_word(pdev, 0x0a, &cc);
  197. if (cc == 0x0101)
  198. scc_s = "IDE";
  199. else if (cc == 0x0106)
  200. scc_s = "SATA";
  201. else if (cc == 0x0104)
  202. scc_s = "RAID";
  203. else
  204. scc_s = "unknown";
  205. #endif
  206. printf("AHCI %02x%02x.%02x%02x "
  207. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  208. (vers >> 24) & 0xff,
  209. (vers >> 16) & 0xff,
  210. (vers >> 8) & 0xff,
  211. vers & 0xff,
  212. ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
  213. printf("flags: "
  214. "%s%s%s%s%s%s"
  215. "%s%s%s%s%s%s%s\n",
  216. cap & (1 << 31) ? "64bit " : "",
  217. cap & (1 << 30) ? "ncq " : "",
  218. cap & (1 << 28) ? "ilck " : "",
  219. cap & (1 << 27) ? "stag " : "",
  220. cap & (1 << 26) ? "pm " : "",
  221. cap & (1 << 25) ? "led " : "",
  222. cap & (1 << 24) ? "clo " : "",
  223. cap & (1 << 19) ? "nz " : "",
  224. cap & (1 << 18) ? "only " : "",
  225. cap & (1 << 17) ? "pmp " : "",
  226. cap & (1 << 15) ? "pio " : "",
  227. cap & (1 << 14) ? "slum " : "",
  228. cap & (1 << 13) ? "part " : "");
  229. }
  230. #ifndef CONFIG_SCSI_AHCI_PLAT
  231. static int ahci_init_one(pci_dev_t pdev)
  232. {
  233. u16 vendor;
  234. int rc;
  235. memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
  236. probe_ent = malloc(sizeof(struct ahci_probe_ent));
  237. memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
  238. probe_ent->dev = pdev;
  239. probe_ent->host_flags = ATA_FLAG_SATA
  240. | ATA_FLAG_NO_LEGACY
  241. | ATA_FLAG_MMIO
  242. | ATA_FLAG_PIO_DMA
  243. | ATA_FLAG_NO_ATAPI;
  244. probe_ent->pio_mask = 0x1f;
  245. probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  246. pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
  247. debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
  248. /* Take from kernel:
  249. * JMicron-specific fixup:
  250. * make sure we're in AHCI mode
  251. */
  252. pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
  253. if (vendor == 0x197b)
  254. pci_write_config_byte(pdev, 0x41, 0xa1);
  255. /* initialize adapter */
  256. rc = ahci_host_init(probe_ent);
  257. if (rc)
  258. goto err_out;
  259. ahci_print_info(probe_ent);
  260. return 0;
  261. err_out:
  262. return rc;
  263. }
  264. #endif
  265. #define MAX_DATA_BYTE_COUNT (4*1024*1024)
  266. static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
  267. {
  268. struct ahci_ioports *pp = &(probe_ent->port[port]);
  269. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  270. u32 sg_count;
  271. int i;
  272. sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
  273. if (sg_count > AHCI_MAX_SG) {
  274. printf("Error:Too much sg!\n");
  275. return -1;
  276. }
  277. for (i = 0; i < sg_count; i++) {
  278. ahci_sg->addr =
  279. cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
  280. ahci_sg->addr_hi = 0;
  281. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  282. (buf_len < MAX_DATA_BYTE_COUNT
  283. ? (buf_len - 1)
  284. : (MAX_DATA_BYTE_COUNT - 1)));
  285. ahci_sg++;
  286. buf_len -= MAX_DATA_BYTE_COUNT;
  287. }
  288. return sg_count;
  289. }
  290. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
  291. {
  292. pp->cmd_slot->opts = cpu_to_le32(opts);
  293. pp->cmd_slot->status = 0;
  294. pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
  295. pp->cmd_slot->tbl_addr_hi = 0;
  296. }
  297. static void ahci_set_feature(u8 port)
  298. {
  299. struct ahci_ioports *pp = &(probe_ent->port[port]);
  300. volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
  301. u32 cmd_fis_len = 5; /* five dwords */
  302. u8 fis[20];
  303. /*set feature */
  304. memset(fis, 0, 20);
  305. fis[0] = 0x27;
  306. fis[1] = 1 << 7;
  307. fis[2] = ATA_CMD_SETF;
  308. fis[3] = SETFEATURES_XFER;
  309. fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
  310. memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
  311. ahci_fill_cmd_slot(pp, cmd_fis_len);
  312. writel(1, port_mmio + PORT_CMD_ISSUE);
  313. readl(port_mmio + PORT_CMD_ISSUE);
  314. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
  315. printf("set feature error!\n");
  316. }
  317. }
  318. static int ahci_port_start(u8 port)
  319. {
  320. struct ahci_ioports *pp = &(probe_ent->port[port]);
  321. volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
  322. u32 port_status;
  323. u32 mem;
  324. debug("Enter start port: %d\n", port);
  325. port_status = readl(port_mmio + PORT_SCR_STAT);
  326. debug("Port %d status: %x\n", port, port_status);
  327. if ((port_status & 0xf) != 0x03) {
  328. printf("No Link on this port!\n");
  329. return -1;
  330. }
  331. mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
  332. if (!mem) {
  333. free(pp);
  334. printf("No mem for table!\n");
  335. return -ENOMEM;
  336. }
  337. mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
  338. memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  339. /*
  340. * First item in chunk of DMA memory: 32-slot command table,
  341. * 32 bytes each in size
  342. */
  343. pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
  344. debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
  345. mem += (AHCI_CMD_SLOT_SZ + 224);
  346. /*
  347. * Second item: Received-FIS area
  348. */
  349. pp->rx_fis = mem;
  350. mem += AHCI_RX_FIS_SZ;
  351. /*
  352. * Third item: data area for storing a single command
  353. * and its scatter-gather table
  354. */
  355. pp->cmd_tbl = mem;
  356. debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
  357. mem += AHCI_CMD_TBL_HDR;
  358. pp->cmd_tbl_sg = (struct ahci_sg *)mem;
  359. writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
  360. writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
  361. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  362. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  363. PORT_CMD_START, port_mmio + PORT_CMD);
  364. debug("Exit start port %d\n", port);
  365. return 0;
  366. }
  367. static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
  368. int buf_len)
  369. {
  370. struct ahci_ioports *pp = &(probe_ent->port[port]);
  371. volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
  372. u32 opts;
  373. u32 port_status;
  374. int sg_count;
  375. debug("Enter get_ahci_device_data: for port %d\n", port);
  376. if (port > probe_ent->n_ports) {
  377. printf("Invaild port number %d\n", port);
  378. return -1;
  379. }
  380. port_status = readl(port_mmio + PORT_SCR_STAT);
  381. if ((port_status & 0xf) != 0x03) {
  382. debug("No Link on port %d!\n", port);
  383. return -1;
  384. }
  385. memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
  386. sg_count = ahci_fill_sg(port, buf, buf_len);
  387. opts = (fis_len >> 2) | (sg_count << 16);
  388. ahci_fill_cmd_slot(pp, opts);
  389. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  390. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
  391. printf("timeout exit!\n");
  392. return -1;
  393. }
  394. debug("get_ahci_device_data: %d byte transferred.\n",
  395. pp->cmd_slot->status);
  396. return 0;
  397. }
  398. static char *ata_id_strcpy(u16 *target, u16 *src, int len)
  399. {
  400. int i;
  401. for (i = 0; i < len / 2; i++)
  402. target[i] = swab16(src[i]);
  403. return (char *)target;
  404. }
  405. static void dump_ataid(hd_driveid_t *ataid)
  406. {
  407. debug("(49)ataid->capability = 0x%x\n", ataid->capability);
  408. debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
  409. debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
  410. debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
  411. debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
  412. debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
  413. debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
  414. debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
  415. debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
  416. debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
  417. debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
  418. debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
  419. debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
  420. debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
  421. debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
  422. }
  423. /*
  424. * SCSI INQUIRY command operation.
  425. */
  426. static int ata_scsiop_inquiry(ccb *pccb)
  427. {
  428. u8 hdr[] = {
  429. 0,
  430. 0,
  431. 0x5, /* claim SPC-3 version compatibility */
  432. 2,
  433. 95 - 4,
  434. };
  435. u8 fis[20];
  436. u8 *tmpid;
  437. u8 port;
  438. /* Clean ccb data buffer */
  439. memset(pccb->pdata, 0, pccb->datalen);
  440. memcpy(pccb->pdata, hdr, sizeof(hdr));
  441. if (pccb->datalen <= 35)
  442. return 0;
  443. memset(fis, 0, 20);
  444. /* Construct the FIS */
  445. fis[0] = 0x27; /* Host to device FIS. */
  446. fis[1] = 1 << 7; /* Command FIS. */
  447. fis[2] = ATA_CMD_IDENT; /* Command byte. */
  448. /* Read id from sata */
  449. port = pccb->target;
  450. if (!(tmpid = malloc(sizeof(hd_driveid_t))))
  451. return -ENOMEM;
  452. if (get_ahci_device_data(port, (u8 *) & fis, 20,
  453. tmpid, sizeof(hd_driveid_t))) {
  454. debug("scsi_ahci: SCSI inquiry command failure.\n");
  455. return -EIO;
  456. }
  457. if (ataid[port])
  458. free(ataid[port]);
  459. ataid[port] = (hd_driveid_t *) tmpid;
  460. memcpy(&pccb->pdata[8], "ATA ", 8);
  461. ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
  462. ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
  463. dump_ataid(ataid[port]);
  464. return 0;
  465. }
  466. /*
  467. * SCSI READ10 command operation.
  468. */
  469. static int ata_scsiop_read10(ccb * pccb)
  470. {
  471. u32 lba = 0;
  472. u16 blocks = 0;
  473. u8 fis[20];
  474. u8 *user_buffer = pccb->pdata;
  475. u32 user_buffer_size = pccb->datalen;
  476. /* Retrieve the base LBA number from the ccb structure. */
  477. memcpy(&lba, pccb->cmd + 2, sizeof(lba));
  478. lba = be32_to_cpu(lba);
  479. /*
  480. * And the number of blocks.
  481. *
  482. * For 10-byte and 16-byte SCSI R/W commands, transfer
  483. * length 0 means transfer 0 block of data.
  484. * However, for ATA R/W commands, sector count 0 means
  485. * 256 or 65536 sectors, not 0 sectors as in SCSI.
  486. *
  487. * WARNING: one or two older ATA drives treat 0 as 0...
  488. */
  489. blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
  490. debug("scsi_ahci: read %d blocks starting from lba 0x%x\n",
  491. (unsigned)lba, blocks);
  492. /* Preset the FIS */
  493. memset(fis, 0, 20);
  494. fis[0] = 0x27; /* Host to device FIS. */
  495. fis[1] = 1 << 7; /* Command FIS. */
  496. fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
  497. while (blocks) {
  498. u16 now_blocks; /* number of blocks per iteration */
  499. u32 transfer_size; /* number of bytes per iteration */
  500. now_blocks = min(MAX_SATA_BLOCKS_READ, blocks);
  501. transfer_size = ATA_BLOCKSIZE * now_blocks;
  502. if (transfer_size > user_buffer_size) {
  503. printf("scsi_ahci: Error: buffer too small.\n");
  504. return -EIO;
  505. }
  506. /* LBA address, only support LBA28 in this driver */
  507. fis[4] = (lba >> 0) & 0xff;
  508. fis[5] = (lba >> 8) & 0xff;
  509. fis[6] = (lba >> 16) & 0xff;
  510. fis[7] = ((lba >> 24) & 0xf) | 0xe0;
  511. /* Block (sector) count */
  512. fis[12] = (now_blocks >> 0) & 0xff;
  513. fis[13] = (now_blocks >> 8) & 0xff;
  514. /* Read from ahci */
  515. if (get_ahci_device_data(pccb->target, (u8 *) &fis, sizeof(fis),
  516. user_buffer, user_buffer_size)) {
  517. debug("scsi_ahci: SCSI READ10 command failure.\n");
  518. return -EIO;
  519. }
  520. user_buffer += transfer_size;
  521. user_buffer_size -= transfer_size;
  522. blocks -= now_blocks;
  523. lba += now_blocks;
  524. }
  525. return 0;
  526. }
  527. /*
  528. * SCSI READ CAPACITY10 command operation.
  529. */
  530. static int ata_scsiop_read_capacity10(ccb *pccb)
  531. {
  532. u32 cap;
  533. if (!ataid[pccb->target]) {
  534. printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
  535. "\tNo ATA info!\n"
  536. "\tPlease run SCSI commmand INQUIRY firstly!\n");
  537. return -EPERM;
  538. }
  539. cap = be32_to_cpu(ataid[pccb->target]->lba_capacity);
  540. memcpy(pccb->pdata, &cap, sizeof(cap));
  541. pccb->pdata[4] = pccb->pdata[5] = 0;
  542. pccb->pdata[6] = 512 >> 8;
  543. pccb->pdata[7] = 512 & 0xff;
  544. return 0;
  545. }
  546. /*
  547. * SCSI TEST UNIT READY command operation.
  548. */
  549. static int ata_scsiop_test_unit_ready(ccb *pccb)
  550. {
  551. return (ataid[pccb->target]) ? 0 : -EPERM;
  552. }
  553. int scsi_exec(ccb *pccb)
  554. {
  555. int ret;
  556. switch (pccb->cmd[0]) {
  557. case SCSI_READ10:
  558. ret = ata_scsiop_read10(pccb);
  559. break;
  560. case SCSI_RD_CAPAC:
  561. ret = ata_scsiop_read_capacity10(pccb);
  562. break;
  563. case SCSI_TST_U_RDY:
  564. ret = ata_scsiop_test_unit_ready(pccb);
  565. break;
  566. case SCSI_INQUIRY:
  567. ret = ata_scsiop_inquiry(pccb);
  568. break;
  569. default:
  570. printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
  571. return FALSE;
  572. }
  573. if (ret) {
  574. debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
  575. return FALSE;
  576. }
  577. return TRUE;
  578. }
  579. void scsi_low_level_init(int busdevfunc)
  580. {
  581. int i;
  582. u32 linkmap;
  583. #ifndef CONFIG_SCSI_AHCI_PLAT
  584. ahci_init_one(busdevfunc);
  585. #endif
  586. linkmap = probe_ent->link_port_map;
  587. for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
  588. if (((linkmap >> i) & 0x01)) {
  589. if (ahci_port_start((u8) i)) {
  590. printf("Can not start port %d\n", i);
  591. continue;
  592. }
  593. ahci_set_feature((u8) i);
  594. }
  595. }
  596. }
  597. #ifdef CONFIG_SCSI_AHCI_PLAT
  598. int ahci_init(u32 base)
  599. {
  600. int i, rc = 0;
  601. u32 linkmap;
  602. memset(ataid, 0, sizeof(ataid));
  603. probe_ent = malloc(sizeof(struct ahci_probe_ent));
  604. memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
  605. probe_ent->host_flags = ATA_FLAG_SATA
  606. | ATA_FLAG_NO_LEGACY
  607. | ATA_FLAG_MMIO
  608. | ATA_FLAG_PIO_DMA
  609. | ATA_FLAG_NO_ATAPI;
  610. probe_ent->pio_mask = 0x1f;
  611. probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  612. probe_ent->mmio_base = base;
  613. /* initialize adapter */
  614. rc = ahci_host_init(probe_ent);
  615. if (rc)
  616. goto err_out;
  617. ahci_print_info(probe_ent);
  618. linkmap = probe_ent->link_port_map;
  619. for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
  620. if (((linkmap >> i) & 0x01)) {
  621. if (ahci_port_start((u8) i)) {
  622. printf("Can not start port %d\n", i);
  623. continue;
  624. }
  625. ahci_set_feature((u8) i);
  626. }
  627. }
  628. err_out:
  629. return rc;
  630. }
  631. #endif
  632. void scsi_bus_reset(void)
  633. {
  634. /*Not implement*/
  635. }
  636. void scsi_print_error(ccb * pccb)
  637. {
  638. /*The ahci error info can be read in the ahci driver*/
  639. }