ehci.h 6.1 KB

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  1. /*-
  2. * Copyright (c) 2007-2008, Juniper Networks, Inc.
  3. * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
  4. * All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2 of
  9. * the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. */
  21. #ifndef USB_EHCI_H
  22. #define USB_EHCI_H
  23. #if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
  24. #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
  25. #endif
  26. /* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
  27. #define DeviceRequest \
  28. ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
  29. #define DeviceOutRequest \
  30. ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
  31. #define InterfaceRequest \
  32. ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
  33. #define EndpointRequest \
  34. ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
  35. #define EndpointOutRequest \
  36. ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
  37. /*
  38. * Register Space.
  39. */
  40. struct ehci_hccr {
  41. uint32_t cr_capbase;
  42. #define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
  43. #define HC_VERSION(p) (((p) >> 16) & 0xffff)
  44. uint32_t cr_hcsparams;
  45. #define HCS_PPC(p) ((p) & (1 << 4))
  46. #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
  47. #define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
  48. uint32_t cr_hccparams;
  49. uint8_t cr_hcsp_portrt[8];
  50. } __attribute__ ((packed));
  51. struct ehci_hcor {
  52. uint32_t or_usbcmd;
  53. #define CMD_PARK (1 << 11) /* enable "park" */
  54. #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
  55. #define CMD_ASE (1 << 5) /* async schedule enable */
  56. #define CMD_LRESET (1 << 7) /* partial reset */
  57. #define CMD_IAAD (1 << 5) /* "doorbell" interrupt */
  58. #define CMD_PSE (1 << 4) /* periodic schedule enable */
  59. #define CMD_RESET (1 << 1) /* reset HC not bus */
  60. #define CMD_RUN (1 << 0) /* start/stop HC */
  61. uint32_t or_usbsts;
  62. #define STD_ASS (1 << 15)
  63. #define STS_HALT (1 << 12)
  64. uint32_t or_usbintr;
  65. uint32_t or_frindex;
  66. uint32_t or_ctrldssegment;
  67. uint32_t or_periodiclistbase;
  68. uint32_t or_asynclistaddr;
  69. uint32_t _reserved_[9];
  70. uint32_t or_configflag;
  71. #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
  72. uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
  73. uint32_t or_systune;
  74. } __attribute__ ((packed));
  75. #define USBMODE 0x68 /* USB Device mode */
  76. #define USBMODE_SDIS (1 << 3) /* Stream disable */
  77. #define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
  78. #define USBMODE_CM_HC (3 << 0) /* host controller mode */
  79. #define USBMODE_CM_IDLE (0 << 0) /* idle state */
  80. /* Interface descriptor */
  81. struct usb_linux_interface_descriptor {
  82. unsigned char bLength;
  83. unsigned char bDescriptorType;
  84. unsigned char bInterfaceNumber;
  85. unsigned char bAlternateSetting;
  86. unsigned char bNumEndpoints;
  87. unsigned char bInterfaceClass;
  88. unsigned char bInterfaceSubClass;
  89. unsigned char bInterfaceProtocol;
  90. unsigned char iInterface;
  91. } __attribute__ ((packed));
  92. /* Configuration descriptor information.. */
  93. struct usb_linux_config_descriptor {
  94. unsigned char bLength;
  95. unsigned char bDescriptorType;
  96. unsigned short wTotalLength;
  97. unsigned char bNumInterfaces;
  98. unsigned char bConfigurationValue;
  99. unsigned char iConfiguration;
  100. unsigned char bmAttributes;
  101. unsigned char MaxPower;
  102. } __attribute__ ((packed));
  103. #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
  104. #define ehci_readl(x) (*((volatile u32 *)(x)))
  105. #define ehci_writel(a, b) (*((volatile u32 *)(a)) = ((volatile u32)b))
  106. #else
  107. #define ehci_readl(x) cpu_to_le32((*((volatile u32 *)(x))))
  108. #define ehci_writel(a, b) (*((volatile u32 *)(a)) = \
  109. cpu_to_le32(((volatile u32)b)))
  110. #endif
  111. #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
  112. #define hc32_to_cpu(x) be32_to_cpu((x))
  113. #define cpu_to_hc32(x) cpu_to_be32((x))
  114. #else
  115. #define hc32_to_cpu(x) le32_to_cpu((x))
  116. #define cpu_to_hc32(x) cpu_to_le32((x))
  117. #endif
  118. #define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
  119. #define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
  120. #define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
  121. #define EHCI_PS_PO (1 << 13) /* RW port owner */
  122. #define EHCI_PS_PP (1 << 12) /* RW,RO port power */
  123. #define EHCI_PS_LS (3 << 10) /* RO line status */
  124. #define EHCI_PS_PR (1 << 8) /* RW port reset */
  125. #define EHCI_PS_SUSP (1 << 7) /* RW suspend */
  126. #define EHCI_PS_FPR (1 << 6) /* RW force port resume */
  127. #define EHCI_PS_OCC (1 << 5) /* RWC over current change */
  128. #define EHCI_PS_OCA (1 << 4) /* RO over current active */
  129. #define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
  130. #define EHCI_PS_PE (1 << 2) /* RW port enable */
  131. #define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
  132. #define EHCI_PS_CS (1 << 0) /* RO connect status */
  133. #define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
  134. #define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
  135. /*
  136. * Schedule Interface Space.
  137. *
  138. * IMPORTANT: Software must ensure that no interface data structure
  139. * reachable by the EHCI host controller spans a 4K page boundary!
  140. *
  141. * Periodic transfers (i.e. isochronous and interrupt transfers) are
  142. * not supported.
  143. */
  144. /* Queue Element Transfer Descriptor (qTD). */
  145. struct qTD {
  146. uint32_t qt_next;
  147. #define QT_NEXT_TERMINATE 1
  148. uint32_t qt_altnext;
  149. uint32_t qt_token;
  150. uint32_t qt_buffer[5];
  151. };
  152. /* Queue Head (QH). */
  153. struct QH {
  154. uint32_t qh_link;
  155. #define QH_LINK_TERMINATE 1
  156. #define QH_LINK_TYPE_ITD 0
  157. #define QH_LINK_TYPE_QH 2
  158. #define QH_LINK_TYPE_SITD 4
  159. #define QH_LINK_TYPE_FSTN 6
  160. uint32_t qh_endpt1;
  161. uint32_t qh_endpt2;
  162. uint32_t qh_curtd;
  163. struct qTD qh_overlay;
  164. /*
  165. * Add dummy fill value to make the size of this struct
  166. * aligned to 32 bytes
  167. */
  168. uint8_t fill[16];
  169. };
  170. /* Low level init functions */
  171. int ehci_hcd_init(void);
  172. int ehci_hcd_stop(void);
  173. #endif /* USB_EHCI_H */