mpc8260ads.c 17 KB

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  1. /*
  2. * (C) Copyright 2001-2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Modified during 2001 by
  6. * Advanced Communications Technologies (Australia) Pty. Ltd.
  7. * Howard Walker, Tuong Vu-Dinh
  8. *
  9. * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
  10. * Added support for the 16M dram simm on the 8260ads boards
  11. *
  12. * (C) Copyright 2003 Arabella Software Ltd.
  13. * Yuli Barcohen <yuli@arabellasw.com>
  14. * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
  15. *
  16. * See file CREDITS for list of people who contributed to this
  17. * project.
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License as
  21. * published by the Free Software Foundation; either version 2 of
  22. * the License, or (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32. * MA 02111-1307 USA
  33. */
  34. #include <common.h>
  35. #include <ioports.h>
  36. #include <mpc8260.h>
  37. #include <i2c.h>
  38. #include <spd.h>
  39. #include <miiphy.h>
  40. /*
  41. * I/O Port configuration table
  42. *
  43. * if conf is 1, then that port pin will be configured at boot time
  44. * according to the five values podr/pdir/ppar/psor/pdat for that entry
  45. */
  46. const iop_conf_t iop_conf_tab[4][32] = {
  47. /* Port A configuration */
  48. { /* conf ppar psor pdir podr pdat */
  49. /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
  50. /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
  51. /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
  52. /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
  53. /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
  54. /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
  55. /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
  56. /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
  57. /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
  58. /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
  59. /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
  60. /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
  61. /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
  62. /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
  63. /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
  64. /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
  65. /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
  66. /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
  67. /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
  68. /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
  69. /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
  70. /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
  71. /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
  72. /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
  73. /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
  74. /* PA6 */ { 1, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
  75. /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
  76. /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
  77. /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
  78. /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
  79. /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
  80. /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
  81. },
  82. /* Port B configuration */
  83. { /* conf ppar psor pdir podr pdat */
  84. /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
  85. /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
  86. /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
  87. /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
  88. /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
  89. /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
  90. /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
  91. /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
  92. /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
  93. /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
  94. /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
  95. /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
  96. /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
  97. /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
  98. /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
  99. /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
  100. /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
  101. /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
  102. /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
  103. /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
  104. /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  105. /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  106. /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  107. /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
  108. /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  109. /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  110. /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  111. /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
  112. /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  113. /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  114. /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  115. /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  116. },
  117. /* Port C */
  118. { /* conf ppar psor pdir podr pdat */
  119. /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
  120. /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
  121. /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
  122. /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
  123. /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
  124. /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
  125. /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
  126. /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
  127. /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
  128. /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
  129. /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
  130. /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
  131. /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
  132. /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
  133. /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
  134. /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
  135. /* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
  136. /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
  137. /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
  138. /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
  139. /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
  140. /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
  141. /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
  142. /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
  143. /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
  144. /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
  145. /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
  146. /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
  147. /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
  148. /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
  149. /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
  150. /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
  151. },
  152. /* Port D */
  153. { /* conf ppar psor pdir podr pdat */
  154. /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
  155. /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
  156. /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
  157. /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
  158. /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
  159. /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
  160. /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
  161. /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
  162. /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
  163. /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
  164. /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
  165. /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
  166. /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
  167. /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
  168. /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
  169. /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
  170. /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
  171. /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
  172. /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  173. /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  174. /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  175. /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  176. /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
  177. /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
  178. /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
  179. /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
  180. /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
  181. /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
  182. /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  183. /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  184. /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
  185. /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
  186. }
  187. };
  188. void reset_phy (void)
  189. {
  190. vu_long *bcsr = (vu_long *)CFG_BCSR;
  191. /* reset the FEC port */
  192. bcsr[1] &= ~FETH1_RST;
  193. udelay(2);
  194. bcsr[1] |= FETH1_RST;
  195. udelay(1000);
  196. #ifdef CONFIG_MII
  197. #if CONFIG_ADSTYPE == CFG_PQ2FADS
  198. /*
  199. * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
  200. * Enable autonegotiation.
  201. */
  202. miiphy_write(0, 16, 0x610);
  203. miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  204. #else
  205. /*
  206. * Ethernet PHY is configured (by means of configuration pins)
  207. * to work at 10Mb/s only. We reconfigure it using MII
  208. * to advertise all capabilities, including 100Mb/s, and
  209. * restart autonegotiation.
  210. */
  211. miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
  212. miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
  213. miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
  214. #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
  215. #endif /* CONFIG_MII */
  216. }
  217. int board_pre_init (void)
  218. {
  219. vu_long *bcsr = (vu_long *)CFG_BCSR;
  220. bcsr[1] = ~FETHIEN1 & ~RS232EN_1;
  221. return 0;
  222. }
  223. #define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
  224. long int initdram (int board_type)
  225. {
  226. volatile immap_t *immap = (immap_t *) CFG_IMMR;
  227. volatile memctl8260_t *memctl = &immap->im_memctl;
  228. volatile uchar *ramaddr, c = 0xff;
  229. long int msize;
  230. uint or;
  231. uint psdmr;
  232. uint psrt;
  233. int i;
  234. #ifndef CFG_RAMBOOT
  235. immap->im_siu_conf.sc_ppc_acr = 0x00000002;
  236. immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
  237. immap->im_siu_conf.sc_tescr1 = 0x00004000;
  238. memctl->memc_mptpr = CFG_MPTPR;
  239. #ifdef CFG_LSDRAM_BASE
  240. /* Init local bus SDRAM */
  241. memctl->memc_lsrt = CFG_LSRT;
  242. #if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
  243. memctl->memc_or3 = 0xFF803280;
  244. memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
  245. #else /* CS4 */
  246. memctl->memc_or4 = 0xFFC01480;
  247. memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
  248. #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
  249. memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
  250. ramaddr = (uchar *) CFG_LSDRAM_BASE;
  251. *ramaddr = c;
  252. memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
  253. for (i = 0; i < 8; i++) {
  254. *ramaddr = c;
  255. }
  256. memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
  257. *ramaddr = c;
  258. memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
  259. #endif /* CFG_LSDRAM_BASE */
  260. /* Init 60x bus SDRAM */
  261. #ifdef CONFIG_SPD_EEPROM
  262. {
  263. spd_eeprom_t spd;
  264. uint pbi, bsel, rowst, lsb, tmp;
  265. i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
  266. /* Bank-based interleaving is not supported for physical bank
  267. sizes greater than 128MB which is encoded as 0x20 in SPD
  268. */
  269. pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
  270. msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
  271. or = ~(msize - 1) << 20; /* SDAM */
  272. switch (spd.nbanks) { /* BPD */
  273. case 2:
  274. bsel = 1;
  275. break;
  276. case 4:
  277. bsel = 2;
  278. or |= 0x00002000;
  279. break;
  280. case 8:
  281. bsel = 3;
  282. or |= 0x00004000;
  283. break;
  284. }
  285. lsb = 3; /* For 64-bit port, lsb is 3 bits */
  286. if (pbi) { /* Bus partition depends on interleaving */
  287. rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
  288. or |= (rowst << 9); /* ROWST */
  289. } else {
  290. rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
  291. or |= ((rowst * 2 - 12) << 9); /* ROWST */
  292. }
  293. or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
  294. psdmr = (pbi << 31); /* PBI */
  295. /* Bus multiplexing parameters */
  296. tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
  297. psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
  298. psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
  299. tmp = (31 - lsb - 10) - tmp;
  300. /* Pin connected to SDA10 is (31 - lsb - 10).
  301. rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
  302. so (rowst + tmp) alternates with AP.
  303. */
  304. if (pbi) /* Table 10-7 */
  305. psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
  306. else
  307. psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
  308. /* SDRAM device-specific parameters */
  309. tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
  310. switch (tmp) { /* RFRC */
  311. case 1:
  312. case 2:
  313. psdmr |= (1 << 15);
  314. break;
  315. case 3:
  316. case 4:
  317. case 5:
  318. case 6:
  319. case 7:
  320. case 8:
  321. psdmr |= ((tmp - 2) << 15);
  322. break;
  323. default:
  324. psdmr |= (7 << 15);
  325. }
  326. psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
  327. psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
  328. /* BL=0 because for 64-bit SDRAM burst length must be 4 */
  329. /* LDOTOPRE ??? */
  330. for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
  331. tmp >>= 1;
  332. switch (i) { /* WRC */
  333. case 0:
  334. case 1:
  335. psdmr |= (1 << 4);
  336. break;
  337. case 2:
  338. case 3:
  339. psdmr |= (i << 4);
  340. break;
  341. }
  342. /* EAMUX=0 - no external address multiplexing */
  343. /* BUFCMD=0 - no external buffers */
  344. for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
  345. tmp >>= 1;
  346. psdmr |= i; /* CL */
  347. switch (spd.refresh & 0x7F) {
  348. case 1:
  349. tmp = 3900;
  350. break;
  351. case 2:
  352. tmp = 7800;
  353. break;
  354. case 3:
  355. tmp = 31300;
  356. break;
  357. case 4:
  358. tmp = 62500;
  359. break;
  360. case 5:
  361. tmp = 125000;
  362. break;
  363. default:
  364. tmp = 15625;
  365. }
  366. psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
  367. ((memctl->memc_mptpr >> 8) + 1)) - 1;
  368. #ifdef SPD_DEBUG
  369. printf ("\nDIMM type: %-18.18s\n", spd.mpart);
  370. printf ("SPD size: %d\n", spd.info_size);
  371. printf ("EEPROM size: %d\n", 1 << spd.chip_size);
  372. printf ("Memory type: %d\n", spd.mem_type);
  373. printf ("Row addr: %d\n", spd.nrow_addr);
  374. printf ("Column addr: %d\n", spd.ncol_addr);
  375. printf ("# of rows: %d\n", spd.nrows);
  376. printf ("Row density: %d\n", spd.row_dens);
  377. printf ("# of banks: %d\n", spd.nbanks);
  378. printf ("Data width: %d\n",
  379. 256 * spd.dataw_msb + spd.dataw_lsb);
  380. printf ("Chip width: %d\n", spd.primw);
  381. printf ("Refresh rate: %02X\n", spd.refresh);
  382. printf ("CAS latencies: %02X\n", spd.cas_lat);
  383. printf ("Write latencies: %02X\n", spd.write_lat);
  384. printf ("tRP: %d\n", spd.trp);
  385. printf ("tRCD: %d\n", spd.trcd);
  386. printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
  387. #endif /* SPD_DEBUG */
  388. }
  389. #else /* !CONFIG_SPD_EEPROM */
  390. #if CONFIG_ADSTYPE == CFG_PQ2FADS
  391. msize = 32;
  392. or = 0xFE002EC0;
  393. #else
  394. msize = 16;
  395. or = 0xFF000CA0;
  396. #endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
  397. psdmr = CFG_PSDMR;
  398. psrt = CFG_PSRT;
  399. #endif /* CONFIG_SPD_EEPROM */
  400. memctl->memc_psrt = psrt;
  401. memctl->memc_or2 = or;
  402. memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
  403. ramaddr = (uchar *) CFG_SDRAM_BASE;
  404. memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
  405. *ramaddr = c;
  406. memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
  407. for (i = 0; i < 8; i++)
  408. *ramaddr = c;
  409. memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
  410. *ramaddr = c;
  411. memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
  412. *ramaddr = c;
  413. #endif
  414. /* return total 60x bus SDRAM size */
  415. return (msize * 1024 * 1024);
  416. }
  417. int checkboard (void)
  418. {
  419. #if CONFIG_ADSTYPE == CFG_8260ADS
  420. puts ("Board: Motorola MPC8260ADS\n");
  421. #elif CONFIG_ADSTYPE == CFG_8266ADS
  422. puts ("Board: Motorola MPC8266ADS\n");
  423. #elif CONFIG_ADSTYPE == CFG_PQ2FADS
  424. puts ("Board: Motorola PQ2FADS-ZU\n");
  425. #else
  426. puts ("Board: unknown\n");
  427. #endif
  428. return 0;
  429. }