usb_ohci.c 44 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200.
  3. *
  4. * (C) Copyright 2003
  5. * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  6. *
  7. * Note: Much of this code has been derived from Linux 2.4
  8. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  9. * (C) Copyright 2000-2002 David Brownell
  10. *
  11. * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  12. * ebenard@eukrea.com - based on s3c24x0's driver
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. *
  32. */
  33. /*
  34. * IMPORTANT NOTES
  35. * 1 - you MUST define LITTLEENDIAN in the configuration file for the
  36. * board or this driver will NOT work!
  37. * 2 - this driver is intended for use with USB Mass Storage Devices
  38. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  39. * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  40. * to activate workaround for bug #41 or this driver will NOT work!
  41. */
  42. #include <common.h>
  43. /* #include <pci.h> no PCI on the S3C24X0 */
  44. #ifdef CONFIG_USB_OHCI
  45. #include <asm/arch/hardware.h>
  46. #include <malloc.h>
  47. #include <usb.h>
  48. #include "usb_ohci.h"
  49. #ifdef CONFIG_ARM920T
  50. # define OHCI_USE_NPS /* force NoPowerSwitching mode */
  51. #endif
  52. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  53. /* For initializing controller (mask in an HCFS mode too) */
  54. #define OHCI_CONTROL_INIT \
  55. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  56. #define readl(a) (*((vu_long *)(a)))
  57. #define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
  58. #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  59. #undef DEBUG
  60. #ifdef DEBUG
  61. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  62. #else
  63. #define dbg(format, arg...) do {} while(0)
  64. #endif /* DEBUG */
  65. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  66. #undef SHOW_INFO
  67. #ifdef SHOW_INFO
  68. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  69. #else
  70. #define info(format, arg...) do {} while(0)
  71. #endif
  72. #define m16_swap(x) swap_16(x)
  73. #define m32_swap(x) swap_32(x)
  74. /* global ohci_t */
  75. static ohci_t gohci;
  76. /* this must be aligned to a 256 byte boundary */
  77. struct ohci_hcca ghcca[1];
  78. /* a pointer to the aligned storage */
  79. struct ohci_hcca *phcca;
  80. /* this allocates EDs for all possible endpoints */
  81. struct ohci_device ohci_dev;
  82. /* urb_priv */
  83. urb_priv_t urb_priv;
  84. /* RHSC flag */
  85. int got_rhsc;
  86. /* device which was disconnected */
  87. struct usb_device *devgone;
  88. /*-------------------------------------------------------------------------*/
  89. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  90. * The erratum (#4) description is incorrect. AMD's workaround waits
  91. * till some bits (mostly reserved) are clear; ok for all revs.
  92. */
  93. #define OHCI_QUIRK_AMD756 0xabcd
  94. #define read_roothub(hc, register, mask) ({ \
  95. u32 temp = readl (&hc->regs->roothub.register); \
  96. if (hc->flags & OHCI_QUIRK_AMD756) \
  97. while (temp & mask) \
  98. temp = readl (&hc->regs->roothub.register); \
  99. temp; })
  100. static u32 roothub_a (struct ohci *hc)
  101. { return read_roothub (hc, a, 0xfc0fe000); }
  102. static inline u32 roothub_b (struct ohci *hc)
  103. { return readl (&hc->regs->roothub.b); }
  104. static inline u32 roothub_status (struct ohci *hc)
  105. { return readl (&hc->regs->roothub.status); }
  106. static u32 roothub_portstatus (struct ohci *hc, int i)
  107. { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
  108. /* forward declaration */
  109. static int hc_interrupt (void);
  110. static void
  111. td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
  112. int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
  113. /*-------------------------------------------------------------------------*
  114. * URB support functions
  115. *-------------------------------------------------------------------------*/
  116. /* free HCD-private data associated with this URB */
  117. static void urb_free_priv (urb_priv_t * urb)
  118. {
  119. int i;
  120. int last;
  121. struct td * td;
  122. last = urb->length - 1;
  123. if (last >= 0) {
  124. for (i = 0; i <= last; i++) {
  125. td = urb->td[i];
  126. if (td) {
  127. td->usb_dev = NULL;
  128. urb->td[i] = NULL;
  129. }
  130. }
  131. }
  132. }
  133. /*-------------------------------------------------------------------------*/
  134. #ifdef DEBUG
  135. static int sohci_get_current_frame_number (struct usb_device * dev);
  136. /* debug| print the main components of an URB
  137. * small: 0) header + data packets 1) just header */
  138. static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
  139. int transfer_len, struct devrequest * setup, char * str, int small)
  140. {
  141. urb_priv_t * purb = &urb_priv;
  142. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  143. str,
  144. sohci_get_current_frame_number (dev),
  145. usb_pipedevice (pipe),
  146. usb_pipeendpoint (pipe),
  147. usb_pipeout (pipe)? 'O': 'I',
  148. usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
  149. (usb_pipecontrol (pipe)? "CTRL": "BULK"),
  150. purb->actual_length,
  151. transfer_len, dev->status);
  152. #ifdef OHCI_VERBOSE_DEBUG
  153. if (!small) {
  154. int i, len;
  155. if (usb_pipecontrol (pipe)) {
  156. printf (__FILE__ ": cmd(8):");
  157. for (i = 0; i < 8 ; i++)
  158. printf (" %02x", ((__u8 *) setup) [i]);
  159. printf ("\n");
  160. }
  161. if (transfer_len > 0 && buffer) {
  162. printf (__FILE__ ": data(%d/%d):",
  163. purb->actual_length,
  164. transfer_len);
  165. len = usb_pipeout (pipe)?
  166. transfer_len: purb->actual_length;
  167. for (i = 0; i < 16 && i < len; i++)
  168. printf (" %02x", ((__u8 *) buffer) [i]);
  169. printf ("%s\n", i < len? "...": "");
  170. }
  171. }
  172. #endif
  173. }
  174. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  175. void ep_print_int_eds (ohci_t *ohci, char * str) {
  176. int i, j;
  177. __u32 * ed_p;
  178. for (i= 0; i < 32; i++) {
  179. j = 5;
  180. ed_p = &(ohci->hcca->int_table [i]);
  181. if (*ed_p == 0)
  182. continue;
  183. printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  184. while (*ed_p != 0 && j--) {
  185. ed_t *ed = (ed_t *)m32_swap(ed_p);
  186. printf (" ed: %4x;", ed->hwINFO);
  187. ed_p = &ed->hwNextED;
  188. }
  189. printf ("\n");
  190. }
  191. }
  192. static void ohci_dump_intr_mask (char *label, __u32 mask)
  193. {
  194. dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  195. label,
  196. mask,
  197. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  198. (mask & OHCI_INTR_OC) ? " OC" : "",
  199. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  200. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  201. (mask & OHCI_INTR_UE) ? " UE" : "",
  202. (mask & OHCI_INTR_RD) ? " RD" : "",
  203. (mask & OHCI_INTR_SF) ? " SF" : "",
  204. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  205. (mask & OHCI_INTR_SO) ? " SO" : ""
  206. );
  207. }
  208. static void maybe_print_eds (char *label, __u32 value)
  209. {
  210. ed_t *edp = (ed_t *)value;
  211. if (value) {
  212. dbg ("%s %08x", label, value);
  213. dbg ("%08x", edp->hwINFO);
  214. dbg ("%08x", edp->hwTailP);
  215. dbg ("%08x", edp->hwHeadP);
  216. dbg ("%08x", edp->hwNextED);
  217. }
  218. }
  219. static char * hcfs2string (int state)
  220. {
  221. switch (state) {
  222. case OHCI_USB_RESET: return "reset";
  223. case OHCI_USB_RESUME: return "resume";
  224. case OHCI_USB_OPER: return "operational";
  225. case OHCI_USB_SUSPEND: return "suspend";
  226. }
  227. return "?";
  228. }
  229. /* dump control and status registers */
  230. static void ohci_dump_status (ohci_t *controller)
  231. {
  232. struct ohci_regs *regs = controller->regs;
  233. __u32 temp;
  234. temp = readl (&regs->revision) & 0xff;
  235. if (temp != 0x10)
  236. dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
  237. temp = readl (&regs->control);
  238. dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  239. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  240. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  241. (temp & OHCI_CTRL_IR) ? " IR" : "",
  242. hcfs2string (temp & OHCI_CTRL_HCFS),
  243. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  244. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  245. (temp & OHCI_CTRL_IE) ? " IE" : "",
  246. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  247. temp & OHCI_CTRL_CBSR
  248. );
  249. temp = readl (&regs->cmdstatus);
  250. dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  251. (temp & OHCI_SOC) >> 16,
  252. (temp & OHCI_OCR) ? " OCR" : "",
  253. (temp & OHCI_BLF) ? " BLF" : "",
  254. (temp & OHCI_CLF) ? " CLF" : "",
  255. (temp & OHCI_HCR) ? " HCR" : ""
  256. );
  257. ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
  258. ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
  259. maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
  260. maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
  261. maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
  262. maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
  263. maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
  264. maybe_print_eds ("donehead", readl (&regs->donehead));
  265. }
  266. static void ohci_dump_roothub (ohci_t *controller, int verbose)
  267. {
  268. __u32 temp, ndp, i;
  269. temp = roothub_a (controller);
  270. ndp = (temp & RH_A_NDP);
  271. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  272. ndp = (ndp == 2) ? 1:0;
  273. #endif
  274. if (verbose) {
  275. dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  276. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  277. (temp & RH_A_NOCP) ? " NOCP" : "",
  278. (temp & RH_A_OCPM) ? " OCPM" : "",
  279. (temp & RH_A_DT) ? " DT" : "",
  280. (temp & RH_A_NPS) ? " NPS" : "",
  281. (temp & RH_A_PSM) ? " PSM" : "",
  282. ndp
  283. );
  284. temp = roothub_b (controller);
  285. dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
  286. temp,
  287. (temp & RH_B_PPCM) >> 16,
  288. (temp & RH_B_DR)
  289. );
  290. temp = roothub_status (controller);
  291. dbg ("roothub.status: %08x%s%s%s%s%s%s",
  292. temp,
  293. (temp & RH_HS_CRWE) ? " CRWE" : "",
  294. (temp & RH_HS_OCIC) ? " OCIC" : "",
  295. (temp & RH_HS_LPSC) ? " LPSC" : "",
  296. (temp & RH_HS_DRWE) ? " DRWE" : "",
  297. (temp & RH_HS_OCI) ? " OCI" : "",
  298. (temp & RH_HS_LPS) ? " LPS" : ""
  299. );
  300. }
  301. for (i = 0; i < ndp; i++) {
  302. temp = roothub_portstatus (controller, i);
  303. dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  304. i,
  305. temp,
  306. (temp & RH_PS_PRSC) ? " PRSC" : "",
  307. (temp & RH_PS_OCIC) ? " OCIC" : "",
  308. (temp & RH_PS_PSSC) ? " PSSC" : "",
  309. (temp & RH_PS_PESC) ? " PESC" : "",
  310. (temp & RH_PS_CSC) ? " CSC" : "",
  311. (temp & RH_PS_LSDA) ? " LSDA" : "",
  312. (temp & RH_PS_PPS) ? " PPS" : "",
  313. (temp & RH_PS_PRS) ? " PRS" : "",
  314. (temp & RH_PS_POCI) ? " POCI" : "",
  315. (temp & RH_PS_PSS) ? " PSS" : "",
  316. (temp & RH_PS_PES) ? " PES" : "",
  317. (temp & RH_PS_CCS) ? " CCS" : ""
  318. );
  319. }
  320. }
  321. static void ohci_dump (ohci_t *controller, int verbose)
  322. {
  323. dbg ("OHCI controller usb-%s state", controller->slot_name);
  324. /* dumps some of the state we know about */
  325. ohci_dump_status (controller);
  326. if (verbose)
  327. ep_print_int_eds (controller, "hcca");
  328. dbg ("hcca frame #%04x", controller->hcca->frame_no);
  329. ohci_dump_roothub (controller, 1);
  330. }
  331. #endif /* DEBUG */
  332. /*-------------------------------------------------------------------------*
  333. * Interface functions (URB)
  334. *-------------------------------------------------------------------------*/
  335. /* get a transfer request */
  336. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  337. int transfer_len, struct devrequest *setup, int interval)
  338. {
  339. ohci_t *ohci;
  340. ed_t * ed;
  341. urb_priv_t *purb_priv;
  342. int i, size = 0;
  343. ohci = &gohci;
  344. /* when controller's hung, permit only roothub cleanup attempts
  345. * such as powering down ports */
  346. if (ohci->disabled) {
  347. err("sohci_submit_job: EPIPE");
  348. return -1;
  349. }
  350. /* every endpoint has a ed, locate and fill it */
  351. if (!(ed = ep_add_ed (dev, pipe))) {
  352. err("sohci_submit_job: ENOMEM");
  353. return -1;
  354. }
  355. /* for the private part of the URB we need the number of TDs (size) */
  356. switch (usb_pipetype (pipe)) {
  357. case PIPE_BULK: /* one TD for every 4096 Byte */
  358. size = (transfer_len - 1) / 4096 + 1;
  359. break;
  360. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  361. size = (transfer_len == 0)? 2:
  362. (transfer_len - 1) / 4096 + 3;
  363. break;
  364. }
  365. if (size >= (N_URB_TD - 1)) {
  366. err("need %d TDs, only have %d", size, N_URB_TD);
  367. return -1;
  368. }
  369. purb_priv = &urb_priv;
  370. purb_priv->pipe = pipe;
  371. /* fill the private part of the URB */
  372. purb_priv->length = size;
  373. purb_priv->ed = ed;
  374. purb_priv->actual_length = 0;
  375. /* allocate the TDs */
  376. /* note that td[0] was allocated in ep_add_ed */
  377. for (i = 0; i < size; i++) {
  378. purb_priv->td[i] = td_alloc (dev);
  379. if (!purb_priv->td[i]) {
  380. purb_priv->length = i;
  381. urb_free_priv (purb_priv);
  382. err("sohci_submit_job: ENOMEM");
  383. return -1;
  384. }
  385. }
  386. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  387. urb_free_priv (purb_priv);
  388. err("sohci_submit_job: EINVAL");
  389. return -1;
  390. }
  391. /* link the ed into a chain if is not already */
  392. if (ed->state != ED_OPER)
  393. ep_link (ohci, ed);
  394. /* fill the TDs and link it to the ed */
  395. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
  396. return 0;
  397. }
  398. /*-------------------------------------------------------------------------*/
  399. #ifdef DEBUG
  400. /* tell us the current USB frame number */
  401. static int sohci_get_current_frame_number (struct usb_device *usb_dev)
  402. {
  403. ohci_t *ohci = &gohci;
  404. return m16_swap (ohci->hcca->frame_no);
  405. }
  406. #endif
  407. /*-------------------------------------------------------------------------*
  408. * ED handling functions
  409. *-------------------------------------------------------------------------*/
  410. /* link an ed into one of the HC chains */
  411. static int ep_link (ohci_t *ohci, ed_t *edi)
  412. {
  413. volatile ed_t *ed = edi;
  414. ed->state = ED_OPER;
  415. switch (ed->type) {
  416. case PIPE_CONTROL:
  417. ed->hwNextED = 0;
  418. if (ohci->ed_controltail == NULL) {
  419. writel (ed, &ohci->regs->ed_controlhead);
  420. } else {
  421. ohci->ed_controltail->hwNextED = m32_swap (ed);
  422. }
  423. ed->ed_prev = ohci->ed_controltail;
  424. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  425. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  426. ohci->hc_control |= OHCI_CTRL_CLE;
  427. writel (ohci->hc_control, &ohci->regs->control);
  428. }
  429. ohci->ed_controltail = edi;
  430. break;
  431. case PIPE_BULK:
  432. ed->hwNextED = 0;
  433. if (ohci->ed_bulktail == NULL) {
  434. writel (ed, &ohci->regs->ed_bulkhead);
  435. } else {
  436. ohci->ed_bulktail->hwNextED = m32_swap (ed);
  437. }
  438. ed->ed_prev = ohci->ed_bulktail;
  439. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  440. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  441. ohci->hc_control |= OHCI_CTRL_BLE;
  442. writel (ohci->hc_control, &ohci->regs->control);
  443. }
  444. ohci->ed_bulktail = edi;
  445. break;
  446. }
  447. return 0;
  448. }
  449. /*-------------------------------------------------------------------------*/
  450. /* unlink an ed from one of the HC chains.
  451. * just the link to the ed is unlinked.
  452. * the link from the ed still points to another operational ed or 0
  453. * so the HC can eventually finish the processing of the unlinked ed */
  454. static int ep_unlink (ohci_t *ohci, ed_t *ed)
  455. {
  456. ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
  457. switch (ed->type) {
  458. case PIPE_CONTROL:
  459. if (ed->ed_prev == NULL) {
  460. if (!ed->hwNextED) {
  461. ohci->hc_control &= ~OHCI_CTRL_CLE;
  462. writel (ohci->hc_control, &ohci->regs->control);
  463. }
  464. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
  465. } else {
  466. ed->ed_prev->hwNextED = ed->hwNextED;
  467. }
  468. if (ohci->ed_controltail == ed) {
  469. ohci->ed_controltail = ed->ed_prev;
  470. } else {
  471. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  472. }
  473. break;
  474. case PIPE_BULK:
  475. if (ed->ed_prev == NULL) {
  476. if (!ed->hwNextED) {
  477. ohci->hc_control &= ~OHCI_CTRL_BLE;
  478. writel (ohci->hc_control, &ohci->regs->control);
  479. }
  480. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
  481. } else {
  482. ed->ed_prev->hwNextED = ed->hwNextED;
  483. }
  484. if (ohci->ed_bulktail == ed) {
  485. ohci->ed_bulktail = ed->ed_prev;
  486. } else {
  487. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  488. }
  489. break;
  490. }
  491. ed->state = ED_UNLINK;
  492. return 0;
  493. }
  494. /*-------------------------------------------------------------------------*/
  495. /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
  496. * but the USB stack is a little bit stateless so we do it at every transaction
  497. * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
  498. * in all other cases the state is left unchanged
  499. * the ed info fields are setted anyway even though most of them should not change */
  500. static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
  501. {
  502. td_t *td;
  503. ed_t *ed_ret;
  504. volatile ed_t *ed;
  505. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
  506. (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
  507. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  508. err("ep_add_ed: pending delete");
  509. /* pending delete request */
  510. return NULL;
  511. }
  512. if (ed->state == ED_NEW) {
  513. ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
  514. /* dummy td; end of td list for ed */
  515. td = td_alloc (usb_dev);
  516. ed->hwTailP = m32_swap (td);
  517. ed->hwHeadP = ed->hwTailP;
  518. ed->state = ED_UNLINK;
  519. ed->type = usb_pipetype (pipe);
  520. ohci_dev.ed_cnt++;
  521. }
  522. ed->hwINFO = m32_swap (usb_pipedevice (pipe)
  523. | usb_pipeendpoint (pipe) << 7
  524. | (usb_pipeisoc (pipe)? 0x8000: 0)
  525. | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
  526. | usb_pipeslow (pipe) << 13
  527. | usb_maxpacket (usb_dev, pipe) << 16);
  528. return ed_ret;
  529. }
  530. /*-------------------------------------------------------------------------*
  531. * TD handling functions
  532. *-------------------------------------------------------------------------*/
  533. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  534. static void td_fill (ohci_t *ohci, unsigned int info,
  535. void *data, int len,
  536. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  537. {
  538. volatile td_t *td, *td_pt;
  539. #ifdef OHCI_FILL_TRACE
  540. int i;
  541. #endif
  542. if (index > urb_priv->length) {
  543. err("index > length");
  544. return;
  545. }
  546. /* use this td as the next dummy */
  547. td_pt = urb_priv->td [index];
  548. td_pt->hwNextTD = 0;
  549. /* fill the old dummy TD */
  550. td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
  551. td->ed = urb_priv->ed;
  552. td->next_dl_td = NULL;
  553. td->index = index;
  554. td->data = (__u32)data;
  555. #ifdef OHCI_FILL_TRACE
  556. if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
  557. for (i = 0; i < len; i++)
  558. printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
  559. printf("\n");
  560. }
  561. #endif
  562. if (!len)
  563. data = 0;
  564. td->hwINFO = m32_swap (info);
  565. td->hwCBP = m32_swap (data);
  566. if (data)
  567. td->hwBE = m32_swap (data + len - 1);
  568. else
  569. td->hwBE = 0;
  570. td->hwNextTD = m32_swap (td_pt);
  571. td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
  572. /* append to queue */
  573. td->ed->hwTailP = td->hwNextTD;
  574. }
  575. /*-------------------------------------------------------------------------*/
  576. /* prepare all TDs of a transfer */
  577. static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
  578. int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
  579. {
  580. ohci_t *ohci = &gohci;
  581. int data_len = transfer_len;
  582. void *data;
  583. int cnt = 0;
  584. __u32 info = 0;
  585. unsigned int toggle = 0;
  586. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
  587. if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  588. toggle = TD_T_TOGGLE;
  589. } else {
  590. toggle = TD_T_DATA0;
  591. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
  592. }
  593. urb->td_cnt = 0;
  594. if (data_len)
  595. data = buffer;
  596. else
  597. data = 0;
  598. switch (usb_pipetype (pipe)) {
  599. case PIPE_BULK:
  600. info = usb_pipeout (pipe)?
  601. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  602. while(data_len > 4096) {
  603. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
  604. data += 4096; data_len -= 4096; cnt++;
  605. }
  606. info = usb_pipeout (pipe)?
  607. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  608. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
  609. cnt++;
  610. if (!ohci->sleeping)
  611. writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  612. break;
  613. case PIPE_CONTROL:
  614. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  615. td_fill (ohci, info, setup, 8, dev, cnt++, urb);
  616. if (data_len > 0) {
  617. info = usb_pipeout (pipe)?
  618. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  619. /* NOTE: mishandles transfers >8K, some >4K */
  620. td_fill (ohci, info, data, data_len, dev, cnt++, urb);
  621. }
  622. info = usb_pipeout (pipe)?
  623. TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
  624. td_fill (ohci, info, data, 0, dev, cnt++, urb);
  625. if (!ohci->sleeping)
  626. writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  627. break;
  628. }
  629. if (urb->length != cnt)
  630. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  631. }
  632. /*-------------------------------------------------------------------------*
  633. * Done List handling functions
  634. *-------------------------------------------------------------------------*/
  635. /* calculate the transfer length and update the urb */
  636. static void dl_transfer_length(td_t * td)
  637. {
  638. __u32 tdINFO, tdBE, tdCBP;
  639. urb_priv_t *lurb_priv = &urb_priv;
  640. tdINFO = m32_swap (td->hwINFO);
  641. tdBE = m32_swap (td->hwBE);
  642. tdCBP = m32_swap (td->hwCBP);
  643. if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
  644. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  645. if (tdBE != 0) {
  646. if (td->hwCBP == 0)
  647. lurb_priv->actual_length += tdBE - td->data + 1;
  648. else
  649. lurb_priv->actual_length += tdCBP - td->data;
  650. }
  651. }
  652. }
  653. /*-------------------------------------------------------------------------*/
  654. /* replies to the request have to be on a FIFO basis so
  655. * we reverse the reversed done-list */
  656. static td_t * dl_reverse_done_list (ohci_t *ohci)
  657. {
  658. __u32 td_list_hc;
  659. td_t *td_rev = NULL;
  660. td_t *td_list = NULL;
  661. urb_priv_t *lurb_priv = NULL;
  662. td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
  663. ohci->hcca->done_head = 0;
  664. while (td_list_hc) {
  665. td_list = (td_t *)td_list_hc;
  666. if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
  667. lurb_priv = &urb_priv;
  668. dbg(" USB-error/status: %x : %p",
  669. TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
  670. if (td_list->ed->hwHeadP & m32_swap (0x1)) {
  671. if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
  672. td_list->ed->hwHeadP =
  673. (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
  674. (td_list->ed->hwHeadP & m32_swap (0x2));
  675. lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
  676. } else
  677. td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
  678. }
  679. }
  680. td_list->next_dl_td = td_rev;
  681. td_rev = td_list;
  682. td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
  683. }
  684. return td_list;
  685. }
  686. /*-------------------------------------------------------------------------*/
  687. /* td done list */
  688. static int dl_done_list (ohci_t *ohci, td_t *td_list)
  689. {
  690. td_t *td_list_next = NULL;
  691. ed_t *ed;
  692. int cc = 0;
  693. int stat = 0;
  694. /* urb_t *urb; */
  695. urb_priv_t *lurb_priv;
  696. __u32 tdINFO, edHeadP, edTailP;
  697. while (td_list) {
  698. td_list_next = td_list->next_dl_td;
  699. lurb_priv = &urb_priv;
  700. tdINFO = m32_swap (td_list->hwINFO);
  701. ed = td_list->ed;
  702. dl_transfer_length(td_list);
  703. /* error code of transfer */
  704. cc = TD_CC_GET (tdINFO);
  705. if (cc != 0) {
  706. dbg("ConditionCode %#x", cc);
  707. stat = cc_to_error[cc];
  708. }
  709. if (ed->state != ED_NEW) {
  710. edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
  711. edTailP = m32_swap (ed->hwTailP);
  712. /* unlink eds if they are not busy */
  713. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  714. ep_unlink (ohci, ed);
  715. }
  716. td_list = td_list_next;
  717. }
  718. return stat;
  719. }
  720. /*-------------------------------------------------------------------------*
  721. * Virtual Root Hub
  722. *-------------------------------------------------------------------------*/
  723. /* Device descriptor */
  724. static __u8 root_hub_dev_des[] =
  725. {
  726. 0x12, /* __u8 bLength; */
  727. 0x01, /* __u8 bDescriptorType; Device */
  728. 0x10, /* __u16 bcdUSB; v1.1 */
  729. 0x01,
  730. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  731. 0x00, /* __u8 bDeviceSubClass; */
  732. 0x00, /* __u8 bDeviceProtocol; */
  733. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  734. 0x00, /* __u16 idVendor; */
  735. 0x00,
  736. 0x00, /* __u16 idProduct; */
  737. 0x00,
  738. 0x00, /* __u16 bcdDevice; */
  739. 0x00,
  740. 0x00, /* __u8 iManufacturer; */
  741. 0x01, /* __u8 iProduct; */
  742. 0x00, /* __u8 iSerialNumber; */
  743. 0x01 /* __u8 bNumConfigurations; */
  744. };
  745. /* Configuration descriptor */
  746. static __u8 root_hub_config_des[] =
  747. {
  748. 0x09, /* __u8 bLength; */
  749. 0x02, /* __u8 bDescriptorType; Configuration */
  750. 0x19, /* __u16 wTotalLength; */
  751. 0x00,
  752. 0x01, /* __u8 bNumInterfaces; */
  753. 0x01, /* __u8 bConfigurationValue; */
  754. 0x00, /* __u8 iConfiguration; */
  755. 0x40, /* __u8 bmAttributes;
  756. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  757. 0x00, /* __u8 MaxPower; */
  758. /* interface */
  759. 0x09, /* __u8 if_bLength; */
  760. 0x04, /* __u8 if_bDescriptorType; Interface */
  761. 0x00, /* __u8 if_bInterfaceNumber; */
  762. 0x00, /* __u8 if_bAlternateSetting; */
  763. 0x01, /* __u8 if_bNumEndpoints; */
  764. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  765. 0x00, /* __u8 if_bInterfaceSubClass; */
  766. 0x00, /* __u8 if_bInterfaceProtocol; */
  767. 0x00, /* __u8 if_iInterface; */
  768. /* endpoint */
  769. 0x07, /* __u8 ep_bLength; */
  770. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  771. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  772. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  773. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  774. 0x00,
  775. 0xff /* __u8 ep_bInterval; 255 ms */
  776. };
  777. static unsigned char root_hub_str_index0[] =
  778. {
  779. 0x04, /* __u8 bLength; */
  780. 0x03, /* __u8 bDescriptorType; String-descriptor */
  781. 0x09, /* __u8 lang ID */
  782. 0x04, /* __u8 lang ID */
  783. };
  784. static unsigned char root_hub_str_index1[] =
  785. {
  786. 28, /* __u8 bLength; */
  787. 0x03, /* __u8 bDescriptorType; String-descriptor */
  788. 'O', /* __u8 Unicode */
  789. 0, /* __u8 Unicode */
  790. 'H', /* __u8 Unicode */
  791. 0, /* __u8 Unicode */
  792. 'C', /* __u8 Unicode */
  793. 0, /* __u8 Unicode */
  794. 'I', /* __u8 Unicode */
  795. 0, /* __u8 Unicode */
  796. ' ', /* __u8 Unicode */
  797. 0, /* __u8 Unicode */
  798. 'R', /* __u8 Unicode */
  799. 0, /* __u8 Unicode */
  800. 'o', /* __u8 Unicode */
  801. 0, /* __u8 Unicode */
  802. 'o', /* __u8 Unicode */
  803. 0, /* __u8 Unicode */
  804. 't', /* __u8 Unicode */
  805. 0, /* __u8 Unicode */
  806. ' ', /* __u8 Unicode */
  807. 0, /* __u8 Unicode */
  808. 'H', /* __u8 Unicode */
  809. 0, /* __u8 Unicode */
  810. 'u', /* __u8 Unicode */
  811. 0, /* __u8 Unicode */
  812. 'b', /* __u8 Unicode */
  813. 0, /* __u8 Unicode */
  814. };
  815. /* Hub class-specific descriptor is constructed dynamically */
  816. /*-------------------------------------------------------------------------*/
  817. #define OK(x) len = (x); break
  818. #ifdef DEBUG
  819. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  820. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  821. #else
  822. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  823. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  824. #endif
  825. #define RD_RH_STAT roothub_status(&gohci)
  826. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  827. /* request to virtual root hub */
  828. int rh_check_port_status(ohci_t *controller)
  829. {
  830. __u32 temp, ndp, i;
  831. int res;
  832. res = -1;
  833. temp = roothub_a (controller);
  834. ndp = (temp & RH_A_NDP);
  835. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  836. ndp = (ndp == 2) ? 1:0;
  837. #endif
  838. for (i = 0; i < ndp; i++) {
  839. temp = roothub_portstatus (controller, i);
  840. /* check for a device disconnect */
  841. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  842. (RH_PS_PESC | RH_PS_CSC)) &&
  843. ((temp & RH_PS_CCS) == 0)) {
  844. res = i;
  845. break;
  846. }
  847. }
  848. return res;
  849. }
  850. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  851. void *buffer, int transfer_len, struct devrequest *cmd)
  852. {
  853. void * data = buffer;
  854. int leni = transfer_len;
  855. int len = 0;
  856. int stat = 0;
  857. __u32 datab[4];
  858. __u8 *data_buf = (__u8 *)datab;
  859. __u16 bmRType_bReq;
  860. __u16 wValue;
  861. __u16 wIndex;
  862. __u16 wLength;
  863. #ifdef DEBUG
  864. urb_priv.actual_length = 0;
  865. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
  866. #else
  867. wait_ms(1);
  868. #endif
  869. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  870. info("Root-Hub submit IRQ: NOT implemented");
  871. return 0;
  872. }
  873. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  874. wValue = m16_swap (cmd->value);
  875. wIndex = m16_swap (cmd->index);
  876. wLength = m16_swap (cmd->length);
  877. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  878. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  879. switch (bmRType_bReq) {
  880. /* Request Destination:
  881. without flags: Device,
  882. RH_INTERFACE: interface,
  883. RH_ENDPOINT: endpoint,
  884. RH_CLASS means HUB here,
  885. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  886. */
  887. case RH_GET_STATUS:
  888. *(__u16 *) data_buf = m16_swap (1); OK (2);
  889. case RH_GET_STATUS | RH_INTERFACE:
  890. *(__u16 *) data_buf = m16_swap (0); OK (2);
  891. case RH_GET_STATUS | RH_ENDPOINT:
  892. *(__u16 *) data_buf = m16_swap (0); OK (2);
  893. case RH_GET_STATUS | RH_CLASS:
  894. *(__u32 *) data_buf = m32_swap (
  895. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  896. OK (4);
  897. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  898. *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
  899. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  900. switch (wValue) {
  901. case (RH_ENDPOINT_STALL): OK (0);
  902. }
  903. break;
  904. case RH_CLEAR_FEATURE | RH_CLASS:
  905. switch (wValue) {
  906. case RH_C_HUB_LOCAL_POWER:
  907. OK(0);
  908. case (RH_C_HUB_OVER_CURRENT):
  909. WR_RH_STAT(RH_HS_OCIC); OK (0);
  910. }
  911. break;
  912. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  913. switch (wValue) {
  914. case (RH_PORT_ENABLE):
  915. WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
  916. case (RH_PORT_SUSPEND):
  917. WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
  918. case (RH_PORT_POWER):
  919. WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
  920. case (RH_C_PORT_CONNECTION):
  921. WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
  922. case (RH_C_PORT_ENABLE):
  923. WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
  924. case (RH_C_PORT_SUSPEND):
  925. WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
  926. case (RH_C_PORT_OVER_CURRENT):
  927. WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
  928. case (RH_C_PORT_RESET):
  929. WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
  930. }
  931. break;
  932. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  933. switch (wValue) {
  934. case (RH_PORT_SUSPEND):
  935. WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
  936. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  937. if (RD_RH_PORTSTAT & RH_PS_CCS)
  938. WR_RH_PORTSTAT (RH_PS_PRS);
  939. OK (0);
  940. case (RH_PORT_POWER):
  941. WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
  942. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  943. if (RD_RH_PORTSTAT & RH_PS_CCS)
  944. WR_RH_PORTSTAT (RH_PS_PES );
  945. OK (0);
  946. }
  947. break;
  948. case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
  949. case RH_GET_DESCRIPTOR:
  950. switch ((wValue & 0xff00) >> 8) {
  951. case (0x01): /* device descriptor */
  952. len = min_t(unsigned int,
  953. leni,
  954. min_t(unsigned int,
  955. sizeof (root_hub_dev_des),
  956. wLength));
  957. data_buf = root_hub_dev_des; OK(len);
  958. case (0x02): /* configuration descriptor */
  959. len = min_t(unsigned int,
  960. leni,
  961. min_t(unsigned int,
  962. sizeof (root_hub_config_des),
  963. wLength));
  964. data_buf = root_hub_config_des; OK(len);
  965. case (0x03): /* string descriptors */
  966. if(wValue==0x0300) {
  967. len = min_t(unsigned int,
  968. leni,
  969. min_t(unsigned int,
  970. sizeof (root_hub_str_index0),
  971. wLength));
  972. data_buf = root_hub_str_index0;
  973. OK(len);
  974. }
  975. if(wValue==0x0301) {
  976. len = min_t(unsigned int,
  977. leni,
  978. min_t(unsigned int,
  979. sizeof (root_hub_str_index1),
  980. wLength));
  981. data_buf = root_hub_str_index1;
  982. OK(len);
  983. }
  984. default:
  985. stat = USB_ST_STALLED;
  986. }
  987. break;
  988. case RH_GET_DESCRIPTOR | RH_CLASS:
  989. {
  990. __u32 temp = roothub_a (&gohci);
  991. data_buf [0] = 9; /* min length; */
  992. data_buf [1] = 0x29;
  993. data_buf [2] = temp & RH_A_NDP;
  994. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  995. data_buf [2] = (data_buf [2] == 2) ? 1:0;
  996. #endif
  997. data_buf [3] = 0;
  998. if (temp & RH_A_PSM) /* per-port power switching? */
  999. data_buf [3] |= 0x1;
  1000. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  1001. data_buf [3] |= 0x10;
  1002. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  1003. data_buf [3] |= 0x8;
  1004. /* corresponds to data_buf[4-7] */
  1005. datab [1] = 0;
  1006. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  1007. temp = roothub_b (&gohci);
  1008. data_buf [7] = temp & RH_B_DR;
  1009. if (data_buf [2] < 7) {
  1010. data_buf [8] = 0xff;
  1011. } else {
  1012. data_buf [0] += 2;
  1013. data_buf [8] = (temp & RH_B_DR) >> 8;
  1014. data_buf [10] = data_buf [9] = 0xff;
  1015. }
  1016. len = min_t(unsigned int, leni,
  1017. min_t(unsigned int, data_buf [0], wLength));
  1018. OK (len);
  1019. }
  1020. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
  1021. case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
  1022. default:
  1023. dbg ("unsupported root hub command");
  1024. stat = USB_ST_STALLED;
  1025. }
  1026. #ifdef DEBUG
  1027. ohci_dump_roothub (&gohci, 1);
  1028. #else
  1029. wait_ms(1);
  1030. #endif
  1031. len = min_t(int, len, leni);
  1032. if (data != data_buf)
  1033. memcpy (data, data_buf, len);
  1034. dev->act_len = len;
  1035. dev->status = stat;
  1036. #ifdef DEBUG
  1037. if (transfer_len)
  1038. urb_priv.actual_length = transfer_len;
  1039. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1040. #else
  1041. wait_ms(1);
  1042. #endif
  1043. return stat;
  1044. }
  1045. /*-------------------------------------------------------------------------*/
  1046. /* common code for handling submit messages - used for all but root hub */
  1047. /* accesses. */
  1048. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1049. int transfer_len, struct devrequest *setup, int interval)
  1050. {
  1051. int stat = 0;
  1052. int maxsize = usb_maxpacket(dev, pipe);
  1053. int timeout;
  1054. /* device pulled? Shortcut the action. */
  1055. if (devgone == dev) {
  1056. dev->status = USB_ST_CRC_ERR;
  1057. return 0;
  1058. }
  1059. #ifdef DEBUG
  1060. urb_priv.actual_length = 0;
  1061. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1062. #else
  1063. wait_ms(1);
  1064. #endif
  1065. if (!maxsize) {
  1066. err("submit_common_message: pipesize for pipe %lx is zero",
  1067. pipe);
  1068. return -1;
  1069. }
  1070. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
  1071. err("sohci_submit_job failed");
  1072. return -1;
  1073. }
  1074. wait_ms(10);
  1075. /* ohci_dump_status(&gohci); */
  1076. /* allow more time for a BULK device to react - some are slow */
  1077. #define BULK_TO 5000 /* timeout in milliseconds */
  1078. if (usb_pipetype (pipe) == PIPE_BULK)
  1079. timeout = BULK_TO;
  1080. else
  1081. timeout = 100;
  1082. /* wait for it to complete */
  1083. for (;;) {
  1084. /* check whether the controller is done */
  1085. stat = hc_interrupt();
  1086. if (stat < 0) {
  1087. stat = USB_ST_CRC_ERR;
  1088. break;
  1089. }
  1090. if (stat >= 0 && stat != 0xff) {
  1091. /* 0xff is returned for an SF-interrupt */
  1092. break;
  1093. }
  1094. if (--timeout) {
  1095. wait_ms(1);
  1096. } else {
  1097. err("CTL:TIMEOUT ");
  1098. stat = USB_ST_CRC_ERR;
  1099. break;
  1100. }
  1101. }
  1102. /* we got an Root Hub Status Change interrupt */
  1103. if (got_rhsc) {
  1104. #ifdef DEBUG
  1105. ohci_dump_roothub (&gohci, 1);
  1106. #endif
  1107. got_rhsc = 0;
  1108. /* abuse timeout */
  1109. timeout = rh_check_port_status(&gohci);
  1110. if (timeout >= 0) {
  1111. #if 0 /* this does nothing useful, but leave it here in case that changes */
  1112. /* the called routine adds 1 to the passed value */
  1113. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1114. #endif
  1115. /*
  1116. * XXX
  1117. * This is potentially dangerous because it assumes
  1118. * that only one device is ever plugged in!
  1119. */
  1120. devgone = dev;
  1121. }
  1122. }
  1123. dev->status = stat;
  1124. dev->act_len = transfer_len;
  1125. #ifdef DEBUG
  1126. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
  1127. #else
  1128. wait_ms(1);
  1129. #endif
  1130. /* free TDs in urb_priv */
  1131. urb_free_priv (&urb_priv);
  1132. return 0;
  1133. }
  1134. /* submit routines called from usb.c */
  1135. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1136. int transfer_len)
  1137. {
  1138. info("submit_bulk_msg");
  1139. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1140. }
  1141. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1142. int transfer_len, struct devrequest *setup)
  1143. {
  1144. int maxsize = usb_maxpacket(dev, pipe);
  1145. info("submit_control_msg");
  1146. #ifdef DEBUG
  1147. urb_priv.actual_length = 0;
  1148. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1149. #else
  1150. wait_ms(1);
  1151. #endif
  1152. if (!maxsize) {
  1153. err("submit_control_message: pipesize for pipe %lx is zero",
  1154. pipe);
  1155. return -1;
  1156. }
  1157. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1158. gohci.rh.dev = dev;
  1159. /* root hub - redirect */
  1160. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1161. setup);
  1162. }
  1163. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1164. }
  1165. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1166. int transfer_len, int interval)
  1167. {
  1168. info("submit_int_msg");
  1169. return -1;
  1170. }
  1171. /*-------------------------------------------------------------------------*
  1172. * HC functions
  1173. *-------------------------------------------------------------------------*/
  1174. /* reset the HC and BUS */
  1175. static int hc_reset (ohci_t *ohci)
  1176. {
  1177. int timeout = 30;
  1178. int smm_timeout = 50; /* 0,5 sec */
  1179. dbg("%s\n", __FUNCTION__);
  1180. if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1181. writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1182. info("USB HC TakeOver from SMM");
  1183. while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
  1184. wait_ms (10);
  1185. if (--smm_timeout == 0) {
  1186. err("USB HC TakeOver failed!");
  1187. return -1;
  1188. }
  1189. }
  1190. }
  1191. /* Disable HC interrupts */
  1192. writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1193. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
  1194. ohci->slot_name,
  1195. readl(&ohci->regs->control));
  1196. /* Reset USB (needed by some controllers) */
  1197. writel (0, &ohci->regs->control);
  1198. /* HC Reset requires max 10 us delay */
  1199. writel (OHCI_HCR, &ohci->regs->cmdstatus);
  1200. while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1201. if (--timeout == 0) {
  1202. err("USB HC reset timed out!");
  1203. return -1;
  1204. }
  1205. udelay (1);
  1206. }
  1207. return 0;
  1208. }
  1209. /*-------------------------------------------------------------------------*/
  1210. /* Start an OHCI controller, set the BUS operational
  1211. * enable interrupts
  1212. * connect the virtual root hub */
  1213. static int hc_start (ohci_t * ohci)
  1214. {
  1215. __u32 mask;
  1216. unsigned int fminterval;
  1217. ohci->disabled = 1;
  1218. /* Tell the controller where the control and bulk lists are
  1219. * The lists are empty now. */
  1220. writel (0, &ohci->regs->ed_controlhead);
  1221. writel (0, &ohci->regs->ed_bulkhead);
  1222. writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1223. fminterval = 0x2edf;
  1224. writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1225. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1226. writel (fminterval, &ohci->regs->fminterval);
  1227. writel (0x628, &ohci->regs->lsthresh);
  1228. /* start controller operations */
  1229. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1230. ohci->disabled = 0;
  1231. writel (ohci->hc_control, &ohci->regs->control);
  1232. /* disable all interrupts */
  1233. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1234. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1235. OHCI_INTR_OC | OHCI_INTR_MIE);
  1236. writel (mask, &ohci->regs->intrdisable);
  1237. /* clear all interrupts */
  1238. mask &= ~OHCI_INTR_MIE;
  1239. writel (mask, &ohci->regs->intrstatus);
  1240. /* Choose the interrupts we care about now - but w/o MIE */
  1241. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1242. writel (mask, &ohci->regs->intrenable);
  1243. #ifdef OHCI_USE_NPS
  1244. /* required for AMD-756 and some Mac platforms */
  1245. writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
  1246. &ohci->regs->roothub.a);
  1247. writel (RH_HS_LPSC, &ohci->regs->roothub.status);
  1248. #endif /* OHCI_USE_NPS */
  1249. #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
  1250. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1251. mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
  1252. /* connect the virtual root hub */
  1253. ohci->rh.devnum = 0;
  1254. return 0;
  1255. }
  1256. /*-------------------------------------------------------------------------*/
  1257. /* an interrupt happens */
  1258. static int
  1259. hc_interrupt (void)
  1260. {
  1261. ohci_t *ohci = &gohci;
  1262. struct ohci_regs *regs = ohci->regs;
  1263. int ints;
  1264. int stat = -1;
  1265. if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
  1266. ints = OHCI_INTR_WDH;
  1267. } else {
  1268. ints = readl (&regs->intrstatus);
  1269. }
  1270. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1271. if (ints & OHCI_INTR_RHSC) {
  1272. got_rhsc = 1;
  1273. }
  1274. if (ints & OHCI_INTR_UE) {
  1275. ohci->disabled++;
  1276. err ("OHCI Unrecoverable Error, controller usb-%s disabled",
  1277. ohci->slot_name);
  1278. /* e.g. due to PCI Master/Target Abort */
  1279. #ifdef DEBUG
  1280. ohci_dump (ohci, 1);
  1281. #else
  1282. wait_ms(1);
  1283. #endif
  1284. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1285. /* Make some non-interrupt context restart the controller. */
  1286. /* Count and limit the retries though; either hardware or */
  1287. /* software errors can go forever... */
  1288. hc_reset (ohci);
  1289. return -1;
  1290. }
  1291. if (ints & OHCI_INTR_WDH) {
  1292. wait_ms(1);
  1293. writel (OHCI_INTR_WDH, &regs->intrdisable);
  1294. stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
  1295. writel (OHCI_INTR_WDH, &regs->intrenable);
  1296. }
  1297. if (ints & OHCI_INTR_SO) {
  1298. dbg("USB Schedule overrun\n");
  1299. writel (OHCI_INTR_SO, &regs->intrenable);
  1300. stat = -1;
  1301. }
  1302. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1303. if (ints & OHCI_INTR_SF) {
  1304. unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
  1305. wait_ms(1);
  1306. writel (OHCI_INTR_SF, &regs->intrdisable);
  1307. if (ohci->ed_rm_list[frame] != NULL)
  1308. writel (OHCI_INTR_SF, &regs->intrenable);
  1309. stat = 0xff;
  1310. }
  1311. writel (ints, &regs->intrstatus);
  1312. return stat;
  1313. }
  1314. /*-------------------------------------------------------------------------*/
  1315. /*-------------------------------------------------------------------------*/
  1316. /* De-allocate all resources.. */
  1317. static void hc_release_ohci (ohci_t *ohci)
  1318. {
  1319. dbg ("USB HC release ohci usb-%s", ohci->slot_name);
  1320. if (!ohci->disabled)
  1321. hc_reset (ohci);
  1322. }
  1323. /*-------------------------------------------------------------------------*/
  1324. /*
  1325. * low level initalisation routine, called from usb.c
  1326. */
  1327. static char ohci_inited = 0;
  1328. int usb_lowlevel_init(void)
  1329. {
  1330. #if CFG_USB_CPU_INIT
  1331. /* cpu dependant init */
  1332. if(usb_cpu_init())
  1333. return -1;
  1334. #endif
  1335. #if CFG_USB_BOARD_INIT
  1336. /* board dependant init */
  1337. if(usb_board_init())
  1338. return -1;
  1339. #endif
  1340. memset (&gohci, 0, sizeof (ohci_t));
  1341. memset (&urb_priv, 0, sizeof (urb_priv_t));
  1342. /* align the storage */
  1343. if ((__u32)&ghcca[0] & 0xff) {
  1344. err("HCCA not aligned!!");
  1345. return -1;
  1346. }
  1347. phcca = &ghcca[0];
  1348. info("aligned ghcca %p", phcca);
  1349. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1350. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1351. err("EDs not aligned!!");
  1352. return -1;
  1353. }
  1354. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1355. if ((__u32)gtd & 0x7) {
  1356. err("TDs not aligned!!");
  1357. return -1;
  1358. }
  1359. ptd = gtd;
  1360. gohci.hcca = phcca;
  1361. memset (phcca, 0, sizeof (struct ohci_hcca));
  1362. gohci.disabled = 1;
  1363. gohci.sleeping = 0;
  1364. gohci.irq = -1;
  1365. gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
  1366. gohci.flags = 0;
  1367. gohci.slot_name = CFG_USB_SLOT_NAME;
  1368. if (hc_reset (&gohci) < 0) {
  1369. hc_release_ohci (&gohci);
  1370. err ("can't reset usb-%s", gohci.slot_name);
  1371. /* Initialization failed disable clocks */
  1372. #if CFG_USB_BOARD_INIT
  1373. /* board dependant cleanup */
  1374. usb_board_stop();
  1375. #endif
  1376. #if CFG_USB_CPU_INIT
  1377. /* cpu dependant cleanup */
  1378. usb_cpu_stop();
  1379. #endif
  1380. return -1;
  1381. }
  1382. /* FIXME this is a second HC reset; why?? */
  1383. /* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
  1384. wait_ms(10); */
  1385. if (hc_start (&gohci) < 0) {
  1386. err ("can't start usb-%s", gohci.slot_name);
  1387. hc_release_ohci (&gohci);
  1388. /* Initialization failed */
  1389. #if CFG_USB_BOARD_INIT
  1390. /* board dependant cleanup */
  1391. usb_board_stop();
  1392. #endif
  1393. #if CFG_USB_CPU_INIT
  1394. /* cpu dependant cleanup */
  1395. usb_cpu_stop();
  1396. #endif
  1397. return -1;
  1398. }
  1399. #ifdef DEBUG
  1400. ohci_dump (&gohci, 1);
  1401. #else
  1402. wait_ms(1);
  1403. #endif
  1404. ohci_inited = 1;
  1405. return 0;
  1406. }
  1407. int usb_lowlevel_stop(void)
  1408. {
  1409. /* this gets called really early - before the controller has */
  1410. /* even been initialized! */
  1411. if (!ohci_inited)
  1412. return 0;
  1413. /* TODO release any interrupts, etc. */
  1414. /* call hc_release_ohci() here ? */
  1415. hc_reset (&gohci);
  1416. #if CFG_USB_BOARD_INIT
  1417. /* board dependant cleanup */
  1418. if(usb_board_stop())
  1419. return -1;
  1420. #endif
  1421. #if CFG_USB_CPU_INIT
  1422. /* cpu dependant cleanup */
  1423. if(usb_cpu_stop())
  1424. return -1;
  1425. #endif
  1426. return 0;
  1427. }
  1428. #endif /* CONFIG_USB_OHCI */