usb_ohci.c 43 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200.
  3. *
  4. * (C) Copyright 2003
  5. * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  6. *
  7. * Note: Much of this code has been derived from Linux 2.4
  8. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  9. * (C) Copyright 2000-2002 David Brownell
  10. *
  11. * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
  12. * ebenard@eukrea.com - based on s3c24x0's driver
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. *
  32. */
  33. /*
  34. * IMPORTANT NOTES
  35. * 1 - you MUST define LITTLEENDIAN in the configuration file for the
  36. * board or this driver will NOT work!
  37. * 2 - this driver is intended for use with USB Mass Storage Devices
  38. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  39. * 3 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
  40. * to activate workaround for bug #41 or this driver will NOT work!
  41. */
  42. #include <common.h>
  43. /* #include <pci.h> no PCI on the S3C24X0 */
  44. #ifdef CONFIG_USB_OHCI
  45. #include <asm/arch/hardware.h>
  46. #include <malloc.h>
  47. #include <usb.h>
  48. #include "usb_ohci.h"
  49. #define OHCI_USE_NPS /* force NoPowerSwitching mode */
  50. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  51. /* For initializing controller (mask in an HCFS mode too) */
  52. #define OHCI_CONTROL_INIT \
  53. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  54. #define readl(a) (*((vu_long *)(a)))
  55. #define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
  56. #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  57. #undef DEBUG
  58. #ifdef DEBUG
  59. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  60. #else
  61. #define dbg(format, arg...) do {} while(0)
  62. #endif /* DEBUG */
  63. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  64. #undef SHOW_INFO
  65. #ifdef SHOW_INFO
  66. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  67. #else
  68. #define info(format, arg...) do {} while(0)
  69. #endif
  70. #define m16_swap(x) swap_16(x)
  71. #define m32_swap(x) swap_32(x)
  72. /* global ohci_t */
  73. static ohci_t gohci;
  74. /* this must be aligned to a 256 byte boundary */
  75. struct ohci_hcca ghcca[1];
  76. /* a pointer to the aligned storage */
  77. struct ohci_hcca *phcca;
  78. /* this allocates EDs for all possible endpoints */
  79. struct ohci_device ohci_dev;
  80. /* urb_priv */
  81. urb_priv_t urb_priv;
  82. /* RHSC flag */
  83. int got_rhsc;
  84. /* device which was disconnected */
  85. struct usb_device *devgone;
  86. /*-------------------------------------------------------------------------*/
  87. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  88. * The erratum (#4) description is incorrect. AMD's workaround waits
  89. * till some bits (mostly reserved) are clear; ok for all revs.
  90. */
  91. #define OHCI_QUIRK_AMD756 0xabcd
  92. #define read_roothub(hc, register, mask) ({ \
  93. u32 temp = readl (&hc->regs->roothub.register); \
  94. if (hc->flags & OHCI_QUIRK_AMD756) \
  95. while (temp & mask) \
  96. temp = readl (&hc->regs->roothub.register); \
  97. temp; })
  98. static u32 roothub_a (struct ohci *hc)
  99. { return read_roothub (hc, a, 0xfc0fe000); }
  100. static inline u32 roothub_b (struct ohci *hc)
  101. { return readl (&hc->regs->roothub.b); }
  102. static inline u32 roothub_status (struct ohci *hc)
  103. { return readl (&hc->regs->roothub.status); }
  104. static u32 roothub_portstatus (struct ohci *hc, int i)
  105. { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
  106. /* forward declaration */
  107. static int hc_interrupt (void);
  108. static void
  109. td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
  110. int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
  111. /*-------------------------------------------------------------------------*
  112. * URB support functions
  113. *-------------------------------------------------------------------------*/
  114. /* free HCD-private data associated with this URB */
  115. static void urb_free_priv (urb_priv_t * urb)
  116. {
  117. int i;
  118. int last;
  119. struct td * td;
  120. last = urb->length - 1;
  121. if (last >= 0) {
  122. for (i = 0; i <= last; i++) {
  123. td = urb->td[i];
  124. if (td) {
  125. td->usb_dev = NULL;
  126. urb->td[i] = NULL;
  127. }
  128. }
  129. }
  130. }
  131. /*-------------------------------------------------------------------------*/
  132. #ifdef DEBUG
  133. static int sohci_get_current_frame_number (struct usb_device * dev);
  134. /* debug| print the main components of an URB
  135. * small: 0) header + data packets 1) just header */
  136. static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
  137. int transfer_len, struct devrequest * setup, char * str, int small)
  138. {
  139. urb_priv_t * purb = &urb_priv;
  140. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  141. str,
  142. sohci_get_current_frame_number (dev),
  143. usb_pipedevice (pipe),
  144. usb_pipeendpoint (pipe),
  145. usb_pipeout (pipe)? 'O': 'I',
  146. usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
  147. (usb_pipecontrol (pipe)? "CTRL": "BULK"),
  148. purb->actual_length,
  149. transfer_len, dev->status);
  150. #ifdef OHCI_VERBOSE_DEBUG
  151. if (!small) {
  152. int i, len;
  153. if (usb_pipecontrol (pipe)) {
  154. printf (__FILE__ ": cmd(8):");
  155. for (i = 0; i < 8 ; i++)
  156. printf (" %02x", ((__u8 *) setup) [i]);
  157. printf ("\n");
  158. }
  159. if (transfer_len > 0 && buffer) {
  160. printf (__FILE__ ": data(%d/%d):",
  161. purb->actual_length,
  162. transfer_len);
  163. len = usb_pipeout (pipe)?
  164. transfer_len: purb->actual_length;
  165. for (i = 0; i < 16 && i < len; i++)
  166. printf (" %02x", ((__u8 *) buffer) [i]);
  167. printf ("%s\n", i < len? "...": "");
  168. }
  169. }
  170. #endif
  171. }
  172. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  173. void ep_print_int_eds (ohci_t *ohci, char * str) {
  174. int i, j;
  175. __u32 * ed_p;
  176. for (i= 0; i < 32; i++) {
  177. j = 5;
  178. ed_p = &(ohci->hcca->int_table [i]);
  179. if (*ed_p == 0)
  180. continue;
  181. printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  182. while (*ed_p != 0 && j--) {
  183. ed_t *ed = (ed_t *)m32_swap(ed_p);
  184. printf (" ed: %4x;", ed->hwINFO);
  185. ed_p = &ed->hwNextED;
  186. }
  187. printf ("\n");
  188. }
  189. }
  190. static void ohci_dump_intr_mask (char *label, __u32 mask)
  191. {
  192. dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  193. label,
  194. mask,
  195. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  196. (mask & OHCI_INTR_OC) ? " OC" : "",
  197. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  198. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  199. (mask & OHCI_INTR_UE) ? " UE" : "",
  200. (mask & OHCI_INTR_RD) ? " RD" : "",
  201. (mask & OHCI_INTR_SF) ? " SF" : "",
  202. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  203. (mask & OHCI_INTR_SO) ? " SO" : ""
  204. );
  205. }
  206. static void maybe_print_eds (char *label, __u32 value)
  207. {
  208. ed_t *edp = (ed_t *)value;
  209. if (value) {
  210. dbg ("%s %08x", label, value);
  211. dbg ("%08x", edp->hwINFO);
  212. dbg ("%08x", edp->hwTailP);
  213. dbg ("%08x", edp->hwHeadP);
  214. dbg ("%08x", edp->hwNextED);
  215. }
  216. }
  217. static char * hcfs2string (int state)
  218. {
  219. switch (state) {
  220. case OHCI_USB_RESET: return "reset";
  221. case OHCI_USB_RESUME: return "resume";
  222. case OHCI_USB_OPER: return "operational";
  223. case OHCI_USB_SUSPEND: return "suspend";
  224. }
  225. return "?";
  226. }
  227. /* dump control and status registers */
  228. static void ohci_dump_status (ohci_t *controller)
  229. {
  230. struct ohci_regs *regs = controller->regs;
  231. __u32 temp;
  232. temp = readl (&regs->revision) & 0xff;
  233. if (temp != 0x10)
  234. dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
  235. temp = readl (&regs->control);
  236. dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  237. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  238. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  239. (temp & OHCI_CTRL_IR) ? " IR" : "",
  240. hcfs2string (temp & OHCI_CTRL_HCFS),
  241. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  242. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  243. (temp & OHCI_CTRL_IE) ? " IE" : "",
  244. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  245. temp & OHCI_CTRL_CBSR
  246. );
  247. temp = readl (&regs->cmdstatus);
  248. dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  249. (temp & OHCI_SOC) >> 16,
  250. (temp & OHCI_OCR) ? " OCR" : "",
  251. (temp & OHCI_BLF) ? " BLF" : "",
  252. (temp & OHCI_CLF) ? " CLF" : "",
  253. (temp & OHCI_HCR) ? " HCR" : ""
  254. );
  255. ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
  256. ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
  257. maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
  258. maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
  259. maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
  260. maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
  261. maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
  262. maybe_print_eds ("donehead", readl (&regs->donehead));
  263. }
  264. static void ohci_dump_roothub (ohci_t *controller, int verbose)
  265. {
  266. __u32 temp, ndp, i;
  267. temp = roothub_a (controller);
  268. ndp = (temp & RH_A_NDP);
  269. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  270. ndp = (ndp == 2) ? 1:0;
  271. #endif
  272. if (verbose) {
  273. dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  274. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  275. (temp & RH_A_NOCP) ? " NOCP" : "",
  276. (temp & RH_A_OCPM) ? " OCPM" : "",
  277. (temp & RH_A_DT) ? " DT" : "",
  278. (temp & RH_A_NPS) ? " NPS" : "",
  279. (temp & RH_A_PSM) ? " PSM" : "",
  280. ndp
  281. );
  282. temp = roothub_b (controller);
  283. dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
  284. temp,
  285. (temp & RH_B_PPCM) >> 16,
  286. (temp & RH_B_DR)
  287. );
  288. temp = roothub_status (controller);
  289. dbg ("roothub.status: %08x%s%s%s%s%s%s",
  290. temp,
  291. (temp & RH_HS_CRWE) ? " CRWE" : "",
  292. (temp & RH_HS_OCIC) ? " OCIC" : "",
  293. (temp & RH_HS_LPSC) ? " LPSC" : "",
  294. (temp & RH_HS_DRWE) ? " DRWE" : "",
  295. (temp & RH_HS_OCI) ? " OCI" : "",
  296. (temp & RH_HS_LPS) ? " LPS" : ""
  297. );
  298. }
  299. for (i = 0; i < ndp; i++) {
  300. temp = roothub_portstatus (controller, i);
  301. dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  302. i,
  303. temp,
  304. (temp & RH_PS_PRSC) ? " PRSC" : "",
  305. (temp & RH_PS_OCIC) ? " OCIC" : "",
  306. (temp & RH_PS_PSSC) ? " PSSC" : "",
  307. (temp & RH_PS_PESC) ? " PESC" : "",
  308. (temp & RH_PS_CSC) ? " CSC" : "",
  309. (temp & RH_PS_LSDA) ? " LSDA" : "",
  310. (temp & RH_PS_PPS) ? " PPS" : "",
  311. (temp & RH_PS_PRS) ? " PRS" : "",
  312. (temp & RH_PS_POCI) ? " POCI" : "",
  313. (temp & RH_PS_PSS) ? " PSS" : "",
  314. (temp & RH_PS_PES) ? " PES" : "",
  315. (temp & RH_PS_CCS) ? " CCS" : ""
  316. );
  317. }
  318. }
  319. static void ohci_dump (ohci_t *controller, int verbose)
  320. {
  321. dbg ("OHCI controller usb-%s state", controller->slot_name);
  322. /* dumps some of the state we know about */
  323. ohci_dump_status (controller);
  324. if (verbose)
  325. ep_print_int_eds (controller, "hcca");
  326. dbg ("hcca frame #%04x", controller->hcca->frame_no);
  327. ohci_dump_roothub (controller, 1);
  328. }
  329. #endif /* DEBUG */
  330. /*-------------------------------------------------------------------------*
  331. * Interface functions (URB)
  332. *-------------------------------------------------------------------------*/
  333. /* get a transfer request */
  334. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  335. int transfer_len, struct devrequest *setup, int interval)
  336. {
  337. ohci_t *ohci;
  338. ed_t * ed;
  339. urb_priv_t *purb_priv;
  340. int i, size = 0;
  341. ohci = &gohci;
  342. /* when controller's hung, permit only roothub cleanup attempts
  343. * such as powering down ports */
  344. if (ohci->disabled) {
  345. err("sohci_submit_job: EPIPE");
  346. return -1;
  347. }
  348. /* every endpoint has a ed, locate and fill it */
  349. if (!(ed = ep_add_ed (dev, pipe))) {
  350. err("sohci_submit_job: ENOMEM");
  351. return -1;
  352. }
  353. /* for the private part of the URB we need the number of TDs (size) */
  354. switch (usb_pipetype (pipe)) {
  355. case PIPE_BULK: /* one TD for every 4096 Byte */
  356. size = (transfer_len - 1) / 4096 + 1;
  357. break;
  358. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  359. size = (transfer_len == 0)? 2:
  360. (transfer_len - 1) / 4096 + 3;
  361. break;
  362. }
  363. if (size >= (N_URB_TD - 1)) {
  364. err("need %d TDs, only have %d", size, N_URB_TD);
  365. return -1;
  366. }
  367. purb_priv = &urb_priv;
  368. purb_priv->pipe = pipe;
  369. /* fill the private part of the URB */
  370. purb_priv->length = size;
  371. purb_priv->ed = ed;
  372. purb_priv->actual_length = 0;
  373. /* allocate the TDs */
  374. /* note that td[0] was allocated in ep_add_ed */
  375. for (i = 0; i < size; i++) {
  376. purb_priv->td[i] = td_alloc (dev);
  377. if (!purb_priv->td[i]) {
  378. purb_priv->length = i;
  379. urb_free_priv (purb_priv);
  380. err("sohci_submit_job: ENOMEM");
  381. return -1;
  382. }
  383. }
  384. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  385. urb_free_priv (purb_priv);
  386. err("sohci_submit_job: EINVAL");
  387. return -1;
  388. }
  389. /* link the ed into a chain if is not already */
  390. if (ed->state != ED_OPER)
  391. ep_link (ohci, ed);
  392. /* fill the TDs and link it to the ed */
  393. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
  394. return 0;
  395. }
  396. /*-------------------------------------------------------------------------*/
  397. #ifdef DEBUG
  398. /* tell us the current USB frame number */
  399. static int sohci_get_current_frame_number (struct usb_device *usb_dev)
  400. {
  401. ohci_t *ohci = &gohci;
  402. return m16_swap (ohci->hcca->frame_no);
  403. }
  404. #endif
  405. /*-------------------------------------------------------------------------*
  406. * ED handling functions
  407. *-------------------------------------------------------------------------*/
  408. /* link an ed into one of the HC chains */
  409. static int ep_link (ohci_t *ohci, ed_t *edi)
  410. {
  411. volatile ed_t *ed = edi;
  412. ed->state = ED_OPER;
  413. switch (ed->type) {
  414. case PIPE_CONTROL:
  415. ed->hwNextED = 0;
  416. if (ohci->ed_controltail == NULL) {
  417. writel (ed, &ohci->regs->ed_controlhead);
  418. } else {
  419. ohci->ed_controltail->hwNextED = m32_swap (ed);
  420. }
  421. ed->ed_prev = ohci->ed_controltail;
  422. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  423. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  424. ohci->hc_control |= OHCI_CTRL_CLE;
  425. writel (ohci->hc_control, &ohci->regs->control);
  426. }
  427. ohci->ed_controltail = edi;
  428. break;
  429. case PIPE_BULK:
  430. ed->hwNextED = 0;
  431. if (ohci->ed_bulktail == NULL) {
  432. writel (ed, &ohci->regs->ed_bulkhead);
  433. } else {
  434. ohci->ed_bulktail->hwNextED = m32_swap (ed);
  435. }
  436. ed->ed_prev = ohci->ed_bulktail;
  437. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  438. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  439. ohci->hc_control |= OHCI_CTRL_BLE;
  440. writel (ohci->hc_control, &ohci->regs->control);
  441. }
  442. ohci->ed_bulktail = edi;
  443. break;
  444. }
  445. return 0;
  446. }
  447. /*-------------------------------------------------------------------------*/
  448. /* unlink an ed from one of the HC chains.
  449. * just the link to the ed is unlinked.
  450. * the link from the ed still points to another operational ed or 0
  451. * so the HC can eventually finish the processing of the unlinked ed */
  452. static int ep_unlink (ohci_t *ohci, ed_t *ed)
  453. {
  454. ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
  455. switch (ed->type) {
  456. case PIPE_CONTROL:
  457. if (ed->ed_prev == NULL) {
  458. if (!ed->hwNextED) {
  459. ohci->hc_control &= ~OHCI_CTRL_CLE;
  460. writel (ohci->hc_control, &ohci->regs->control);
  461. }
  462. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
  463. } else {
  464. ed->ed_prev->hwNextED = ed->hwNextED;
  465. }
  466. if (ohci->ed_controltail == ed) {
  467. ohci->ed_controltail = ed->ed_prev;
  468. } else {
  469. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  470. }
  471. break;
  472. case PIPE_BULK:
  473. if (ed->ed_prev == NULL) {
  474. if (!ed->hwNextED) {
  475. ohci->hc_control &= ~OHCI_CTRL_BLE;
  476. writel (ohci->hc_control, &ohci->regs->control);
  477. }
  478. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
  479. } else {
  480. ed->ed_prev->hwNextED = ed->hwNextED;
  481. }
  482. if (ohci->ed_bulktail == ed) {
  483. ohci->ed_bulktail = ed->ed_prev;
  484. } else {
  485. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  486. }
  487. break;
  488. }
  489. ed->state = ED_UNLINK;
  490. return 0;
  491. }
  492. /*-------------------------------------------------------------------------*/
  493. /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
  494. * but the USB stack is a little bit stateless so we do it at every transaction
  495. * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
  496. * in all other cases the state is left unchanged
  497. * the ed info fields are setted anyway even though most of them should not change */
  498. static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
  499. {
  500. td_t *td;
  501. ed_t *ed_ret;
  502. volatile ed_t *ed;
  503. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
  504. (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
  505. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  506. err("ep_add_ed: pending delete");
  507. /* pending delete request */
  508. return NULL;
  509. }
  510. if (ed->state == ED_NEW) {
  511. ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
  512. /* dummy td; end of td list for ed */
  513. td = td_alloc (usb_dev);
  514. ed->hwTailP = m32_swap (td);
  515. ed->hwHeadP = ed->hwTailP;
  516. ed->state = ED_UNLINK;
  517. ed->type = usb_pipetype (pipe);
  518. ohci_dev.ed_cnt++;
  519. }
  520. ed->hwINFO = m32_swap (usb_pipedevice (pipe)
  521. | usb_pipeendpoint (pipe) << 7
  522. | (usb_pipeisoc (pipe)? 0x8000: 0)
  523. | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
  524. | usb_pipeslow (pipe) << 13
  525. | usb_maxpacket (usb_dev, pipe) << 16);
  526. return ed_ret;
  527. }
  528. /*-------------------------------------------------------------------------*
  529. * TD handling functions
  530. *-------------------------------------------------------------------------*/
  531. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  532. static void td_fill (ohci_t *ohci, unsigned int info,
  533. void *data, int len,
  534. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  535. {
  536. volatile td_t *td, *td_pt;
  537. #ifdef OHCI_FILL_TRACE
  538. int i;
  539. #endif
  540. if (index > urb_priv->length) {
  541. err("index > length");
  542. return;
  543. }
  544. /* use this td as the next dummy */
  545. td_pt = urb_priv->td [index];
  546. td_pt->hwNextTD = 0;
  547. /* fill the old dummy TD */
  548. td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
  549. td->ed = urb_priv->ed;
  550. td->next_dl_td = NULL;
  551. td->index = index;
  552. td->data = (__u32)data;
  553. #ifdef OHCI_FILL_TRACE
  554. if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
  555. for (i = 0; i < len; i++)
  556. printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
  557. printf("\n");
  558. }
  559. #endif
  560. if (!len)
  561. data = 0;
  562. td->hwINFO = m32_swap (info);
  563. td->hwCBP = m32_swap (data);
  564. if (data)
  565. td->hwBE = m32_swap (data + len - 1);
  566. else
  567. td->hwBE = 0;
  568. td->hwNextTD = m32_swap (td_pt);
  569. td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
  570. /* append to queue */
  571. td->ed->hwTailP = td->hwNextTD;
  572. }
  573. /*-------------------------------------------------------------------------*/
  574. /* prepare all TDs of a transfer */
  575. static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
  576. int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
  577. {
  578. ohci_t *ohci = &gohci;
  579. int data_len = transfer_len;
  580. void *data;
  581. int cnt = 0;
  582. __u32 info = 0;
  583. unsigned int toggle = 0;
  584. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
  585. if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  586. toggle = TD_T_TOGGLE;
  587. } else {
  588. toggle = TD_T_DATA0;
  589. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
  590. }
  591. urb->td_cnt = 0;
  592. if (data_len)
  593. data = buffer;
  594. else
  595. data = 0;
  596. switch (usb_pipetype (pipe)) {
  597. case PIPE_BULK:
  598. info = usb_pipeout (pipe)?
  599. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  600. while(data_len > 4096) {
  601. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
  602. data += 4096; data_len -= 4096; cnt++;
  603. }
  604. info = usb_pipeout (pipe)?
  605. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  606. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
  607. cnt++;
  608. if (!ohci->sleeping)
  609. writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  610. break;
  611. case PIPE_CONTROL:
  612. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  613. td_fill (ohci, info, setup, 8, dev, cnt++, urb);
  614. if (data_len > 0) {
  615. info = usb_pipeout (pipe)?
  616. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  617. /* NOTE: mishandles transfers >8K, some >4K */
  618. td_fill (ohci, info, data, data_len, dev, cnt++, urb);
  619. }
  620. info = usb_pipeout (pipe)?
  621. TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
  622. td_fill (ohci, info, data, 0, dev, cnt++, urb);
  623. if (!ohci->sleeping)
  624. writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  625. break;
  626. }
  627. if (urb->length != cnt)
  628. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  629. }
  630. /*-------------------------------------------------------------------------*
  631. * Done List handling functions
  632. *-------------------------------------------------------------------------*/
  633. /* calculate the transfer length and update the urb */
  634. static void dl_transfer_length(td_t * td)
  635. {
  636. __u32 tdINFO, tdBE, tdCBP;
  637. urb_priv_t *lurb_priv = &urb_priv;
  638. tdINFO = m32_swap (td->hwINFO);
  639. tdBE = m32_swap (td->hwBE);
  640. tdCBP = m32_swap (td->hwCBP);
  641. if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
  642. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  643. if (tdBE != 0) {
  644. if (td->hwCBP == 0)
  645. lurb_priv->actual_length += tdBE - td->data + 1;
  646. else
  647. lurb_priv->actual_length += tdCBP - td->data;
  648. }
  649. }
  650. }
  651. /*-------------------------------------------------------------------------*/
  652. /* replies to the request have to be on a FIFO basis so
  653. * we reverse the reversed done-list */
  654. static td_t * dl_reverse_done_list (ohci_t *ohci)
  655. {
  656. __u32 td_list_hc;
  657. td_t *td_rev = NULL;
  658. td_t *td_list = NULL;
  659. urb_priv_t *lurb_priv = NULL;
  660. td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
  661. ohci->hcca->done_head = 0;
  662. while (td_list_hc) {
  663. td_list = (td_t *)td_list_hc;
  664. if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
  665. lurb_priv = &urb_priv;
  666. dbg(" USB-error/status: %x : %p",
  667. TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
  668. if (td_list->ed->hwHeadP & m32_swap (0x1)) {
  669. if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
  670. td_list->ed->hwHeadP =
  671. (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
  672. (td_list->ed->hwHeadP & m32_swap (0x2));
  673. lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
  674. } else
  675. td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
  676. }
  677. }
  678. td_list->next_dl_td = td_rev;
  679. td_rev = td_list;
  680. td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
  681. }
  682. return td_list;
  683. }
  684. /*-------------------------------------------------------------------------*/
  685. /* td done list */
  686. static int dl_done_list (ohci_t *ohci, td_t *td_list)
  687. {
  688. td_t *td_list_next = NULL;
  689. ed_t *ed;
  690. int cc = 0;
  691. int stat = 0;
  692. /* urb_t *urb; */
  693. urb_priv_t *lurb_priv;
  694. __u32 tdINFO, edHeadP, edTailP;
  695. while (td_list) {
  696. td_list_next = td_list->next_dl_td;
  697. lurb_priv = &urb_priv;
  698. tdINFO = m32_swap (td_list->hwINFO);
  699. ed = td_list->ed;
  700. dl_transfer_length(td_list);
  701. /* error code of transfer */
  702. cc = TD_CC_GET (tdINFO);
  703. if (cc != 0) {
  704. dbg("ConditionCode %#x", cc);
  705. stat = cc_to_error[cc];
  706. }
  707. if (ed->state != ED_NEW) {
  708. edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
  709. edTailP = m32_swap (ed->hwTailP);
  710. /* unlink eds if they are not busy */
  711. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  712. ep_unlink (ohci, ed);
  713. }
  714. td_list = td_list_next;
  715. }
  716. return stat;
  717. }
  718. /*-------------------------------------------------------------------------*
  719. * Virtual Root Hub
  720. *-------------------------------------------------------------------------*/
  721. /* Device descriptor */
  722. static __u8 root_hub_dev_des[] =
  723. {
  724. 0x12, /* __u8 bLength; */
  725. 0x01, /* __u8 bDescriptorType; Device */
  726. 0x10, /* __u16 bcdUSB; v1.1 */
  727. 0x01,
  728. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  729. 0x00, /* __u8 bDeviceSubClass; */
  730. 0x00, /* __u8 bDeviceProtocol; */
  731. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  732. 0x00, /* __u16 idVendor; */
  733. 0x00,
  734. 0x00, /* __u16 idProduct; */
  735. 0x00,
  736. 0x00, /* __u16 bcdDevice; */
  737. 0x00,
  738. 0x00, /* __u8 iManufacturer; */
  739. 0x01, /* __u8 iProduct; */
  740. 0x00, /* __u8 iSerialNumber; */
  741. 0x01 /* __u8 bNumConfigurations; */
  742. };
  743. /* Configuration descriptor */
  744. static __u8 root_hub_config_des[] =
  745. {
  746. 0x09, /* __u8 bLength; */
  747. 0x02, /* __u8 bDescriptorType; Configuration */
  748. 0x19, /* __u16 wTotalLength; */
  749. 0x00,
  750. 0x01, /* __u8 bNumInterfaces; */
  751. 0x01, /* __u8 bConfigurationValue; */
  752. 0x00, /* __u8 iConfiguration; */
  753. 0x40, /* __u8 bmAttributes;
  754. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  755. 0x00, /* __u8 MaxPower; */
  756. /* interface */
  757. 0x09, /* __u8 if_bLength; */
  758. 0x04, /* __u8 if_bDescriptorType; Interface */
  759. 0x00, /* __u8 if_bInterfaceNumber; */
  760. 0x00, /* __u8 if_bAlternateSetting; */
  761. 0x01, /* __u8 if_bNumEndpoints; */
  762. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  763. 0x00, /* __u8 if_bInterfaceSubClass; */
  764. 0x00, /* __u8 if_bInterfaceProtocol; */
  765. 0x00, /* __u8 if_iInterface; */
  766. /* endpoint */
  767. 0x07, /* __u8 ep_bLength; */
  768. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  769. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  770. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  771. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  772. 0x00,
  773. 0xff /* __u8 ep_bInterval; 255 ms */
  774. };
  775. static unsigned char root_hub_str_index0[] =
  776. {
  777. 0x04, /* __u8 bLength; */
  778. 0x03, /* __u8 bDescriptorType; String-descriptor */
  779. 0x09, /* __u8 lang ID */
  780. 0x04, /* __u8 lang ID */
  781. };
  782. static unsigned char root_hub_str_index1[] =
  783. {
  784. 28, /* __u8 bLength; */
  785. 0x03, /* __u8 bDescriptorType; String-descriptor */
  786. 'O', /* __u8 Unicode */
  787. 0, /* __u8 Unicode */
  788. 'H', /* __u8 Unicode */
  789. 0, /* __u8 Unicode */
  790. 'C', /* __u8 Unicode */
  791. 0, /* __u8 Unicode */
  792. 'I', /* __u8 Unicode */
  793. 0, /* __u8 Unicode */
  794. ' ', /* __u8 Unicode */
  795. 0, /* __u8 Unicode */
  796. 'R', /* __u8 Unicode */
  797. 0, /* __u8 Unicode */
  798. 'o', /* __u8 Unicode */
  799. 0, /* __u8 Unicode */
  800. 'o', /* __u8 Unicode */
  801. 0, /* __u8 Unicode */
  802. 't', /* __u8 Unicode */
  803. 0, /* __u8 Unicode */
  804. ' ', /* __u8 Unicode */
  805. 0, /* __u8 Unicode */
  806. 'H', /* __u8 Unicode */
  807. 0, /* __u8 Unicode */
  808. 'u', /* __u8 Unicode */
  809. 0, /* __u8 Unicode */
  810. 'b', /* __u8 Unicode */
  811. 0, /* __u8 Unicode */
  812. };
  813. /* Hub class-specific descriptor is constructed dynamically */
  814. /*-------------------------------------------------------------------------*/
  815. #define OK(x) len = (x); break
  816. #ifdef DEBUG
  817. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  818. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  819. #else
  820. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  821. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  822. #endif
  823. #define RD_RH_STAT roothub_status(&gohci)
  824. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  825. /* request to virtual root hub */
  826. int rh_check_port_status(ohci_t *controller)
  827. {
  828. __u32 temp, ndp, i;
  829. int res;
  830. res = -1;
  831. temp = roothub_a (controller);
  832. ndp = (temp & RH_A_NDP);
  833. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  834. ndp = (ndp == 2) ? 1:0;
  835. #endif
  836. for (i = 0; i < ndp; i++) {
  837. temp = roothub_portstatus (controller, i);
  838. /* check for a device disconnect */
  839. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  840. (RH_PS_PESC | RH_PS_CSC)) &&
  841. ((temp & RH_PS_CCS) == 0)) {
  842. res = i;
  843. break;
  844. }
  845. }
  846. return res;
  847. }
  848. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  849. void *buffer, int transfer_len, struct devrequest *cmd)
  850. {
  851. void * data = buffer;
  852. int leni = transfer_len;
  853. int len = 0;
  854. int stat = 0;
  855. __u32 datab[4];
  856. __u8 *data_buf = (__u8 *)datab;
  857. __u16 bmRType_bReq;
  858. __u16 wValue;
  859. __u16 wIndex;
  860. __u16 wLength;
  861. #ifdef DEBUG
  862. urb_priv.actual_length = 0;
  863. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
  864. #else
  865. wait_ms(1);
  866. #endif
  867. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  868. info("Root-Hub submit IRQ: NOT implemented");
  869. return 0;
  870. }
  871. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  872. wValue = m16_swap (cmd->value);
  873. wIndex = m16_swap (cmd->index);
  874. wLength = m16_swap (cmd->length);
  875. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  876. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  877. switch (bmRType_bReq) {
  878. /* Request Destination:
  879. without flags: Device,
  880. RH_INTERFACE: interface,
  881. RH_ENDPOINT: endpoint,
  882. RH_CLASS means HUB here,
  883. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  884. */
  885. case RH_GET_STATUS:
  886. *(__u16 *) data_buf = m16_swap (1); OK (2);
  887. case RH_GET_STATUS | RH_INTERFACE:
  888. *(__u16 *) data_buf = m16_swap (0); OK (2);
  889. case RH_GET_STATUS | RH_ENDPOINT:
  890. *(__u16 *) data_buf = m16_swap (0); OK (2);
  891. case RH_GET_STATUS | RH_CLASS:
  892. *(__u32 *) data_buf = m32_swap (
  893. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  894. OK (4);
  895. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  896. *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
  897. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  898. switch (wValue) {
  899. case (RH_ENDPOINT_STALL): OK (0);
  900. }
  901. break;
  902. case RH_CLEAR_FEATURE | RH_CLASS:
  903. switch (wValue) {
  904. case RH_C_HUB_LOCAL_POWER:
  905. OK(0);
  906. case (RH_C_HUB_OVER_CURRENT):
  907. WR_RH_STAT(RH_HS_OCIC); OK (0);
  908. }
  909. break;
  910. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  911. switch (wValue) {
  912. case (RH_PORT_ENABLE):
  913. WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
  914. case (RH_PORT_SUSPEND):
  915. WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
  916. case (RH_PORT_POWER):
  917. WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
  918. case (RH_C_PORT_CONNECTION):
  919. WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
  920. case (RH_C_PORT_ENABLE):
  921. WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
  922. case (RH_C_PORT_SUSPEND):
  923. WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
  924. case (RH_C_PORT_OVER_CURRENT):
  925. WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
  926. case (RH_C_PORT_RESET):
  927. WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
  928. }
  929. break;
  930. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  931. switch (wValue) {
  932. case (RH_PORT_SUSPEND):
  933. WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
  934. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  935. if (RD_RH_PORTSTAT & RH_PS_CCS)
  936. WR_RH_PORTSTAT (RH_PS_PRS);
  937. OK (0);
  938. case (RH_PORT_POWER):
  939. WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
  940. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  941. if (RD_RH_PORTSTAT & RH_PS_CCS)
  942. WR_RH_PORTSTAT (RH_PS_PES );
  943. OK (0);
  944. }
  945. break;
  946. case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
  947. case RH_GET_DESCRIPTOR:
  948. switch ((wValue & 0xff00) >> 8) {
  949. case (0x01): /* device descriptor */
  950. len = min_t(unsigned int,
  951. leni,
  952. min_t(unsigned int,
  953. sizeof (root_hub_dev_des),
  954. wLength));
  955. data_buf = root_hub_dev_des; OK(len);
  956. case (0x02): /* configuration descriptor */
  957. len = min_t(unsigned int,
  958. leni,
  959. min_t(unsigned int,
  960. sizeof (root_hub_config_des),
  961. wLength));
  962. data_buf = root_hub_config_des; OK(len);
  963. case (0x03): /* string descriptors */
  964. if(wValue==0x0300) {
  965. len = min_t(unsigned int,
  966. leni,
  967. min_t(unsigned int,
  968. sizeof (root_hub_str_index0),
  969. wLength));
  970. data_buf = root_hub_str_index0;
  971. OK(len);
  972. }
  973. if(wValue==0x0301) {
  974. len = min_t(unsigned int,
  975. leni,
  976. min_t(unsigned int,
  977. sizeof (root_hub_str_index1),
  978. wLength));
  979. data_buf = root_hub_str_index1;
  980. OK(len);
  981. }
  982. default:
  983. stat = USB_ST_STALLED;
  984. }
  985. break;
  986. case RH_GET_DESCRIPTOR | RH_CLASS:
  987. {
  988. __u32 temp = roothub_a (&gohci);
  989. data_buf [0] = 9; /* min length; */
  990. data_buf [1] = 0x29;
  991. data_buf [2] = temp & RH_A_NDP;
  992. #ifdef CONFIG_AT91C_PQFP_UHPBUG
  993. data_buf [2] = (data_buf [2] == 2) ? 1:0;
  994. #endif
  995. data_buf [3] = 0;
  996. if (temp & RH_A_PSM) /* per-port power switching? */
  997. data_buf [3] |= 0x1;
  998. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  999. data_buf [3] |= 0x10;
  1000. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  1001. data_buf [3] |= 0x8;
  1002. /* corresponds to data_buf[4-7] */
  1003. datab [1] = 0;
  1004. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  1005. temp = roothub_b (&gohci);
  1006. data_buf [7] = temp & RH_B_DR;
  1007. if (data_buf [2] < 7) {
  1008. data_buf [8] = 0xff;
  1009. } else {
  1010. data_buf [0] += 2;
  1011. data_buf [8] = (temp & RH_B_DR) >> 8;
  1012. data_buf [10] = data_buf [9] = 0xff;
  1013. }
  1014. len = min_t(unsigned int, leni,
  1015. min_t(unsigned int, data_buf [0], wLength));
  1016. OK (len);
  1017. }
  1018. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
  1019. case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
  1020. default:
  1021. dbg ("unsupported root hub command");
  1022. stat = USB_ST_STALLED;
  1023. }
  1024. #ifdef DEBUG
  1025. ohci_dump_roothub (&gohci, 1);
  1026. #else
  1027. wait_ms(1);
  1028. #endif
  1029. len = min_t(int, len, leni);
  1030. if (data != data_buf)
  1031. memcpy (data, data_buf, len);
  1032. dev->act_len = len;
  1033. dev->status = stat;
  1034. #ifdef DEBUG
  1035. if (transfer_len)
  1036. urb_priv.actual_length = transfer_len;
  1037. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1038. #else
  1039. wait_ms(1);
  1040. #endif
  1041. return stat;
  1042. }
  1043. /*-------------------------------------------------------------------------*/
  1044. /* common code for handling submit messages - used for all but root hub */
  1045. /* accesses. */
  1046. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1047. int transfer_len, struct devrequest *setup, int interval)
  1048. {
  1049. int stat = 0;
  1050. int maxsize = usb_maxpacket(dev, pipe);
  1051. int timeout;
  1052. /* device pulled? Shortcut the action. */
  1053. if (devgone == dev) {
  1054. dev->status = USB_ST_CRC_ERR;
  1055. return 0;
  1056. }
  1057. #ifdef DEBUG
  1058. urb_priv.actual_length = 0;
  1059. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1060. #else
  1061. wait_ms(1);
  1062. #endif
  1063. if (!maxsize) {
  1064. err("submit_common_message: pipesize for pipe %lx is zero",
  1065. pipe);
  1066. return -1;
  1067. }
  1068. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
  1069. err("sohci_submit_job failed");
  1070. return -1;
  1071. }
  1072. wait_ms(10);
  1073. /* ohci_dump_status(&gohci); */
  1074. /* allow more time for a BULK device to react - some are slow */
  1075. #define BULK_TO 5000 /* timeout in milliseconds */
  1076. if (usb_pipetype (pipe) == PIPE_BULK)
  1077. timeout = BULK_TO;
  1078. else
  1079. timeout = 100;
  1080. /* wait for it to complete */
  1081. for (;;) {
  1082. /* check whether the controller is done */
  1083. stat = hc_interrupt();
  1084. if (stat < 0) {
  1085. stat = USB_ST_CRC_ERR;
  1086. break;
  1087. }
  1088. if (stat >= 0 && stat != 0xff) {
  1089. /* 0xff is returned for an SF-interrupt */
  1090. break;
  1091. }
  1092. if (--timeout) {
  1093. wait_ms(1);
  1094. } else {
  1095. err("CTL:TIMEOUT ");
  1096. stat = USB_ST_CRC_ERR;
  1097. break;
  1098. }
  1099. }
  1100. /* we got an Root Hub Status Change interrupt */
  1101. if (got_rhsc) {
  1102. #ifdef DEBUG
  1103. ohci_dump_roothub (&gohci, 1);
  1104. #endif
  1105. got_rhsc = 0;
  1106. /* abuse timeout */
  1107. timeout = rh_check_port_status(&gohci);
  1108. if (timeout >= 0) {
  1109. #if 0 /* this does nothing useful, but leave it here in case that changes */
  1110. /* the called routine adds 1 to the passed value */
  1111. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1112. #endif
  1113. /*
  1114. * XXX
  1115. * This is potentially dangerous because it assumes
  1116. * that only one device is ever plugged in!
  1117. */
  1118. devgone = dev;
  1119. }
  1120. }
  1121. dev->status = stat;
  1122. dev->act_len = transfer_len;
  1123. #ifdef DEBUG
  1124. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
  1125. #else
  1126. wait_ms(1);
  1127. #endif
  1128. /* free TDs in urb_priv */
  1129. urb_free_priv (&urb_priv);
  1130. return 0;
  1131. }
  1132. /* submit routines called from usb.c */
  1133. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1134. int transfer_len)
  1135. {
  1136. info("submit_bulk_msg");
  1137. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1138. }
  1139. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1140. int transfer_len, struct devrequest *setup)
  1141. {
  1142. int maxsize = usb_maxpacket(dev, pipe);
  1143. info("submit_control_msg");
  1144. #ifdef DEBUG
  1145. urb_priv.actual_length = 0;
  1146. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1147. #else
  1148. wait_ms(1);
  1149. #endif
  1150. if (!maxsize) {
  1151. err("submit_control_message: pipesize for pipe %lx is zero",
  1152. pipe);
  1153. return -1;
  1154. }
  1155. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1156. gohci.rh.dev = dev;
  1157. /* root hub - redirect */
  1158. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1159. setup);
  1160. }
  1161. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1162. }
  1163. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1164. int transfer_len, int interval)
  1165. {
  1166. info("submit_int_msg");
  1167. return -1;
  1168. }
  1169. /*-------------------------------------------------------------------------*
  1170. * HC functions
  1171. *-------------------------------------------------------------------------*/
  1172. /* reset the HC and BUS */
  1173. static int hc_reset (ohci_t *ohci)
  1174. {
  1175. int timeout = 30;
  1176. int smm_timeout = 50; /* 0,5 sec */
  1177. dbg("%s\n", __FUNCTION__);
  1178. if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1179. writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1180. info("USB HC TakeOver from SMM");
  1181. while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
  1182. wait_ms (10);
  1183. if (--smm_timeout == 0) {
  1184. err("USB HC TakeOver failed!");
  1185. return -1;
  1186. }
  1187. }
  1188. }
  1189. /* Disable HC interrupts */
  1190. writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1191. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
  1192. ohci->slot_name,
  1193. readl(&ohci->regs->control));
  1194. /* Reset USB (needed by some controllers) */
  1195. writel (0, &ohci->regs->control);
  1196. /* HC Reset requires max 10 us delay */
  1197. writel (OHCI_HCR, &ohci->regs->cmdstatus);
  1198. while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1199. if (--timeout == 0) {
  1200. err("USB HC reset timed out!");
  1201. return -1;
  1202. }
  1203. udelay (1);
  1204. }
  1205. return 0;
  1206. }
  1207. /*-------------------------------------------------------------------------*/
  1208. /* Start an OHCI controller, set the BUS operational
  1209. * enable interrupts
  1210. * connect the virtual root hub */
  1211. static int hc_start (ohci_t * ohci)
  1212. {
  1213. __u32 mask;
  1214. unsigned int fminterval;
  1215. ohci->disabled = 1;
  1216. /* Tell the controller where the control and bulk lists are
  1217. * The lists are empty now. */
  1218. writel (0, &ohci->regs->ed_controlhead);
  1219. writel (0, &ohci->regs->ed_bulkhead);
  1220. writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1221. fminterval = 0x2edf;
  1222. writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1223. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1224. writel (fminterval, &ohci->regs->fminterval);
  1225. writel (0x628, &ohci->regs->lsthresh);
  1226. /* start controller operations */
  1227. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1228. ohci->disabled = 0;
  1229. writel (ohci->hc_control, &ohci->regs->control);
  1230. /* disable all interrupts */
  1231. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1232. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1233. OHCI_INTR_OC | OHCI_INTR_MIE);
  1234. writel (mask, &ohci->regs->intrdisable);
  1235. /* clear all interrupts */
  1236. mask &= ~OHCI_INTR_MIE;
  1237. writel (mask, &ohci->regs->intrstatus);
  1238. /* Choose the interrupts we care about now - but w/o MIE */
  1239. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1240. writel (mask, &ohci->regs->intrenable);
  1241. #ifdef OHCI_USE_NPS
  1242. /* required for AMD-756 and some Mac platforms */
  1243. writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
  1244. &ohci->regs->roothub.a);
  1245. writel (RH_HS_LPSC, &ohci->regs->roothub.status);
  1246. #endif /* OHCI_USE_NPS */
  1247. #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
  1248. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1249. mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
  1250. /* connect the virtual root hub */
  1251. ohci->rh.devnum = 0;
  1252. return 0;
  1253. }
  1254. /*-------------------------------------------------------------------------*/
  1255. /* an interrupt happens */
  1256. static int
  1257. hc_interrupt (void)
  1258. {
  1259. ohci_t *ohci = &gohci;
  1260. struct ohci_regs *regs = ohci->regs;
  1261. int ints;
  1262. int stat = -1;
  1263. if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
  1264. ints = OHCI_INTR_WDH;
  1265. } else {
  1266. ints = readl (&regs->intrstatus);
  1267. }
  1268. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1269. if (ints & OHCI_INTR_RHSC) {
  1270. got_rhsc = 1;
  1271. }
  1272. if (ints & OHCI_INTR_UE) {
  1273. ohci->disabled++;
  1274. err ("OHCI Unrecoverable Error, controller usb-%s disabled",
  1275. ohci->slot_name);
  1276. /* e.g. due to PCI Master/Target Abort */
  1277. #ifdef DEBUG
  1278. ohci_dump (ohci, 1);
  1279. #else
  1280. wait_ms(1);
  1281. #endif
  1282. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1283. /* Make some non-interrupt context restart the controller. */
  1284. /* Count and limit the retries though; either hardware or */
  1285. /* software errors can go forever... */
  1286. hc_reset (ohci);
  1287. return -1;
  1288. }
  1289. if (ints & OHCI_INTR_WDH) {
  1290. wait_ms(1);
  1291. writel (OHCI_INTR_WDH, &regs->intrdisable);
  1292. stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
  1293. writel (OHCI_INTR_WDH, &regs->intrenable);
  1294. }
  1295. if (ints & OHCI_INTR_SO) {
  1296. dbg("USB Schedule overrun\n");
  1297. writel (OHCI_INTR_SO, &regs->intrenable);
  1298. stat = -1;
  1299. }
  1300. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1301. if (ints & OHCI_INTR_SF) {
  1302. unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
  1303. wait_ms(1);
  1304. writel (OHCI_INTR_SF, &regs->intrdisable);
  1305. if (ohci->ed_rm_list[frame] != NULL)
  1306. writel (OHCI_INTR_SF, &regs->intrenable);
  1307. stat = 0xff;
  1308. }
  1309. writel (ints, &regs->intrstatus);
  1310. return stat;
  1311. }
  1312. /*-------------------------------------------------------------------------*/
  1313. /*-------------------------------------------------------------------------*/
  1314. /* De-allocate all resources.. */
  1315. static void hc_release_ohci (ohci_t *ohci)
  1316. {
  1317. dbg ("USB HC release ohci usb-%s", ohci->slot_name);
  1318. if (!ohci->disabled)
  1319. hc_reset (ohci);
  1320. }
  1321. /*-------------------------------------------------------------------------*/
  1322. /*
  1323. * low level initalisation routine, called from usb.c
  1324. */
  1325. static char ohci_inited = 0;
  1326. int usb_lowlevel_init(void)
  1327. {
  1328. /*
  1329. * Enable USB host clock.
  1330. */
  1331. *AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */
  1332. *AT91C_PMC_PCER = 1 << AT91C_ID_UHP; /* Peripheral Clock Enable Register */
  1333. memset (&gohci, 0, sizeof (ohci_t));
  1334. memset (&urb_priv, 0, sizeof (urb_priv_t));
  1335. /* align the storage */
  1336. if ((__u32)&ghcca[0] & 0xff) {
  1337. err("HCCA not aligned!!");
  1338. return -1;
  1339. }
  1340. phcca = &ghcca[0];
  1341. info("aligned ghcca %p", phcca);
  1342. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1343. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1344. err("EDs not aligned!!");
  1345. return -1;
  1346. }
  1347. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1348. if ((__u32)gtd & 0x7) {
  1349. err("TDs not aligned!!");
  1350. return -1;
  1351. }
  1352. ptd = gtd;
  1353. gohci.hcca = phcca;
  1354. memset (phcca, 0, sizeof (struct ohci_hcca));
  1355. gohci.disabled = 1;
  1356. gohci.sleeping = 0;
  1357. gohci.irq = -1;
  1358. gohci.regs = (struct ohci_regs *)AT91_USB_HOST_BASE;
  1359. gohci.flags = 0;
  1360. gohci.slot_name = "at91rm9200";
  1361. if (hc_reset (&gohci) < 0) {
  1362. hc_release_ohci (&gohci);
  1363. /* Initialization failed */
  1364. *AT91C_PMC_PCER = AT91C_ID_UHP;
  1365. *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
  1366. return -1;
  1367. }
  1368. /* FIXME this is a second HC reset; why?? */
  1369. /* writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
  1370. wait_ms (10);*/
  1371. if (hc_start (&gohci) < 0) {
  1372. err ("can't start usb-%s", gohci.slot_name);
  1373. hc_release_ohci (&gohci);
  1374. /* Initialization failed */
  1375. *AT91C_PMC_PCER = AT91C_ID_UHP;
  1376. *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
  1377. return -1;
  1378. }
  1379. #ifdef DEBUG
  1380. ohci_dump (&gohci, 1);
  1381. #else
  1382. wait_ms(1);
  1383. #endif
  1384. ohci_inited = 1;
  1385. return 0;
  1386. }
  1387. int usb_lowlevel_stop(void)
  1388. {
  1389. /* this gets called really early - before the controller has */
  1390. /* even been initialized! */
  1391. if (!ohci_inited)
  1392. return 0;
  1393. /* TODO release any interrupts, etc. */
  1394. /* call hc_release_ohci() here ? */
  1395. hc_reset (&gohci);
  1396. /* may not want to do this */
  1397. *AT91C_PMC_PCER = 1 << AT91C_ID_UHP;
  1398. *AT91C_PMC_SCDR = 1 << AT91C_PMC_UHP; /* 48MHz clock disabled for UHP */
  1399. return 0;
  1400. }
  1401. #endif /* CONFIG_USB_OHCI */