TQM834x.h 18 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * TQM8349 board configuration file
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. */
  31. #define CONFIG_E300 1 /* E300 Family */
  32. #define CONFIG_MPC83xx 1 /* MPC83xx family */
  33. #define CONFIG_MPC834x 1 /* MPC834x specific */
  34. #define CONFIG_MPC8349 1 /* MPC8349 specific */
  35. #define CONFIG_TQM834X 1 /* TQM834X board specific */
  36. /* IMMR Base Addres Register, use Freescale default: 0xff400000 */
  37. #define CONFIG_SYS_IMMR 0xff400000
  38. /* System clock. Primary input clock when in PCI host mode */
  39. #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
  40. /*
  41. * Local Bus LCRR
  42. * LCRR: DLL bypass, Clock divider is 8
  43. *
  44. * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
  45. *
  46. * External Local Bus rate is
  47. * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  48. */
  49. #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
  50. #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
  51. /* board pre init: do not call, nothing to do */
  52. #undef CONFIG_BOARD_EARLY_INIT_F
  53. /* detect the number of flash banks */
  54. #define CONFIG_BOARD_EARLY_INIT_R
  55. /*
  56. * DDR Setup
  57. */
  58. #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
  59. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
  60. #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
  61. #define DDR_CASLAT_25 /* CASLAT set to 2.5 */
  62. #undef CONFIG_DDR_ECC /* only for ECC DDR module */
  63. #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
  64. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  65. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
  66. #define CONFIG_SYS_MEMTEST_END 0x00100000
  67. /*
  68. * FLASH on the Local Bus
  69. */
  70. #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
  71. #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
  72. #undef CONFIG_SYS_FLASH_CHECKSUM
  73. #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
  74. #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
  75. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
  76. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  77. /*
  78. * FLASH bank number detection
  79. */
  80. /*
  81. * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
  82. * banks has to be determined at runtime and stored in a gloabl variable
  83. * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
  84. * used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
  85. * should be made sufficiently large to accomodate the number of banks that
  86. * might actually be detected. Since most (all?) Flash related functions use
  87. * CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
  88. * defined as tqm834x_num_flash_banks.
  89. */
  90. #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
  91. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
  92. /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
  93. #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) | \
  94. BR_MS_GPCM | BR_PS_32 | BR_V)
  95. /* FLASH timing (0x0000_0c54) */
  96. #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
  97. OR_GPCM_SCY_5 | OR_GPCM_TRLX)
  98. #define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
  99. #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
  100. #define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
  101. #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
  102. /* disable remaining mappings */
  103. #define CONFIG_SYS_BR1_PRELIM 0x00000000
  104. #define CONFIG_SYS_OR1_PRELIM 0x00000000
  105. #define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
  106. #define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
  107. #define CONFIG_SYS_BR2_PRELIM 0x00000000
  108. #define CONFIG_SYS_OR2_PRELIM 0x00000000
  109. #define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
  110. #define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
  111. #define CONFIG_SYS_BR3_PRELIM 0x00000000
  112. #define CONFIG_SYS_OR3_PRELIM 0x00000000
  113. #define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
  114. #define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
  115. /*
  116. * Monitor config
  117. */
  118. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  119. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  120. # define CONFIG_SYS_RAMBOOT
  121. #else
  122. # undef CONFIG_SYS_RAMBOOT
  123. #endif
  124. #define CONFIG_SYS_INIT_RAM_LOCK 1
  125. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
  126. #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
  127. #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
  128. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  129. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  130. #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */
  131. #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
  132. /*
  133. * Serial Port
  134. */
  135. #define CONFIG_CONS_INDEX 1
  136. #define CONFIG_SYS_NS16550
  137. #define CONFIG_SYS_NS16550_SERIAL
  138. #define CONFIG_SYS_NS16550_REG_SIZE 1
  139. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  140. #define CONFIG_SYS_BAUDRATE_TABLE \
  141. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  142. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
  143. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
  144. /*
  145. * I2C
  146. */
  147. #define CONFIG_HARD_I2C /* I2C with hardware support */
  148. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  149. #define CONFIG_FSL_I2C
  150. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
  151. #define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
  152. #define CONFIG_SYS_I2C_OFFSET 0x3000
  153. /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
  154. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
  155. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
  156. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
  157. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
  158. #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
  159. /* I2C RTC */
  160. #define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
  161. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  162. /* I2C SYSMON (LM75) */
  163. #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
  164. #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
  165. #define CONFIG_SYS_DTT_MAX_TEMP 70
  166. #define CONFIG_SYS_DTT_LOW_TEMP -30
  167. #define CONFIG_SYS_DTT_HYSTERESIS 3
  168. /*
  169. * TSEC
  170. */
  171. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  172. #define CONFIG_MII
  173. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  174. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
  175. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  176. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
  177. #if defined(CONFIG_TSEC_ENET)
  178. #ifndef CONFIG_NET_MULTI
  179. #define CONFIG_NET_MULTI
  180. #endif
  181. #define CONFIG_TSEC1 1
  182. #define CONFIG_TSEC1_NAME "TSEC0"
  183. #define CONFIG_TSEC2 1
  184. #define CONFIG_TSEC2_NAME "TSEC1"
  185. #define TSEC1_PHY_ADDR 2
  186. #define TSEC2_PHY_ADDR 1
  187. #define TSEC1_PHYIDX 0
  188. #define TSEC2_PHYIDX 0
  189. #define TSEC1_FLAGS TSEC_GIGABIT
  190. #define TSEC2_FLAGS TSEC_GIGABIT
  191. /* Options are: TSEC[0-1] */
  192. #define CONFIG_ETHPRIME "TSEC0"
  193. #endif /* CONFIG_TSEC_ENET */
  194. /*
  195. * General PCI
  196. * Addresses are mapped 1-1.
  197. */
  198. #define CONFIG_PCI
  199. #if defined(CONFIG_PCI)
  200. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  201. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  202. /* PCI1 host bridge */
  203. #define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
  204. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  205. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  206. #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
  207. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  208. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  209. #define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
  210. #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
  211. #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
  212. #undef CONFIG_EEPRO100
  213. #define CONFIG_EEPRO100
  214. #undef CONFIG_TULIP
  215. #if !defined(CONFIG_PCI_PNP)
  216. #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
  217. #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
  218. #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
  219. #endif
  220. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
  221. #endif /* CONFIG_PCI */
  222. /*
  223. * Environment
  224. */
  225. #define CONFIG_ENV_IS_IN_FLASH 1
  226. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  227. #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
  228. #define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
  229. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  230. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  231. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  232. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  233. /*
  234. * BOOTP options
  235. */
  236. #define CONFIG_BOOTP_BOOTFILESIZE
  237. #define CONFIG_BOOTP_BOOTPATH
  238. #define CONFIG_BOOTP_GATEWAY
  239. #define CONFIG_BOOTP_HOSTNAME
  240. /*
  241. * Command line configuration.
  242. */
  243. #include <config_cmd_default.h>
  244. #define CONFIG_CMD_ASKENV
  245. #define CONFIG_CMD_DATE
  246. #define CONFIG_CMD_DHCP
  247. #define CONFIG_CMD_DTT
  248. #define CONFIG_CMD_EEPROM
  249. #define CONFIG_CMD_I2C
  250. #define CONFIG_CMD_NFS
  251. #define CONFIG_CMD_JFFS2
  252. #define CONFIG_CMD_MII
  253. #define CONFIG_CMD_PING
  254. #define CONFIG_CMD_REGINFO
  255. #define CONFIG_CMD_SNTP
  256. #if defined(CONFIG_PCI)
  257. #define CONFIG_CMD_PCI
  258. #endif
  259. #if defined(CONFIG_SYS_RAMBOOT)
  260. #undef CONFIG_CMD_SAVEENV
  261. #undef CONFIG_CMD_LOADS
  262. #endif
  263. /*
  264. * Miscellaneous configurable options
  265. */
  266. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  267. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  268. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  269. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  270. #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  271. #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
  272. #ifdef CONFIG_SYS_HUSH_PARSER
  273. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  274. #endif
  275. #if defined(CONFIG_CMD_KGDB)
  276. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  277. #else
  278. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  279. #endif
  280. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  281. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  282. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  283. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  284. #undef CONFIG_WATCHDOG /* watchdog disabled */
  285. /* pass open firmware flat tree */
  286. #define CONFIG_OF_LIBFDT 1
  287. #define CONFIG_OF_BOARD_SETUP 1
  288. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  289. /*
  290. * For booting Linux, the board info and command line data
  291. * have to be in the first 8 MB of memory, since this is
  292. * the maximum mapped by the Linux kernel during initialization.
  293. */
  294. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  295. #define CONFIG_SYS_HRCW_LOW (\
  296. HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
  297. HRCWL_DDR_TO_SCB_CLK_1X1 |\
  298. HRCWL_CSB_TO_CLKIN_4X1 |\
  299. HRCWL_VCO_1X2 |\
  300. HRCWL_CORE_TO_CSB_2X1)
  301. #if defined(PCI_64BIT)
  302. #define CONFIG_SYS_HRCW_HIGH (\
  303. HRCWH_PCI_HOST |\
  304. HRCWH_64_BIT_PCI |\
  305. HRCWH_PCI1_ARBITER_ENABLE |\
  306. HRCWH_PCI2_ARBITER_DISABLE |\
  307. HRCWH_CORE_ENABLE |\
  308. HRCWH_FROM_0X00000100 |\
  309. HRCWH_BOOTSEQ_DISABLE |\
  310. HRCWH_SW_WATCHDOG_DISABLE |\
  311. HRCWH_ROM_LOC_LOCAL_16BIT |\
  312. HRCWH_TSEC1M_IN_GMII |\
  313. HRCWH_TSEC2M_IN_GMII )
  314. #else
  315. #define CONFIG_SYS_HRCW_HIGH (\
  316. HRCWH_PCI_HOST |\
  317. HRCWH_32_BIT_PCI |\
  318. HRCWH_PCI1_ARBITER_ENABLE |\
  319. HRCWH_PCI2_ARBITER_DISABLE |\
  320. HRCWH_CORE_ENABLE |\
  321. HRCWH_FROM_0X00000100 |\
  322. HRCWH_BOOTSEQ_DISABLE |\
  323. HRCWH_SW_WATCHDOG_DISABLE |\
  324. HRCWH_ROM_LOC_LOCAL_16BIT |\
  325. HRCWH_TSEC1M_IN_GMII |\
  326. HRCWH_TSEC2M_IN_GMII )
  327. #endif
  328. /* System IO Config */
  329. #define CONFIG_SYS_SICRH 0
  330. #define CONFIG_SYS_SICRL SICRL_LDP_A
  331. /* i-cache and d-cache disabled */
  332. #define CONFIG_SYS_HID0_INIT 0x000000000
  333. #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
  334. HID0_ENABLE_INSTRUCTION_CACHE)
  335. #define CONFIG_SYS_HID2 HID2_HBE
  336. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  337. /* DDR 0 - 512M */
  338. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  339. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  340. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
  341. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  342. /* stack in DCACHE @ 512M (no backing mem) */
  343. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
  344. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  345. /* PCI */
  346. #ifdef CONFIG_PCI
  347. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  348. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  349. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
  350. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  351. #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  352. #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
  353. #else
  354. #define CONFIG_SYS_IBAT3L (0)
  355. #define CONFIG_SYS_IBAT3U (0)
  356. #define CONFIG_SYS_IBAT4L (0)
  357. #define CONFIG_SYS_IBAT4U (0)
  358. #define CONFIG_SYS_IBAT5L (0)
  359. #define CONFIG_SYS_IBAT5U (0)
  360. #endif
  361. /* IMMRBAR */
  362. #define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  363. #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
  364. /* FLASH */
  365. #define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  366. #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  367. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  368. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  369. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  370. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  371. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  372. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  373. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  374. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  375. #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
  376. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  377. #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
  378. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  379. #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
  380. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  381. #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
  382. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  383. /*
  384. * Internal Definitions
  385. *
  386. * Boot Flags
  387. */
  388. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  389. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  390. #if defined(CONFIG_CMD_KGDB)
  391. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  392. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  393. #endif
  394. /*
  395. * Environment Configuration
  396. */
  397. #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
  398. #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
  399. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  400. #define CONFIG_BAUDRATE 115200
  401. #define CONFIG_PREBOOT "echo;" \
  402. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  403. "echo"
  404. #undef CONFIG_BOOTARGS
  405. #define CONFIG_EXTRA_ENV_SETTINGS \
  406. "netdev=eth0\0" \
  407. "hostname=tqm834x\0" \
  408. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  409. "nfsroot=${serverip}:${rootpath}\0" \
  410. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  411. "addip=setenv bootargs ${bootargs} " \
  412. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  413. ":${hostname}:${netdev}:off panic=1\0" \
  414. "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  415. "flash_nfs_old=run nfsargs addip addcons;" \
  416. "bootm ${kernel_addr}\0" \
  417. "flash_nfs=run nfsargs addip addcons;" \
  418. "bootm ${kernel_addr} - ${fdt_addr}\0" \
  419. "flash_self_old=run ramargs addip addcons;" \
  420. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  421. "flash_self=run ramargs addip addcons;" \
  422. "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
  423. "net_nfs_old=tftp 400000 ${bootfile};" \
  424. "run nfsargs addip addcons;bootm\0" \
  425. "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
  426. "tftp ${fdt_addr_r} ${fdt_file}; " \
  427. "run nfsargs addip addcons; " \
  428. "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
  429. "rootpath=/opt/eldk/ppc_6xx\0" \
  430. "bootfile=tqm834x/uImage\0" \
  431. "fdtfile=tqm834x/tqm834x.dtb\0" \
  432. "kernel_addr_r=400000\0" \
  433. "fdt_addr_r=600000\0" \
  434. "ramdisk_addr_r=800000\0" \
  435. "kernel_addr=800C0000\0" \
  436. "fdt_addr=800A0000\0" \
  437. "ramdisk_addr=80300000\0" \
  438. "u-boot=tqm834x/u-boot.bin\0" \
  439. "load=tftp 200000 ${u-boot}\0" \
  440. "update=protect off 80000000 +${filesize};" \
  441. "era 80000000 +${filesize};" \
  442. "cp.b 200000 80000000 ${filesize}\0" \
  443. "upd=run load update\0" \
  444. ""
  445. #define CONFIG_BOOTCOMMAND "run flash_self"
  446. /*
  447. * JFFS2 partitions
  448. */
  449. /* mtdparts command line support */
  450. #define CONFIG_CMD_MTDPARTS
  451. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  452. #define CONFIG_FLASH_CFI_MTD
  453. #define MTDIDS_DEFAULT "nor0=TQM834x-0"
  454. /* default mtd partition table */
  455. #define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
  456. "1m(kernel),2m(initrd),"\
  457. "-(user);"\
  458. #endif /* __CONFIG_H */