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sc520.h

sc520.h 15 KB
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  1. /*
    2. 

  2.  * (C) Copyright 2002
    3. 

  3.  * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
    4. 

  4.  *
    5. 

  5.  * See file CREDITS for list of people who contributed to this
    6. 

  6.  * project.
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or
    9. 

  9.  * modify it under the terms of the GNU General Public License as
    10. 

  10.  * published by the Free Software Foundation; either version 2 of
    11. 

  11.  * the License, or (at your option) any later version.
    12. 

  12.  *
    13. 

  13.  * This program is distributed in the hope that it will be useful,
    14. 

  14.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15. 

  15.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16. 

  16.  * GNU General Public License for more details.
    17. 

  17.  *
    18. 

  18.  * You should have received a copy of the GNU General Public License
    19. 

  19.  * along with this program; if not, write to the Free Software
    20. 

  20.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    21. 

  21.  * MA 02111-1307 USA
    22. 

  22.  */
    23. 

  23. 

  24. #ifndef _ASM_IC_SC520_H_
    25. 

  25. #define _ASM_IC_SC520_H_ 1
    26. 

  26. 

  27. /* Memory mapped configuration registers, MMCR */
    28. 

  28. #define SC520_REVID		0x0000		/* ElanSC520 Microcontroller Revision ID Register */
    29. 

  29. #define SC520_CPUCTL		0x0002		/* Am5x86 CPU Control Register */
    30. 

  30. #define SC520_DRCCTL            0x0010          /* SDRAM Control Register */
    31. 

  31. #define SC520_DRCTMCTL		0x0012		/* SDRAM Timing Control Register */
    32. 

  32. #define SC520_DRCCFG		0x0014		/* SDRAM Bank Configuration Register*/
    33. 

  33. #define SC520_DRCBENDADR	0x0018		/* SDRAM Bank 0-3 Ending Address Register*/
    34. 

  34. #define SC520_ECCCTL		0x0020		/* ECC Control Register */
    35. 

  35. #define SC520_ECCSTA		0x0021		/* ECC Status Register */
    36. 

  36. #define SC520_ECCCKBPOS		0x0022		/* ECC Check Bit Position Register */
    37. 

  37. #define SC520_ECCSBADD		0x0024		/* ECC Single-Bit Error Address Register */
    38. 

  38. #define SC520_DBCTL		0x0040		/* SDRAM Buffer Control Register */
    39. 

  39. #define SC520_BOOTCSCTL		0x0050		/* /BOOTCS Control Register */
    40. 

  40. #define SC520_ROMCS1CTL		0x0054		/* /ROMCS1 Control Register */
    41. 

  41. #define SC520_ROMCS2CTL		0x0056		/* /ROMCS2 Control Register */
    42. 

  42. #define SC520_HBCTL		0x0060 		/* Host Bridge Control Register */
    43. 

  43. #define SC520_HBTGTIRQCTL	0x0062		/* Host Bridge Target Interrupt Control Register */
    44. 

  44. #define SC520_HBTGTIRQSTA	0x0064		/* Host Bridge Target Interrupt Status Register */
    45. 

  45. #define SC520_HBMSTIRQCTL	0x0066		/* Host Bridge Target Interrupt Control Register */
    46. 

  46. #define SC520_HBMSTIRQSTA	0x0068		/* Host Bridge Master Interrupt Status Register */
    47. 

  47. #define SC520_MSTINTADD		0x006c		/* Host Bridge Master Interrupt Address Register */
    48. 

  48. #define SC520_SYSARBCTL		0x0070		/* System Arbiter Control Register */
    49. 

  49. #define SC520_PCIARBSTA		0x0071		/* PCI Bus Arbiter Status Register */
    50. 

  50. #define SC520_SYSARBMENB	0x0072		/* System Arbiter Master Enable Register */
    51. 

  51. #define SC520_ARBPRICTL		0x0074		/* Arbiter Priority Control Register */
    52. 

  52. #define SC520_ADDDECCTL     	0x0080 		/* Address Decode Control Register */
    53. 

  53. #define SC520_WPVSTA        	0x0082		/* Write-Protect Violation Status Register */
    54. 

  54. #define SC520_PAR0          	0x0088		/* Programmable Address Region 0 Register */
    55. 

  55. #define SC520_PAR1          	0x008c       	/* Programmable Address Region 1 Register */
    56. 

  56. #define SC520_PAR2          	0x0090       	/* Programmable Address Region 2 Register */
    57. 

  57. #define SC520_PAR3          	0x0094      	/* Programmable Address Region 3 Register */
    58. 

  58. #define SC520_PAR4          	0x0098       	/* Programmable Address Region 4 Register */
    59. 

  59. #define SC520_PAR5          	0x009c       	/* Programmable Address Region 5 Register */
    60. 

  60. #define SC520_PAR6         	0x00a0      	/* Programmable Address Region 6 Register */
    61. 

  61. #define SC520_PAR7          	0x00a4       	/* Programmable Address Region 7 Register */
    62. 

  62. #define SC520_PAR8          	0x00a8       	/* Programmable Address Region 8 Register */
    63. 

  63. #define SC520_PAR9          	0x00ac       	/* Programmable Address Region 9 Register */
    64. 

  64. #define SC520_PAR10         	0x00b0       	/* Programmable Address Region 10 Register */
    65. 

  65. #define SC520_PAR11         	0x00b4       	/* Programmable Address Region 11 Register */
    66. 

  66. #define SC520_PAR12         	0x00b8       	/* Programmable Address Region 12 Register */
    67. 

  67. #define SC520_PAR13         	0x00bc       	/* Programmable Address Region 13 Register */
    68. 

  68. #define SC520_PAR14         	0x00c0       	/* Programmable Address Region 14 Register */
    69. 

  69. #define SC520_PAR15		0x00c4		/* Programmable Address Region 15 Register */
    70. 

  70. #define SC520_GPECHO		0x0c00		/* GP Echo Mode Register */
    71. 

  71. #define SC520_GPCSDW		0x0c01		/* GP Chip Select Data Width Register */
    72. 

  72. #define SC520_GPCSQUAL		0x0c02		/* GP Chip Select Qualification Register */
    73. 

  73. #define SC520_GPCSRT		0x0c08		/* GP Chip Select Recovery Time Register */
    74. 

  74. #define SC520_GPCSPW		0x0c09		/* GP Chip Select Pulse Width Register */
    75. 

  75. #define SC520_GPCSOFF		0x0c0a		/* GP Chip Select Offset Register */
    76. 

  76. #define SC520_GPRDW		0x0c0b		/* GP Read Pulse Width Register */
    77. 

  77. #define SC520_GPRDOFF		0x0c0c		/* GP Read Offset Register */
    78. 

  78. #define SC520_GPWRW		0x0c0d		/* GP Write Pulse Width Register */
    79. 

  79. #define SC520_GPWROFF		0x0c0e		/* GP Write Offset Register */
    80. 

  80. #define SC520_GPALEW		0x0c0f		/* GP ALE Pulse Width Register */
    81. 

  81. #define SC520_GPALEOFF		0x0c10		/* GP ALE Offset Register */
    82. 

  82. #define SC520_PIOPFS15_0	0x0c20		/* PIO15-PIO0 Pin Function Select */
    83. 

  83. #define SC520_PIOPFS31_16	0x0c22		/* PIO31-PIO16 Pin Function Select */
    84. 

  84. #define SC520_CSPFS		0x0c24		/* Chip Select Pin Function Select */
    85. 

  85. #define SC520_CLKSEL		0x0c26		/* Clock Select */
    86. 

  86. #define SC520_DSCTL		0x0c28		/* Drive Strength Control */
    87. 

  87. #define SC520_PIODIR15_0	0x0c2a		/* PIO15-PIO0 Direction */
    88. 

  88. #define SC520_PIODIR31_16	0x0c2c		/* PIO31-PIO16 Direction */
    89. 

  89. #define SC520_PIODATA15_0	0x0c30		/* PIO15-PIO0 Data */
    90. 

  90. #define SC520_PIODATA31_16	0x0c32		/* PIO31-PIO16 Data */
    91. 

  91. #define SC520_PIOSET15_0	0x0c34		/* PIO15-PIO0 Set */
    92. 

  92. #define SC520_PIOSET31_16	0x0c36		/* PIO31-PIO16 Set */
    93. 

  93. #define SC520_PIOCLR15_0	0x0c38		/* PIO15-PIO0 Clear */
    94. 

  94. #define SC520_PIOCLR31_16	0x0c3a		/* PIO31-PIO16 Clear */
    95. 

  95. #define SC520_SWTMRMILLI 	0x0c60		/* Software Timer Millisecond Count */
    96. 

  96. #define SC520_SWTMRMICRO 	0x0c62		/* Software Timer Microsecond Count */
    97. 

  97. #define SC520_SWTMRCFG   	0x0c64		/* Software Timer Configuration */
    98. 

  98. #define SC520_GPTMRSTA		0x0c70		/* GP Timers Status Register */
    99. 

  99. #define SC520_GPTMR0CTL		0x0c72		/* GP Timer 0 Mode/Control Register */
    100. 

  100. #define SC520_GPTMR0CNT		0x0c74		/* GP Timer 0 Count Register */
    101. 

  101. #define SC520_GPTMR0MAXCMPA	0x0c76		/* GP Timer 0 Maxcount Compare A Register */
    102. 

  102. #define SC520_GPTMR0MAXCMPB	0x0c78		/* GP Timer 0 Maxcount Compare B Register */
    103. 

  103. #define SC520_GPTMR1CTL		0x0c7a		/* GP Timer 1 Mode/Control Register */
    104. 

  104. #define SC520_GPTMR1CNT		0x0c7c		/* GP Timer 1 Count Register */
    105. 

  105. #define SC520_GPTMR1MAXCMPA	0x0c7e		/* GP Timer 1 Maxcount Compare Register A */
    106. 

  106. #define SC520_GPTMR1MAXCMPB	0x0c80		/* GP Timer 1 Maxcount Compare B Register */
    107. 

  107. #define SC520_GPTMR2CTL		0x0c82		/* GP Timer 2 Mode/Control Register */
    108. 

  108. #define SC520_GPTMR2CNT		0x0c84		/* GP Timer 2 Count Register */
    109. 

  109. #define SC520_GPTMR2MAXCMPA	0x0c8e		/* GP Timer 2 Maxcount Compare A Register */
    110. 

  110. #define SC520_WDTMRCTL		0x0cb0		/* Watchdog Timer Control Register */
    111. 

  111. #define SC520_WDTMRCNTL		0x0cb2		/* Watchdog Timer Count Low Register */
    112. 

  112. #define SC520_WDTMRCNTH		0x0cb4		/* Watchdog Timer Count High Register */
    113. 

  113. #define SC520_UART1CTL		0x0cc0	        /* UART 1 General Control Register */
    114. 

  114. #define SC520_UART1STA		0x0cc1	        /* UART 1 General Status Register */
    115. 

  115. #define SC520_UART1FCRSHAD	0x0cc2	        /* UART 1 FIFO Control Shadow Register */
    116. 

  116. #define SC520_UART2CTL		0x0cc4	        /* UART 2 General Control Register */
    117. 

  117. #define SC520_UART2STA		0x0cc5	        /* UART 2 General Status Register */
    118. 

  118. #define SC520_UART2FCRSHAD	0x0cc6	        /* UART 2 FIFO Control Shadow Register */
    119. 

  119. #define SC520_PICICR		0x0d00		/* Interrupt Control Register */
    120. 

  120. #define SC520_MPICMODE		0x0d02		/* Master PIC Interrupt Mode Register */
    121. 

  121. #define SC520_SL1PICMODE	0x0d03		/* Slave 1 PIC Interrupt Mode Register */
    122. 

  122. #define SC520_SL2PICMODE	0x0d04		/* Slave 2 PIC Interrupt Mode Register */
    123. 

  123. #define SC520_SWINT16_1		0x0d08		/* Software Interrupt 16-1 Control Register */
    124. 

  124. #define SC520_SWINT22_17	0x0d0a		/* Software Interrupt 22-17/NMI Control Register */
    125. 

  125. #define SC520_INTPINPOL		0x0d10		/* Interrupt Pin Polarity Register */
    126. 

  126. #define SC520_PCIHOSTMAP	0x0d14		/* PCI Host Bridge Interrupt Mappin Register */
    127. 

  127. #define SC520_ECCMAP		0x0d18		/* ECC Interrupt Mapping Register */
    128. 

  128. #define SC520_GPTMR0MAP		0x0d1a		/* GP Timer 0 Interrupt Mapping Register */
    129. 

  129. #define SC520_GPTMR1MAP		0x0d1b		/* GP Timer 1 Interrupt Mapping Register */
    130. 

  130. #define SC520_GPTMR2MAP		0x0d1c		/* GP Timer 2 Interrupt Mapping Register */
    131. 

  131. #define SC520_PIT0MAP		0x0d20		/* PIT0 Interrupt Mapping Register */
    132. 

  132. #define SC520_PIT1MAP		0x0d21		/* PIT1 Interrupt Mapping Register */
    133. 

  133. #define SC520_PIT2MAP		0x0d22		/* PIT2 Interrupt Mapping Register */
    134. 

  134. #define SC520_UART1MAP		0x0d28		/* UART 1 Interrupt Mapping Register */
    135. 

  135. #define SC520_UART2MAP		0x0d29		/* UART 2 Interrupt Mapping Register */
    136. 

  136. #define SC520_PCIINTAMAP	0x0d30		/* PCI Interrupt A Mapping Register */
    137. 

  137. #define SC520_PCIINTBMAP	0x0d31		/* PCI Interrupt B Mapping Register */
    138. 

  138. #define SC520_PCIINTCMAP	0x0d32		/* PCI Interrupt C Mapping Register */
    139. 

  139. #define SC520_PCIINTDMAP	0x0d33		/* PCI Interrupt D Mapping Register */
    140. 

  140. #define SC520_DMABCINTMAP	0x0d40		/* DMA Buffer Chaining Interrupt Mapping Register */
    141. 

  141. #define SC520_SSIMAP		0x0d41		/* SSI Interrupt Mapping Register */
    142. 

  142. #define SC520_WDTMAP		0x0d42		/* Watchdog Timer Interrupt Mapping Register */
    143. 

  143. #define SC520_RTCMAP		0x0d43		/* RTC Interrupt Mapping Register */
    144. 

  144. #define SC520_WPVMAP		0x0d44		/* Write-Protect Interrupt Mapping Register */
    145. 

  145. #define SC520_ICEMAP		0x0d45		/* AMDebug JTAG RX/TX Interrupt Mapping Register */
    146. 

  146. #define SC520_FERRMAP		0x0d46		/* Floating Point Error Interrupt Mapping Register */
    147. 

  147. #define SC520_GP0IMAP		0x0d50		/* GPIRQ0 Interrupt Mapping Register */
    148. 

  148. #define SC520_GP1IMAP		0x0d51		/* GPIRQ1 Interrupt Mapping Register */
    149. 

  149. #define SC520_GP2IMAP		0x0d52		/* GPIRQ2 Interrupt Mapping Register */
    150. 

  150. #define SC520_GP3IMAP		0x0d53		/* GPIRQ3 Interrupt Mapping Register */
    151. 

  151. #define SC520_GP4IMAP		0x0d54		/* GPIRQ4 Interrupt Mapping Register */
    152. 

  152. #define SC520_GP5IMAP		0x0d55		/* GPIRQ5 Interrupt Mapping Register */
    153. 

  153. #define SC520_GP6IMAP		0x0d56		/* GPIRQ6 Interrupt Mapping Register */
    154. 

  154. #define SC520_GP7IMAP		0x0d57		/* GPIRQ7 Interrupt Mapping Register */
    155. 

  155. #define SC520_GP8IMAP		0x0d58		/* GPIRQ8 Interrupt Mapping Register */
    156. 

  156. #define SC520_GP9IMAP		0x0d59		/* GPIRQ9 Interrupt Mapping Register */
    157. 

  157. #define SC520_GP10IMAP		0x0d5a		/* GPIRQ10 Interrupt Mapping Register */
    158. 

  158. #define SC520_SYSINFO		0x0d70		/* System Board Information Register */
    159. 

  159. #define SC520_RESCFG		0x0d72		/* Reset Configuration Register */
    160. 

  160. #define SC520_RESSTA		0x0d74		/* Reset Status Register */
    161. 

  161. #define SC520_GPDMAMMIO		0x0d81		/* GP-DMA Memory-Mapped I/O Register */
    162. 

  162. #define SC520_GPDMAEXTCHMAPA	0x0d82		/* GP-DMA Resource Channel Map A */
    163. 

  163. #define SC520_GPDMAEXTCHMAPB	0x0d84		/* GP-DMA Resource Channel Map B */
    164. 

  164. #define SC520_GPDMAEXTPG0	0x0d86		/* GP-DMA Channel 0 Extended Page */
    165. 

  165. #define SC520_GPDMAEXTPG1	0x0d87		/* GP-DMA Channel 1 Extended Page */
    166. 

  166. #define SC520_GPDMAEXTPG2	0x0d88		/* GP-DMA Channel 2 Extended Page */
    167. 

  167. #define SC520_GPDMAEXTPG3	0x0d89		/* GP-DMA Channel 3 Extended Page */
    168. 

  168. #define SC520_GPDMAEXTPG5	0x0d8a		/* GP-DMA Channel 5 Extended Page */
    169. 

  169. #define SC520_GPDMAEXTPG6	0x0d8b		/* GP-DMA Channel 6 Extended Page */
    170. 

  170. #define SC520_GPDMAEXTPG7	0x0d8c		/* GP-DMA Channel 7 Extended Page */
    171. 

  171. #define SC520_GPDMAEXTTC3	0x0d90		/* GP-DMA Channel 3 Extender Transfer count */
    172. 

  172. #define SC520_GPDMAEXTTC5	0x0d91		/* GP-DMA Channel 5 Extender Transfer count */
    173. 

  173. #define SC520_GPDMAEXTTC6	0x0d92		/* GP-DMA Channel 6 Extender Transfer count */
    174. 

  174. #define SC520_GPDMAEXTTC7	0x0d93		/* GP-DMA Channel 7 Extender Transfer count */
    175. 

  175. #define SC520_GPDMABCCTL	0x0d98		/* Buffer Chaining Control */
    176. 

  176. #define SC520_GPDMABCSTA	0x0d99		/* Buffer Chaining Status */
    177. 

  177. #define SC520_GPDMABSINTENB	0x0d9a		/* Buffer Chaining Interrupt Enable */
    178. 

  178. #define SC520_GPDMABCVAL	0x0d9b		/* Buffer Chaining Valid */
    179. 

  179. #define SC520_GPDMANXTADDL3	0x0da0		/* GP-DMA Channel 3 Next Address Low */
    180. 

  180. #define SC520_GPDMANXTADDH3	0x0da2		/* GP-DMA Channel 3 Next Address High */
    181. 

  181. #define SC520_GPDMANXTADDL5	0x0da4		/* GP-DMA Channel 5 Next Address Low */
    182. 

  182. #define SC520_GPDMANXTADDH5	0x0da6		/* GP-DMA Channel 5 Next Address High */
    183. 

  183. #define SC520_GPDMANXTADDL6	0x0da8		/* GP-DMA Channel 6 Next Address Low */
    184. 

  184. #define SC520_GPDMANXTADDH6	0x0daa		/* GP-DMA Channel 6 Next Address High */
    185. 

  185. #define SC520_GPDMANXTADDL7	0x0dac		/* GP-DMA Channel 7 Next Address Low */
    186. 

  186. #define SC520_GPDMANXTADDH7	0x0dae		/* GP-DMA Channel 7 Next Address High */
    187. 

  187. #define SC520_GPDMANXTTCL3	0x0db0		/* GP-DMA Channel 3 Next Transfer Count Low */
    188. 

  188. #define SC520_GPDMANXTTCH3	0x0db2		/* GP-DMA Channel 3 Next Transfer Count High */
    189. 

  189. #define SC520_GPDMANXTTCL5	0x0db4		/* GP-DMA Channel 5 Next Transfer Count Low */
    190. 

  190. #define SC520_GPDMANXTTCH5	0x0db6		/* GP-DMA Channel 5 Next Transfer Count High */
    191. 

  191. #define SC520_GPDMANXTTCL6	0x0db8		/* GP-DMA Channel 6 Next Transfer Count Low */
    192. 

  192. #define SC520_GPDMANXTTCH6	0x0dba		/* GP-DMA Channel 6 Next Transfer Count High */
    193. 

  193. #define SC520_GPDMANXTTCL7	0x0dbc		/* GP-DMA Channel 7 Next Transfer Count Low */
    194. 

  194. #define SC520_GPDMANXTTCH7	0x0dbe		/* GP-DMA Channel 7 Next Transfer Count High */
    195. 

  195. 

  196. /* MMCR Register bits (not all of them :) ) */
    197. 

  197. 

  198. /* BITS for SC520_ADDDECCTL: */
    199. 

  199. #define WPV_INT_ENB		0x80		/* Write-Protect Violation Interrupt Enable */
    200. 

  200. #define IO_HOLE_DEST		0x10		/* I/O Hole Access Destination */
    201. 

  201. #define RTC_DIS			0x04		/* RTC Disable */
    202. 

  202. #define UART2_DIS		0x02		/* UART2 Disable */
    203. 

  203. #define UART1_DIS		0x01		/* UART1 Disable */
    204. 

  204. 

  205. /* bus mapping constants (used for PCI core initialization) */																																																 /* bus mapping constants */
    206. 

  206. #define SC520_REG_ADDR		0x00000cf8     
    207. 

  207. #define SC520_REG_DATA		0x00000cfc
    208. 

  208. 

  209. 

  210. #define SC520_ISA_MEM_PHYS	0x00000000
    211. 

  211. #define SC520_ISA_MEM_BUS	0x00000000
    212. 

  212. #define SC520_ISA_MEM_SIZE	0x01000000
    213. 

  213. 

  214. #define SC520_ISA_IO_PHYS	0x00000000
    215. 

  215. #define SC520_ISA_IO_BUS	0x00000000
    216. 

  216. #define SC520_ISA_IO_SIZE	0x00001000
    217. 

  217. 

  218. /* PCI I/O space from 0x1000 to 0xfdff */
    219. 

  219. #define SC520_PCI_IO_PHYS	0x00001000
    220. 

  220. #define SC520_PCI_IO_BUS	0x00001000
    221. 

  221. #define SC520_PCI_IO_SIZE	0x0000ee00
    222. 

  222. 

  223. /* system memory from 0x00000000 to 0x0fffffff */
    224. 

  224. #define	SC520_PCI_MEMORY_PHYS	0x00000000
    225. 

  225. #define	SC520_PCI_MEMORY_BUS	0x00000000
    226. 

  226. #define SC520_PCI_MEMORY_SIZE	0x10000000
    227. 

  227. 

  228. /* PCI bus memory from 0x10000000 to 0x27ffffff */
    229. 

  229. #define SC520_PCI_MEM_PHYS	0x10000000
    230. 

  230. #define SC520_PCI_MEM_BUS       0x10000000
    231. 

  231. #define SC520_PCI_MEM_SIZE	0x18000000
    232. 

  232. 

  233. /* 0x28000000 - 0x3fffffff is used by the flash banks */
    234. 

  234. 

  235. /* 0x40000000 - 0xffffffff is not adressable by the SC520 */
    236. 

  236. 

  237. /* utility functions */
    238. 

  238. void write_mmcr_byte(u16 mmcr, u8 data);
    239. 

  239. void write_mmcr_word(u16 mmcr, u16 data);
    240. 

  240. void write_mmcr_long(u16 mmcr, u32 data);
    241. 

  241. u8 read_mmcr_byte(u16 mmcr);
    242. 

  242. u16 read_mmcr_word(u16 mmcr);
    243. 

  243. u32 read_mmcr_long(u16 mmcr);
    244. 

  244. 

  245. void init_sc520(void);
    246. 

  246. unsigned long init_sc520_dram(void);
    247. 

  247. void pci_sc520_init(struct pci_controller *hose);
    248. 

  248. 

  249. #endif
    250.