P3G4.h 14 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #ifndef __ASSEMBLY__
  29. #include <galileo/core.h>
  30. #endif
  31. #include "../board/evb64260/local.h"
  32. /*
  33. * High Level Configuration Options
  34. * (easy to change)
  35. */
  36. #define CONFIG_P3G4 1 /* this is a P3G4 board */
  37. #define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
  38. #define CONFIG_SYS_TEXT_BASE 0xfff00000
  39. #define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */
  40. #undef CONFIG_ECC /* enable ECC support */
  41. /* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
  42. /* which initialization functions to call for this board */
  43. #define CONFIG_MISC_INIT_R 1
  44. #define CONFIG_BOARD_EARLY_INIT_F 1
  45. #define CONFIG_SYS_BOARD_NAME "P3G4"
  46. #undef CONFIG_SYS_HUSH_PARSER
  47. /*
  48. * The following defines let you select what serial you want to use
  49. * for your console driver.
  50. *
  51. * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
  52. * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  53. */
  54. #define CONFIG_MPSC
  55. #define CONFIG_MPSC_PORT 0
  56. /* define this if you want to enable GT MAC filtering */
  57. #define CONFIG_GT_USE_MAC_HASH_TABLE
  58. #undef CONFIG_ETHER_PORT_MII /* use RMII */
  59. #if 0
  60. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  61. #else
  62. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  63. #endif
  64. #define CONFIG_ZERO_BOOTDELAY_CHECK
  65. #define CONFIG_PREBOOT "echo;" \
  66. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  67. "echo"
  68. #undef CONFIG_BOOTARGS
  69. #define CONFIG_EXTRA_ENV_SETTINGS \
  70. "netdev=eth0\0" \
  71. "hostname=p3g4\0" \
  72. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  73. "nfsroot=${serverip}:${rootpath}\0" \
  74. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  75. "addip=setenv bootargs ${bootargs} " \
  76. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  77. ":${hostname}:${netdev}:off panic=1\0" \
  78. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  79. "flash_nfs=run nfsargs addip addtty;" \
  80. "bootm ${kernel_addr}\0" \
  81. "flash_self=run ramargs addip addtty;" \
  82. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  83. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  84. "bootm\0" \
  85. "rootpath=/opt/eldk/ppc_74xx\0" \
  86. "bootfile=/tftpboot/p3g4/uImage\0" \
  87. "kernel_addr=ff000000\0" \
  88. "ramdisk_addr=ff010000\0" \
  89. "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \
  90. "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
  91. "cp.b 100000 fff00000 ${filesize};" \
  92. "setenv filesize;saveenv\0" \
  93. "upd=run load update\0" \
  94. ""
  95. #define CONFIG_BOOTCOMMAND "run flash_self"
  96. #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
  97. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
  98. #undef CONFIG_WATCHDOG /* watchdog disabled */
  99. #undef CONFIG_ALTIVEC /* undef to disable */
  100. /*
  101. * BOOTP options
  102. */
  103. #define CONFIG_BOOTP_SUBNETMASK
  104. #define CONFIG_BOOTP_GATEWAY
  105. #define CONFIG_BOOTP_HOSTNAME
  106. #define CONFIG_BOOTP_BOOTPATH
  107. #define CONFIG_BOOTP_BOOTFILESIZE
  108. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  109. /*
  110. * Command line configuration.
  111. */
  112. #include <config_cmd_default.h>
  113. #define CONFIG_CMD_ASKENV
  114. #define CONFIG_CMD_DHCP
  115. #define CONFIG_CMD_PCI
  116. #define CONFIG_CMD_ELF
  117. #define CONFIG_CMD_MII
  118. #define CONFIG_CMD_PING
  119. #define CONFIG_CMD_UNIVERSE
  120. #define CONFIG_CMD_BSP
  121. /*
  122. * Miscellaneous configurable options
  123. */
  124. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  125. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  126. #if defined(CONFIG_CMD_KGDB)
  127. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  128. #else
  129. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  130. #endif
  131. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  132. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  133. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  134. #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
  135. #define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
  136. #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
  137. #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
  138. #define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */
  139. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  140. /*
  141. * Low Level Configuration Settings
  142. * (address mappings, register initial values, etc.)
  143. * You should know what you are doing if you make changes here.
  144. */
  145. /*-----------------------------------------------------------------------
  146. * Definitions for initial stack pointer and data area
  147. */
  148. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  149. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  150. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  151. #define CONFIG_SYS_INIT_RAM_LOCK
  152. /*-----------------------------------------------------------------------
  153. * Start addresses for the final memory configuration
  154. * (Set up by the startup code)
  155. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  156. */
  157. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  158. #define CONFIG_SYS_FLASH_BASE 0xff000000
  159. #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
  160. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  161. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  162. #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
  163. /* areas to map different things with the GT in physical space */
  164. #define CONFIG_SYS_DRAM_BANKS 1
  165. #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
  166. /* What to put in the bats. */
  167. #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
  168. /* Peripheral Device section */
  169. #define CONFIG_SYS_GT_REGS 0xf8000000
  170. #define CONFIG_SYS_DEV_BASE 0xff000000
  171. #define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
  172. #define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
  173. #define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
  174. #define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
  175. #define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */
  176. #define CONFIG_SYS_DEV1_SIZE 0 /* unused */
  177. #define CONFIG_SYS_DEV2_SIZE 0 /* unused */
  178. #define CONFIG_SYS_DEV3_SIZE 0 /* unused */
  179. #define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c
  180. #define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR
  181. #if 0 /* Wrong?? NTL */
  182. #define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
  183. /* DMAAck[1:0] GNT0[1:0] */
  184. #else
  185. #define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
  186. /* REQ0[1:0] GNT0[1:0] */
  187. #endif
  188. #define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
  189. /* DMAReq[4] DMAAck[4] WDNMI WDE */
  190. #if 0 /* Wrong?? NTL */
  191. #define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
  192. /* DMAAck[1:0] GNT1[1:0] */
  193. #else
  194. #define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
  195. /* GPP[22] (RS232IntB or PCI1Int) */
  196. /* GPP[21] (RS323IntA) */
  197. /* BClkIn */
  198. /* REQ1[1:0] GNT1[1:0] */
  199. #endif
  200. #if 0 /* Wrong?? NTL */
  201. # define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
  202. /* GPP[27:26] Int[1:0] */
  203. #else
  204. # define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
  205. /* GPP[29] (PCI1Int) */
  206. /* BClkOut0 */
  207. /* GPP[27] (PCI0Int) */
  208. /* GPP[26] (RtcInt or PCI1Int) */
  209. /* CPUInt[25:24] */
  210. #endif
  211. #define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
  212. #if 0 /* Wrong?? - NTL */
  213. # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6
  214. #else
  215. # define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
  216. /* gpp[29] */
  217. /* gpp[27:26] */
  218. /* gpp[22:21] */
  219. # define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
  220. /* idmas use buffer 1,1
  221. comm use buffer 0
  222. pci use buffer 1,1
  223. cpu use buffer 0
  224. normal load (see also ifdef HVL)
  225. standard SDRAM (see also ifdef REG)
  226. non staggered refresh */
  227. /* 31:26 25 23 20 19 18 16 */
  228. /* 110110 00 111 0 0 00 1 */
  229. /* refresh_count=0x200
  230. phisical interleaving disable
  231. virtual interleaving enable */
  232. /* 15 14 13:0 */
  233. /* 1 0 0x200 */
  234. #endif
  235. #if 0
  236. #define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE
  237. #define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */
  238. #endif
  239. #undef CONFIG_SYS_INIT_CHAN1
  240. #undef CONFIG_SYS_INIT_CHAN2
  241. #if 0
  242. #define SRAM_BASE CONFIG_SYS_DEV0_SPACE
  243. #define SRAM_SIZE 0x00100000 /* 1 MB of sram */
  244. #endif
  245. /*-----------------------------------------------------------------------
  246. * PCI stuff
  247. *-----------------------------------------------------------------------
  248. */
  249. #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  250. #define PCI_HOST_FORCE 1 /* configure as pci host */
  251. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  252. #define CONFIG_PCI /* include pci support */
  253. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  254. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  255. /* PCI MEMORY MAP section */
  256. #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
  257. #define CONFIG_SYS_PCI0_MEM_SIZE _128M
  258. #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
  259. #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
  260. #define CONFIG_SYS_PCI1_MEM_SIZE _128M
  261. #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
  262. /* PCI I/O MAP section */
  263. #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
  264. #define CONFIG_SYS_PCI0_IO_SIZE _16M
  265. #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
  266. #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
  267. #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
  268. #define CONFIG_SYS_PCI1_IO_SIZE _16M
  269. #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
  270. #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
  271. /*----------------------------------------------------------------------
  272. * Initial BAT mappings
  273. */
  274. /* NOTES:
  275. * 1) GUARDED and WRITE_THRU not allowed in IBATS
  276. * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
  277. */
  278. /* SDRAM */
  279. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  280. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  281. #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  282. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  283. /* init ram */
  284. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  285. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  286. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  287. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  288. /* PCI0, PCI1 in one BAT */
  289. #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
  290. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  291. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  292. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  293. /* GT regs, bootrom, all the devices, PCI I/O */
  294. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
  295. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
  296. #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  297. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  298. /* I2C speed and slave address (for compatability) defaults */
  299. #define CONFIG_SYS_I2C_SPEED 400000
  300. #define CONFIG_SYS_I2C_SLAVE 0x7F
  301. /* I2C addresses for the two DIMM SPD chips */
  302. #ifndef CONFIG_EVB64260_750CX
  303. #define DIMM0_I2C_ADDR 0x56
  304. #define DIMM1_I2C_ADDR 0x54
  305. #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
  306. #define DIMM0_I2C_ADDR 0x54
  307. #define DIMM1_I2C_ADDR 0x54
  308. #endif
  309. /*
  310. * For booting Linux, the board info and command line data
  311. * have to be in the first 8 MB of memory, since this is
  312. * the maximum mapped by the Linux kernel during initialization.
  313. */
  314. #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
  315. /*-----------------------------------------------------------------------
  316. * FLASH organization
  317. */
  318. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  319. #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
  320. #define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE
  321. #define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */
  322. #define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */
  323. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  324. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  325. #define CONFIG_SYS_FLASH_CFI 1
  326. #define CONFIG_ENV_IS_IN_FLASH 1
  327. #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
  328. #define CONFIG_ENV_SECT_SIZE 0x20000
  329. #define CONFIG_ENV_ADDR 0xFFFE0000
  330. /*-----------------------------------------------------------------------
  331. * Cache Configuration
  332. */
  333. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
  334. #if defined(CONFIG_CMD_KGDB)
  335. #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  336. #endif
  337. /*-----------------------------------------------------------------------
  338. * L2CR setup -- make sure this is right for your board!
  339. * look in include/74xx_7xx.h for the defines used here
  340. */
  341. #define CONFIG_SYS_L2
  342. #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
  343. L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
  344. #define L2_ENABLE (L2_INIT | L2CR_L2E)
  345. #define CONFIG_SYS_BOARD_ASM_INIT 1
  346. #endif /* __CONFIG_H */