smc91111.c 39 KB

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  1. /*------------------------------------------------------------------------
  2. . smc91111.c
  3. . This is a driver for SMSC's 91C111 single-chip Ethernet device.
  4. .
  5. . (C) Copyright 2002
  6. . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. . Rolf Offermanns <rof@sysgo.de>
  8. .
  9. . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
  10. . Developed by Simple Network Magic Corporation (SNMC)
  11. . Copyright (C) 1996 by Erik Stahlman (ES)
  12. .
  13. . This program is free software; you can redistribute it and/or modify
  14. . it under the terms of the GNU General Public License as published by
  15. . the Free Software Foundation; either version 2 of the License, or
  16. . (at your option) any later version.
  17. .
  18. . This program is distributed in the hope that it will be useful,
  19. . but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. . GNU General Public License for more details.
  22. .
  23. . You should have received a copy of the GNU General Public License
  24. . along with this program; if not, write to the Free Software
  25. . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26. .
  27. . Information contained in this file was obtained from the LAN91C111
  28. . manual from SMC. To get a copy, if you really want one, you can find
  29. . information under www.smsc.com.
  30. .
  31. .
  32. . "Features" of the SMC chip:
  33. . Integrated PHY/MAC for 10/100BaseT Operation
  34. . Supports internal and external MII
  35. . Integrated 8K packet memory
  36. . EEPROM interface for configuration
  37. .
  38. . Arguments:
  39. . io = for the base address
  40. . irq = for the IRQ
  41. .
  42. . author:
  43. . Erik Stahlman ( erik@vt.edu )
  44. . Daris A Nevil ( dnevil@snmc.com )
  45. .
  46. .
  47. . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
  48. .
  49. . Sources:
  50. . o SMSC LAN91C111 databook (www.smsc.com)
  51. . o smc9194.c by Erik Stahlman
  52. . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
  53. .
  54. . History:
  55. . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
  56. . 10/17/01 Marco Hasewinkel Modify for DNP/1110
  57. . 07/25/01 Woojung Huh Modify for ADS Bitsy
  58. . 04/25/01 Daris A Nevil Initial public release through SMSC
  59. . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
  60. ----------------------------------------------------------------------------*/
  61. #include <common.h>
  62. #include <command.h>
  63. #include <config.h>
  64. #include "smc91111.h"
  65. #include <net.h>
  66. #ifdef CONFIG_DRIVER_SMC91111
  67. /* Use power-down feature of the chip */
  68. #define POWER_DOWN 0
  69. #define NO_AUTOPROBE
  70. #define SMC_DEBUG 0
  71. #if SMC_DEBUG > 1
  72. static const char version[] =
  73. "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
  74. #endif
  75. /* Autonegotiation timeout in seconds */
  76. #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
  77. #define CONFIG_SMC_AUTONEG_TIMEOUT 10
  78. #endif
  79. /*------------------------------------------------------------------------
  80. .
  81. . Configuration options, for the experienced user to change.
  82. .
  83. -------------------------------------------------------------------------*/
  84. /*
  85. . Wait time for memory to be free. This probably shouldn't be
  86. . tuned that much, as waiting for this means nothing else happens
  87. . in the system
  88. */
  89. #define MEMORY_WAIT_TIME 16
  90. #if (SMC_DEBUG > 2 )
  91. #define PRINTK3(args...) printf(args)
  92. #else
  93. #define PRINTK3(args...)
  94. #endif
  95. #if SMC_DEBUG > 1
  96. #define PRINTK2(args...) printf(args)
  97. #else
  98. #define PRINTK2(args...)
  99. #endif
  100. #ifdef SMC_DEBUG
  101. #define PRINTK(args...) printf(args)
  102. #else
  103. #define PRINTK(args...)
  104. #endif
  105. /*------------------------------------------------------------------------
  106. .
  107. . The internal workings of the driver. If you are changing anything
  108. . here with the SMC stuff, you should have the datasheet and know
  109. . what you are doing.
  110. .
  111. -------------------------------------------------------------------------*/
  112. #define CARDNAME "LAN91C111"
  113. /* Memory sizing constant */
  114. #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
  115. #ifndef CONFIG_SMC91111_BASE
  116. #define CONFIG_SMC91111_BASE 0x20000300
  117. #endif
  118. #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
  119. #define SMC_DEV_NAME "SMC91111"
  120. #define SMC_PHY_ADDR 0x0000
  121. #define SMC_ALLOC_MAX_TRY 5
  122. #define SMC_TX_TIMEOUT 30
  123. #define SMC_PHY_CLOCK_DELAY 1000
  124. #define ETH_ZLEN 60
  125. #ifdef CONFIG_SMC_USE_32_BIT
  126. #define USE_32_BIT 1
  127. #else
  128. #undef USE_32_BIT
  129. #endif
  130. /*-----------------------------------------------------------------
  131. .
  132. . The driver can be entered at any of the following entry points.
  133. .
  134. .------------------------------------------------------------------ */
  135. extern int eth_init(bd_t *bd);
  136. extern void eth_halt(void);
  137. extern int eth_rx(void);
  138. extern int eth_send(volatile void *packet, int length);
  139. /*
  140. . This is called by register_netdev(). It is responsible for
  141. . checking the portlist for the SMC9000 series chipset. If it finds
  142. . one, then it will initialize the device, find the hardware information,
  143. . and sets up the appropriate device parameters.
  144. . NOTE: Interrupts are *OFF* when this procedure is called.
  145. .
  146. . NB:This shouldn't be static since it is referred to externally.
  147. */
  148. int smc_init(void);
  149. /*
  150. . This is called by unregister_netdev(). It is responsible for
  151. . cleaning up before the driver is finally unregistered and discarded.
  152. */
  153. void smc_destructor(void);
  154. /*
  155. . The kernel calls this function when someone wants to use the device,
  156. . typically 'ifconfig ethX up'.
  157. */
  158. static int smc_open(bd_t *bd);
  159. /*
  160. . This is called by the kernel in response to 'ifconfig ethX down'. It
  161. . is responsible for cleaning up everything that the open routine
  162. . does, and maybe putting the card into a powerdown state.
  163. */
  164. static int smc_close(void);
  165. /*
  166. . Configures the PHY through the MII Management interface
  167. */
  168. #ifndef CONFIG_SMC91111_EXT_PHY
  169. static void smc_phy_configure(void);
  170. #endif /* !CONFIG_SMC91111_EXT_PHY */
  171. /*
  172. . This is a separate procedure to handle the receipt of a packet, to
  173. . leave the interrupt code looking slightly cleaner
  174. */
  175. static int smc_rcv(void);
  176. /* See if a MAC address is defined in the current environment. If so use it. If not
  177. . print a warning and set the environment and other globals with the default.
  178. . If an EEPROM is present it really should be consulted.
  179. */
  180. int smc_get_ethaddr(bd_t *bd);
  181. int get_rom_mac(char *v_rom_mac);
  182. /*
  183. ------------------------------------------------------------
  184. .
  185. . Internal routines
  186. .
  187. ------------------------------------------------------------
  188. */
  189. #ifdef CONFIG_SMC_USE_IOFUNCS
  190. /*
  191. * input and output functions
  192. *
  193. * Implemented due to inx,outx macros accessing the device improperly
  194. * and putting the device into an unkown state.
  195. *
  196. * For instance, on Sharp LPD7A400 SDK, affects were chip memory
  197. * could not be free'd (hence the alloc failures), duplicate packets,
  198. * packets being corrupt (shifted) on the wire, etc. Switching to the
  199. * inx,outx functions fixed this problem.
  200. */
  201. static inline word SMC_inw(dword offset);
  202. static inline void SMC_outw(word value, dword offset);
  203. static inline byte SMC_inb(dword offset);
  204. static inline void SMC_outb(byte value, dword offset);
  205. static inline void SMC_insw(dword offset, volatile uchar* buf, dword len);
  206. static inline void SMC_outsw(dword offset, uchar* buf, dword len);
  207. #define barrier() __asm__ __volatile__("": : :"memory")
  208. static inline word SMC_inw(dword offset)
  209. {
  210. word v;
  211. v = *((volatile word*)(SMC_BASE_ADDRESS+offset));
  212. barrier(); *(volatile u32*)(0xc0000000);
  213. return v;
  214. }
  215. static inline void SMC_outw(word value, dword offset)
  216. {
  217. *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value;
  218. barrier(); *(volatile u32*)(0xc0000000);
  219. }
  220. static inline byte SMC_inb(dword offset)
  221. {
  222. word _w;
  223. _w = SMC_inw(offset & ~((dword)1));
  224. return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
  225. }
  226. static inline void SMC_outb(byte value, dword offset)
  227. {
  228. word _w;
  229. _w = SMC_inw(offset & ~((dword)1));
  230. if (offset & 1)
  231. *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff);
  232. else
  233. *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00);
  234. }
  235. static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
  236. {
  237. while (len-- > 0) {
  238. *((word*)buf)++ = SMC_inw(offset);
  239. barrier(); *((volatile u32*)(0xc0000000));
  240. }
  241. }
  242. static inline void SMC_outsw(dword offset, uchar* buf, dword len)
  243. {
  244. while (len-- > 0) {
  245. SMC_outw(*((word*)buf)++, offset);
  246. barrier(); *(volatile u32*)(0xc0000000);
  247. }
  248. }
  249. #endif /* CONFIG_SMC_USE_IOFUNCS */
  250. static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
  251. /*
  252. * This function must be called before smc_open() if you want to override
  253. * the default mac address.
  254. */
  255. void smc_set_mac_addr(const char *addr) {
  256. int i;
  257. for (i=0; i < sizeof(smc_mac_addr); i++){
  258. smc_mac_addr[i] = addr[i];
  259. }
  260. }
  261. /*
  262. * smc_get_macaddr is no longer used. If you want to override the default
  263. * mac address, call smc_get_mac_addr as a part of the board initialization.
  264. */
  265. #if 0
  266. void smc_get_macaddr( byte *addr ) {
  267. /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
  268. unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
  269. int i;
  270. for (i=0; i<6; i++) {
  271. addr[0] = *(dnp1110_mac+0);
  272. addr[1] = *(dnp1110_mac+1);
  273. addr[2] = *(dnp1110_mac+2);
  274. addr[3] = *(dnp1110_mac+3);
  275. addr[4] = *(dnp1110_mac+4);
  276. addr[5] = *(dnp1110_mac+5);
  277. }
  278. }
  279. #endif /* 0 */
  280. /***********************************************
  281. * Show available memory *
  282. ***********************************************/
  283. void dump_memory_info(void)
  284. {
  285. word mem_info;
  286. word old_bank;
  287. old_bank = SMC_inw(BANK_SELECT)&0xF;
  288. SMC_SELECT_BANK(0);
  289. mem_info = SMC_inw( MIR_REG );
  290. PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
  291. SMC_SELECT_BANK(old_bank);
  292. }
  293. /*
  294. . A rather simple routine to print out a packet for debugging purposes.
  295. */
  296. #if SMC_DEBUG > 2
  297. static void print_packet( byte *, int );
  298. #endif
  299. #define tx_done(dev) 1
  300. /* this does a soft reset on the device */
  301. static void smc_reset( void );
  302. /* Enable Interrupts, Receive, and Transmit */
  303. static void smc_enable( void );
  304. /* this puts the device in an inactive state */
  305. static void smc_shutdown( void );
  306. /* Routines to Read and Write the PHY Registers across the
  307. MII Management Interface
  308. */
  309. #ifndef CONFIG_SMC91111_EXT_PHY
  310. static word smc_read_phy_register(byte phyreg);
  311. static void smc_write_phy_register(byte phyreg, word phydata);
  312. #endif /* !CONFIG_SMC91111_EXT_PHY */
  313. static int poll4int (byte mask, int timeout)
  314. {
  315. int tmo = get_timer (0) + timeout * CFG_HZ;
  316. int is_timeout = 0;
  317. word old_bank = SMC_inw (BSR_REG);
  318. PRINTK2 ("Polling...\n");
  319. SMC_SELECT_BANK (2);
  320. while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) {
  321. if (get_timer (0) >= tmo) {
  322. is_timeout = 1;
  323. break;
  324. }
  325. }
  326. /* restore old bank selection */
  327. SMC_SELECT_BANK (old_bank);
  328. if (is_timeout)
  329. return 1;
  330. else
  331. return 0;
  332. }
  333. /* Only one release command at a time, please */
  334. static inline void smc_wait_mmu_release_complete (void)
  335. {
  336. int count = 0;
  337. /* assume bank 2 selected */
  338. while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
  339. udelay (1); /* Wait until not busy */
  340. if (++count > 200)
  341. break;
  342. }
  343. }
  344. /*
  345. . Function: smc_reset( void )
  346. . Purpose:
  347. . This sets the SMC91111 chip to its normal state, hopefully from whatever
  348. . mess that any other DOS driver has put it in.
  349. .
  350. . Maybe I should reset more registers to defaults in here? SOFTRST should
  351. . do that for me.
  352. .
  353. . Method:
  354. . 1. send a SOFT RESET
  355. . 2. wait for it to finish
  356. . 3. enable autorelease mode
  357. . 4. reset the memory management unit
  358. . 5. clear all interrupts
  359. .
  360. */
  361. static void smc_reset (void)
  362. {
  363. PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
  364. /* This resets the registers mostly to defaults, but doesn't
  365. affect EEPROM. That seems unnecessary */
  366. SMC_SELECT_BANK (0);
  367. SMC_outw (RCR_SOFTRST, RCR_REG);
  368. /* Setup the Configuration Register */
  369. /* This is necessary because the CONFIG_REG is not affected */
  370. /* by a soft reset */
  371. SMC_SELECT_BANK (1);
  372. #if defined(CONFIG_SMC91111_EXT_PHY)
  373. SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
  374. #else
  375. SMC_outw (CONFIG_DEFAULT, CONFIG_REG);
  376. #endif
  377. /* Release from possible power-down state */
  378. /* Configuration register is not affected by Soft Reset */
  379. SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG);
  380. SMC_SELECT_BANK (0);
  381. /* this should pause enough for the chip to be happy */
  382. udelay (10);
  383. /* Disable transmit and receive functionality */
  384. SMC_outw (RCR_CLEAR, RCR_REG);
  385. SMC_outw (TCR_CLEAR, TCR_REG);
  386. /* set the control register */
  387. SMC_SELECT_BANK (1);
  388. SMC_outw (CTL_DEFAULT, CTL_REG);
  389. /* Reset the MMU */
  390. SMC_SELECT_BANK (2);
  391. smc_wait_mmu_release_complete ();
  392. SMC_outw (MC_RESET, MMU_CMD_REG);
  393. while (SMC_inw (MMU_CMD_REG) & MC_BUSY)
  394. udelay (1); /* Wait until not busy */
  395. /* Note: It doesn't seem that waiting for the MMU busy is needed here,
  396. but this is a place where future chipsets _COULD_ break. Be wary
  397. of issuing another MMU command right after this */
  398. /* Disable all interrupts */
  399. SMC_outb (0, IM_REG);
  400. }
  401. /*
  402. . Function: smc_enable
  403. . Purpose: let the chip talk to the outside work
  404. . Method:
  405. . 1. Enable the transmitter
  406. . 2. Enable the receiver
  407. . 3. Enable interrupts
  408. */
  409. static void smc_enable()
  410. {
  411. PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
  412. SMC_SELECT_BANK( 0 );
  413. /* see the header file for options in TCR/RCR DEFAULT*/
  414. SMC_outw( TCR_DEFAULT, TCR_REG );
  415. SMC_outw( RCR_DEFAULT, RCR_REG );
  416. /* clear MII_DIS */
  417. /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
  418. }
  419. /*
  420. . Function: smc_shutdown
  421. . Purpose: closes down the SMC91xxx chip.
  422. . Method:
  423. . 1. zero the interrupt mask
  424. . 2. clear the enable receive flag
  425. . 3. clear the enable xmit flags
  426. .
  427. . TODO:
  428. . (1) maybe utilize power down mode.
  429. . Why not yet? Because while the chip will go into power down mode,
  430. . the manual says that it will wake up in response to any I/O requests
  431. . in the register space. Empirical results do not show this working.
  432. */
  433. static void smc_shutdown()
  434. {
  435. PRINTK2(CARDNAME ": smc_shutdown\n");
  436. /* no more interrupts for me */
  437. SMC_SELECT_BANK( 2 );
  438. SMC_outb( 0, IM_REG );
  439. /* and tell the card to stay away from that nasty outside world */
  440. SMC_SELECT_BANK( 0 );
  441. SMC_outb( RCR_CLEAR, RCR_REG );
  442. SMC_outb( TCR_CLEAR, TCR_REG );
  443. }
  444. /*
  445. . Function: smc_hardware_send_packet(struct net_device * )
  446. . Purpose:
  447. . This sends the actual packet to the SMC9xxx chip.
  448. .
  449. . Algorithm:
  450. . First, see if a saved_skb is available.
  451. . ( this should NOT be called if there is no 'saved_skb'
  452. . Now, find the packet number that the chip allocated
  453. . Point the data pointers at it in memory
  454. . Set the length word in the chip's memory
  455. . Dump the packet to chip memory
  456. . Check if a last byte is needed ( odd length packet )
  457. . if so, set the control flag right
  458. . Tell the card to send it
  459. . Enable the transmit interrupt, so I know if it failed
  460. . Free the kernel data if I actually sent it.
  461. */
  462. static int smc_send_packet (volatile void *packet, int packet_length)
  463. {
  464. byte packet_no;
  465. unsigned long ioaddr;
  466. byte *buf;
  467. int length;
  468. int numPages;
  469. int try = 0;
  470. int time_out;
  471. byte status;
  472. byte saved_pnr;
  473. word saved_ptr;
  474. /* save PTR and PNR registers before manipulation */
  475. SMC_SELECT_BANK (2);
  476. saved_pnr = SMC_inb( PN_REG );
  477. saved_ptr = SMC_inw( PTR_REG );
  478. PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
  479. length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
  480. /* allocate memory
  481. ** The MMU wants the number of pages to be the number of 256 bytes
  482. ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
  483. **
  484. ** The 91C111 ignores the size bits, but the code is left intact
  485. ** for backwards and future compatibility.
  486. **
  487. ** Pkt size for allocating is data length +6 (for additional status
  488. ** words, length and ctl!)
  489. **
  490. ** If odd size then last byte is included in this header.
  491. */
  492. numPages = ((length & 0xfffe) + 6);
  493. numPages >>= 8; /* Divide by 256 */
  494. if (numPages > 7) {
  495. printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
  496. return 0;
  497. }
  498. /* now, try to allocate the memory */
  499. SMC_SELECT_BANK (2);
  500. SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG);
  501. /* FIXME: the ALLOC_INT bit never gets set *
  502. * so the following will always give a *
  503. * memory allocation error. *
  504. * same code works in armboot though *
  505. * -ro
  506. */
  507. again:
  508. try++;
  509. time_out = MEMORY_WAIT_TIME;
  510. do {
  511. status = SMC_inb (SMC91111_INT_REG);
  512. if (status & IM_ALLOC_INT) {
  513. /* acknowledge the interrupt */
  514. SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG);
  515. break;
  516. }
  517. } while (--time_out);
  518. if (!time_out) {
  519. PRINTK2 ("%s: memory allocation, try %d failed ...\n",
  520. SMC_DEV_NAME, try);
  521. if (try < SMC_ALLOC_MAX_TRY)
  522. goto again;
  523. else
  524. return 0;
  525. }
  526. PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
  527. SMC_DEV_NAME, try);
  528. /* I can send the packet now.. */
  529. ioaddr = SMC_BASE_ADDRESS;
  530. buf = (byte *) packet;
  531. /* If I get here, I _know_ there is a packet slot waiting for me */
  532. packet_no = SMC_inb (AR_REG);
  533. if (packet_no & AR_FAILED) {
  534. /* or isn't there? BAD CHIP! */
  535. printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
  536. return 0;
  537. }
  538. /* we have a packet address, so tell the card to use it */
  539. #ifndef CONFIG_XAENIAX
  540. SMC_outb (packet_no, PN_REG);
  541. #else
  542. /* On Xaeniax board, we can't use SMC_outb here because that way
  543. * the Allocate MMU command will end up written to the command register
  544. * as well, which will lead to a problem.
  545. */
  546. SMC_outl (packet_no << 16, 0);
  547. #endif
  548. /* do not write new ptr value if Write data fifo not empty */
  549. while ( saved_ptr & PTR_NOTEMPTY )
  550. printf ("Write data fifo not empty!\n");
  551. /* point to the beginning of the packet */
  552. SMC_outw (PTR_AUTOINC, PTR_REG);
  553. PRINTK3 ("%s: Trying to xmit packet of length %x\n",
  554. SMC_DEV_NAME, length);
  555. #if SMC_DEBUG > 2
  556. printf ("Transmitting Packet\n");
  557. print_packet (buf, length);
  558. #endif
  559. /* send the packet length ( +6 for status, length and ctl byte )
  560. and the status word ( set to zeros ) */
  561. #ifdef USE_32_BIT
  562. SMC_outl ((length + 6) << 16, SMC91111_DATA_REG);
  563. #else
  564. SMC_outw (0, SMC91111_DATA_REG);
  565. /* send the packet length ( +6 for status words, length, and ctl */
  566. SMC_outw ((length + 6), SMC91111_DATA_REG);
  567. #endif
  568. /* send the actual data
  569. . I _think_ it's faster to send the longs first, and then
  570. . mop up by sending the last word. It depends heavily
  571. . on alignment, at least on the 486. Maybe it would be
  572. . a good idea to check which is optimal? But that could take
  573. . almost as much time as is saved?
  574. */
  575. #ifdef USE_32_BIT
  576. SMC_outsl (SMC91111_DATA_REG, buf, length >> 2);
  577. if (length & 0x2)
  578. SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
  579. SMC91111_DATA_REG);
  580. #else
  581. SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
  582. #endif /* USE_32_BIT */
  583. /* Send the last byte, if there is one. */
  584. if ((length & 1) == 0) {
  585. SMC_outw (0, SMC91111_DATA_REG);
  586. } else {
  587. SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG);
  588. }
  589. /* and let the chipset deal with it */
  590. SMC_outw (MC_ENQUEUE, MMU_CMD_REG);
  591. /* poll for TX INT */
  592. /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */
  593. /* poll for TX_EMPTY INT - autorelease enabled */
  594. if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
  595. /* sending failed */
  596. PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
  597. /* release packet */
  598. /* no need to release, MMU does that now */
  599. #ifdef CONFIG_XAENIAX
  600. SMC_outw (MC_FREEPKT, MMU_CMD_REG);
  601. #endif
  602. /* wait for MMU getting ready (low) */
  603. while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
  604. udelay (10);
  605. }
  606. PRINTK2 ("MMU ready\n");
  607. return 0;
  608. } else {
  609. /* ack. int */
  610. SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG);
  611. /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
  612. PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
  613. length);
  614. /* release packet */
  615. /* no need to release, MMU does that now */
  616. #ifdef CONFIG_XAENIAX
  617. SMC_outw (MC_FREEPKT, MMU_CMD_REG);
  618. #endif
  619. /* wait for MMU getting ready (low) */
  620. while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
  621. udelay (10);
  622. }
  623. PRINTK2 ("MMU ready\n");
  624. }
  625. /* restore previously saved registers */
  626. #ifndef CONFIG_XAENIAX
  627. SMC_outb( saved_pnr, PN_REG );
  628. #else
  629. /* On Xaeniax board, we can't use SMC_outb here because that way
  630. * the Allocate MMU command will end up written to the command register
  631. * as well, which will lead to a problem.
  632. */
  633. SMC_outl(saved_pnr << 16, 0);
  634. #endif
  635. SMC_outw( saved_ptr, PTR_REG );
  636. return length;
  637. }
  638. /*-------------------------------------------------------------------------
  639. |
  640. | smc_destructor( struct net_device * dev )
  641. | Input parameters:
  642. | dev, pointer to the device structure
  643. |
  644. | Output:
  645. | None.
  646. |
  647. ---------------------------------------------------------------------------
  648. */
  649. void smc_destructor()
  650. {
  651. PRINTK2(CARDNAME ": smc_destructor\n");
  652. }
  653. /*
  654. * Open and Initialize the board
  655. *
  656. * Set up everything, reset the card, etc ..
  657. *
  658. */
  659. static int smc_open (bd_t * bd)
  660. {
  661. int i, err;
  662. PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME);
  663. /* reset the hardware */
  664. smc_reset ();
  665. smc_enable ();
  666. /* Configure the PHY */
  667. #ifndef CONFIG_SMC91111_EXT_PHY
  668. smc_phy_configure ();
  669. #endif
  670. /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
  671. /* SMC_SELECT_BANK(0); */
  672. /* SMC_outw(0, RPC_REG); */
  673. SMC_SELECT_BANK (1);
  674. err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */
  675. if (err < 0) {
  676. memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */
  677. return (-1); /* upper code ignores this, but NOT bi_enetaddr */
  678. }
  679. #ifdef USE_32_BIT
  680. for (i = 0; i < 6; i += 2) {
  681. word address;
  682. address = smc_mac_addr[i + 1] << 8;
  683. address |= smc_mac_addr[i];
  684. SMC_outw (address, (ADDR0_REG + i));
  685. }
  686. #else
  687. for (i = 0; i < 6; i++)
  688. SMC_outb (smc_mac_addr[i], (ADDR0_REG + i));
  689. #endif
  690. return 0;
  691. }
  692. /*-------------------------------------------------------------
  693. .
  694. . smc_rcv - receive a packet from the card
  695. .
  696. . There is ( at least ) a packet waiting to be read from
  697. . chip-memory.
  698. .
  699. . o Read the status
  700. . o If an error, record it
  701. . o otherwise, read in the packet
  702. --------------------------------------------------------------
  703. */
  704. static int smc_rcv()
  705. {
  706. int packet_number;
  707. word status;
  708. word packet_length;
  709. int is_error = 0;
  710. #ifdef USE_32_BIT
  711. dword stat_len;
  712. #endif
  713. byte saved_pnr;
  714. word saved_ptr;
  715. SMC_SELECT_BANK(2);
  716. /* save PTR and PTR registers */
  717. saved_pnr = SMC_inb( PN_REG );
  718. saved_ptr = SMC_inw( PTR_REG );
  719. packet_number = SMC_inw( RXFIFO_REG );
  720. if ( packet_number & RXFIFO_REMPTY ) {
  721. return 0;
  722. }
  723. PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
  724. /* start reading from the start of the packet */
  725. SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
  726. /* First two words are status and packet_length */
  727. #ifdef USE_32_BIT
  728. stat_len = SMC_inl(SMC91111_DATA_REG);
  729. status = stat_len & 0xffff;
  730. packet_length = stat_len >> 16;
  731. #else
  732. status = SMC_inw( SMC91111_DATA_REG );
  733. packet_length = SMC_inw( SMC91111_DATA_REG );
  734. #endif
  735. packet_length &= 0x07ff; /* mask off top bits */
  736. PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
  737. if ( !(status & RS_ERRORS ) ){
  738. /* Adjust for having already read the first two words */
  739. packet_length -= 4; /*4; */
  740. /* set odd length for bug in LAN91C111, */
  741. /* which never sets RS_ODDFRAME */
  742. /* TODO ? */
  743. #ifdef USE_32_BIT
  744. PRINTK3(" Reading %d dwords (and %d bytes) \n",
  745. packet_length >> 2, packet_length & 3 );
  746. /* QUESTION: Like in the TX routine, do I want
  747. to send the DWORDs or the bytes first, or some
  748. mixture. A mixture might improve already slow PIO
  749. performance */
  750. SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
  751. /* read the left over bytes */
  752. if (packet_length & 3) {
  753. int i;
  754. byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
  755. dword leftover = SMC_inl(SMC91111_DATA_REG);
  756. for (i=0; i<(packet_length & 3); i++)
  757. *tail++ = (byte) (leftover >> (8*i)) & 0xff;
  758. }
  759. #else
  760. PRINTK3(" Reading %d words and %d byte(s) \n",
  761. (packet_length >> 1 ), packet_length & 1 );
  762. SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
  763. #endif /* USE_32_BIT */
  764. #if SMC_DEBUG > 2
  765. printf("Receiving Packet\n");
  766. print_packet( NetRxPackets[0], packet_length );
  767. #endif
  768. } else {
  769. /* error ... */
  770. /* TODO ? */
  771. is_error = 1;
  772. }
  773. while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
  774. udelay(1); /* Wait until not busy */
  775. /* error or good, tell the card to get rid of this packet */
  776. SMC_outw( MC_RELEASE, MMU_CMD_REG );
  777. while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
  778. udelay(1); /* Wait until not busy */
  779. /* restore saved registers */
  780. #ifndef CONFIG_XAENIAX
  781. SMC_outb( saved_pnr, PN_REG );
  782. #else
  783. /* On Xaeniax board, we can't use SMC_outb here because that way
  784. * the Allocate MMU command will end up written to the command register
  785. * as well, which will lead to a problem.
  786. */
  787. SMC_outl( saved_pnr << 16, 0);
  788. #endif
  789. SMC_outw( saved_ptr, PTR_REG );
  790. if (!is_error) {
  791. /* Pass the packet up to the protocol layers. */
  792. NetReceive(NetRxPackets[0], packet_length);
  793. return packet_length;
  794. } else {
  795. return 0;
  796. }
  797. }
  798. /*----------------------------------------------------
  799. . smc_close
  800. .
  801. . this makes the board clean up everything that it can
  802. . and not talk to the outside world. Caused by
  803. . an 'ifconfig ethX down'
  804. .
  805. -----------------------------------------------------*/
  806. static int smc_close()
  807. {
  808. PRINTK2("%s: smc_close\n", SMC_DEV_NAME);
  809. /* clear everything */
  810. smc_shutdown();
  811. return 0;
  812. }
  813. #if 0
  814. /*------------------------------------------------------------
  815. . Modify a bit in the LAN91C111 register set
  816. .-------------------------------------------------------------*/
  817. static word smc_modify_regbit(int bank, int ioaddr, int reg,
  818. unsigned int bit, int val)
  819. {
  820. word regval;
  821. SMC_SELECT_BANK( bank );
  822. regval = SMC_inw( reg );
  823. if (val)
  824. regval |= bit;
  825. else
  826. regval &= ~bit;
  827. SMC_outw( regval, 0 );
  828. return(regval);
  829. }
  830. /*------------------------------------------------------------
  831. . Retrieve a bit in the LAN91C111 register set
  832. .-------------------------------------------------------------*/
  833. static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
  834. {
  835. SMC_SELECT_BANK( bank );
  836. if ( SMC_inw( reg ) & bit)
  837. return(1);
  838. else
  839. return(0);
  840. }
  841. /*------------------------------------------------------------
  842. . Modify a LAN91C111 register (word access only)
  843. .-------------------------------------------------------------*/
  844. static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
  845. {
  846. SMC_SELECT_BANK( bank );
  847. SMC_outw( val, reg );
  848. }
  849. /*------------------------------------------------------------
  850. . Retrieve a LAN91C111 register (word access only)
  851. .-------------------------------------------------------------*/
  852. static int smc_get_reg(int bank, int ioaddr, int reg)
  853. {
  854. SMC_SELECT_BANK( bank );
  855. return(SMC_inw( reg ));
  856. }
  857. #endif /* 0 */
  858. /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
  859. #if (SMC_DEBUG > 2 )
  860. /*------------------------------------------------------------
  861. . Debugging function for viewing MII Management serial bitstream
  862. .-------------------------------------------------------------*/
  863. static void smc_dump_mii_stream (byte * bits, int size)
  864. {
  865. int i;
  866. printf ("BIT#:");
  867. for (i = 0; i < size; ++i) {
  868. printf ("%d", i % 10);
  869. }
  870. printf ("\nMDOE:");
  871. for (i = 0; i < size; ++i) {
  872. if (bits[i] & MII_MDOE)
  873. printf ("1");
  874. else
  875. printf ("0");
  876. }
  877. printf ("\nMDO :");
  878. for (i = 0; i < size; ++i) {
  879. if (bits[i] & MII_MDO)
  880. printf ("1");
  881. else
  882. printf ("0");
  883. }
  884. printf ("\nMDI :");
  885. for (i = 0; i < size; ++i) {
  886. if (bits[i] & MII_MDI)
  887. printf ("1");
  888. else
  889. printf ("0");
  890. }
  891. printf ("\n");
  892. }
  893. #endif
  894. /*------------------------------------------------------------
  895. . Reads a register from the MII Management serial interface
  896. .-------------------------------------------------------------*/
  897. #ifndef CONFIG_SMC91111_EXT_PHY
  898. static word smc_read_phy_register (byte phyreg)
  899. {
  900. int oldBank;
  901. int i;
  902. byte mask;
  903. word mii_reg;
  904. byte bits[64];
  905. int clk_idx = 0;
  906. int input_idx;
  907. word phydata;
  908. byte phyaddr = SMC_PHY_ADDR;
  909. /* 32 consecutive ones on MDO to establish sync */
  910. for (i = 0; i < 32; ++i)
  911. bits[clk_idx++] = MII_MDOE | MII_MDO;
  912. /* Start code <01> */
  913. bits[clk_idx++] = MII_MDOE;
  914. bits[clk_idx++] = MII_MDOE | MII_MDO;
  915. /* Read command <10> */
  916. bits[clk_idx++] = MII_MDOE | MII_MDO;
  917. bits[clk_idx++] = MII_MDOE;
  918. /* Output the PHY address, msb first */
  919. mask = (byte) 0x10;
  920. for (i = 0; i < 5; ++i) {
  921. if (phyaddr & mask)
  922. bits[clk_idx++] = MII_MDOE | MII_MDO;
  923. else
  924. bits[clk_idx++] = MII_MDOE;
  925. /* Shift to next lowest bit */
  926. mask >>= 1;
  927. }
  928. /* Output the phy register number, msb first */
  929. mask = (byte) 0x10;
  930. for (i = 0; i < 5; ++i) {
  931. if (phyreg & mask)
  932. bits[clk_idx++] = MII_MDOE | MII_MDO;
  933. else
  934. bits[clk_idx++] = MII_MDOE;
  935. /* Shift to next lowest bit */
  936. mask >>= 1;
  937. }
  938. /* Tristate and turnaround (2 bit times) */
  939. bits[clk_idx++] = 0;
  940. /*bits[clk_idx++] = 0; */
  941. /* Input starts at this bit time */
  942. input_idx = clk_idx;
  943. /* Will input 16 bits */
  944. for (i = 0; i < 16; ++i)
  945. bits[clk_idx++] = 0;
  946. /* Final clock bit */
  947. bits[clk_idx++] = 0;
  948. /* Save the current bank */
  949. oldBank = SMC_inw (BANK_SELECT);
  950. /* Select bank 3 */
  951. SMC_SELECT_BANK (3);
  952. /* Get the current MII register value */
  953. mii_reg = SMC_inw (MII_REG);
  954. /* Turn off all MII Interface bits */
  955. mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
  956. /* Clock all 64 cycles */
  957. for (i = 0; i < sizeof bits; ++i) {
  958. /* Clock Low - output data */
  959. SMC_outw (mii_reg | bits[i], MII_REG);
  960. udelay (SMC_PHY_CLOCK_DELAY);
  961. /* Clock Hi - input data */
  962. SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
  963. udelay (SMC_PHY_CLOCK_DELAY);
  964. bits[i] |= SMC_inw (MII_REG) & MII_MDI;
  965. }
  966. /* Return to idle state */
  967. /* Set clock to low, data to low, and output tristated */
  968. SMC_outw (mii_reg, MII_REG);
  969. udelay (SMC_PHY_CLOCK_DELAY);
  970. /* Restore original bank select */
  971. SMC_SELECT_BANK (oldBank);
  972. /* Recover input data */
  973. phydata = 0;
  974. for (i = 0; i < 16; ++i) {
  975. phydata <<= 1;
  976. if (bits[input_idx++] & MII_MDI)
  977. phydata |= 0x0001;
  978. }
  979. #if (SMC_DEBUG > 2 )
  980. printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
  981. phyaddr, phyreg, phydata);
  982. smc_dump_mii_stream (bits, sizeof bits);
  983. #endif
  984. return (phydata);
  985. }
  986. /*------------------------------------------------------------
  987. . Writes a register to the MII Management serial interface
  988. .-------------------------------------------------------------*/
  989. static void smc_write_phy_register (byte phyreg, word phydata)
  990. {
  991. int oldBank;
  992. int i;
  993. word mask;
  994. word mii_reg;
  995. byte bits[65];
  996. int clk_idx = 0;
  997. byte phyaddr = SMC_PHY_ADDR;
  998. /* 32 consecutive ones on MDO to establish sync */
  999. for (i = 0; i < 32; ++i)
  1000. bits[clk_idx++] = MII_MDOE | MII_MDO;
  1001. /* Start code <01> */
  1002. bits[clk_idx++] = MII_MDOE;
  1003. bits[clk_idx++] = MII_MDOE | MII_MDO;
  1004. /* Write command <01> */
  1005. bits[clk_idx++] = MII_MDOE;
  1006. bits[clk_idx++] = MII_MDOE | MII_MDO;
  1007. /* Output the PHY address, msb first */
  1008. mask = (byte) 0x10;
  1009. for (i = 0; i < 5; ++i) {
  1010. if (phyaddr & mask)
  1011. bits[clk_idx++] = MII_MDOE | MII_MDO;
  1012. else
  1013. bits[clk_idx++] = MII_MDOE;
  1014. /* Shift to next lowest bit */
  1015. mask >>= 1;
  1016. }
  1017. /* Output the phy register number, msb first */
  1018. mask = (byte) 0x10;
  1019. for (i = 0; i < 5; ++i) {
  1020. if (phyreg & mask)
  1021. bits[clk_idx++] = MII_MDOE | MII_MDO;
  1022. else
  1023. bits[clk_idx++] = MII_MDOE;
  1024. /* Shift to next lowest bit */
  1025. mask >>= 1;
  1026. }
  1027. /* Tristate and turnaround (2 bit times) */
  1028. bits[clk_idx++] = 0;
  1029. bits[clk_idx++] = 0;
  1030. /* Write out 16 bits of data, msb first */
  1031. mask = 0x8000;
  1032. for (i = 0; i < 16; ++i) {
  1033. if (phydata & mask)
  1034. bits[clk_idx++] = MII_MDOE | MII_MDO;
  1035. else
  1036. bits[clk_idx++] = MII_MDOE;
  1037. /* Shift to next lowest bit */
  1038. mask >>= 1;
  1039. }
  1040. /* Final clock bit (tristate) */
  1041. bits[clk_idx++] = 0;
  1042. /* Save the current bank */
  1043. oldBank = SMC_inw (BANK_SELECT);
  1044. /* Select bank 3 */
  1045. SMC_SELECT_BANK (3);
  1046. /* Get the current MII register value */
  1047. mii_reg = SMC_inw (MII_REG);
  1048. /* Turn off all MII Interface bits */
  1049. mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
  1050. /* Clock all cycles */
  1051. for (i = 0; i < sizeof bits; ++i) {
  1052. /* Clock Low - output data */
  1053. SMC_outw (mii_reg | bits[i], MII_REG);
  1054. udelay (SMC_PHY_CLOCK_DELAY);
  1055. /* Clock Hi - input data */
  1056. SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
  1057. udelay (SMC_PHY_CLOCK_DELAY);
  1058. bits[i] |= SMC_inw (MII_REG) & MII_MDI;
  1059. }
  1060. /* Return to idle state */
  1061. /* Set clock to low, data to low, and output tristated */
  1062. SMC_outw (mii_reg, MII_REG);
  1063. udelay (SMC_PHY_CLOCK_DELAY);
  1064. /* Restore original bank select */
  1065. SMC_SELECT_BANK (oldBank);
  1066. #if (SMC_DEBUG > 2 )
  1067. printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
  1068. phyaddr, phyreg, phydata);
  1069. smc_dump_mii_stream (bits, sizeof bits);
  1070. #endif
  1071. }
  1072. #endif /* !CONFIG_SMC91111_EXT_PHY */
  1073. /*------------------------------------------------------------
  1074. . Waits the specified number of milliseconds - kernel friendly
  1075. .-------------------------------------------------------------*/
  1076. #ifndef CONFIG_SMC91111_EXT_PHY
  1077. static void smc_wait_ms(unsigned int ms)
  1078. {
  1079. udelay(ms*1000);
  1080. }
  1081. #endif /* !CONFIG_SMC91111_EXT_PHY */
  1082. /*------------------------------------------------------------
  1083. . Configures the specified PHY using Autonegotiation. Calls
  1084. . smc_phy_fixed() if the user has requested a certain config.
  1085. .-------------------------------------------------------------*/
  1086. #ifndef CONFIG_SMC91111_EXT_PHY
  1087. static void smc_phy_configure ()
  1088. {
  1089. int timeout;
  1090. byte phyaddr;
  1091. word my_phy_caps; /* My PHY capabilities */
  1092. word my_ad_caps; /* My Advertised capabilities */
  1093. word status = 0; /*;my status = 0 */
  1094. int failed = 0;
  1095. PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
  1096. /* Get the detected phy address */
  1097. phyaddr = SMC_PHY_ADDR;
  1098. /* Reset the PHY, setting all other bits to zero */
  1099. smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST);
  1100. /* Wait for the reset to complete, or time out */
  1101. timeout = 6; /* Wait up to 3 seconds */
  1102. while (timeout--) {
  1103. if (!(smc_read_phy_register (PHY_CNTL_REG)
  1104. & PHY_CNTL_RST)) {
  1105. /* reset complete */
  1106. break;
  1107. }
  1108. smc_wait_ms (500); /* wait 500 millisecs */
  1109. }
  1110. if (timeout < 1) {
  1111. printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
  1112. goto smc_phy_configure_exit;
  1113. }
  1114. /* Read PHY Register 18, Status Output */
  1115. /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
  1116. /* Enable PHY Interrupts (for register 18) */
  1117. /* Interrupts listed here are disabled */
  1118. smc_write_phy_register (PHY_MASK_REG, 0xffff);
  1119. /* Configure the Receive/Phy Control register */
  1120. SMC_SELECT_BANK (0);
  1121. SMC_outw (RPC_DEFAULT, RPC_REG);
  1122. /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
  1123. my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
  1124. my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
  1125. if (my_phy_caps & PHY_STAT_CAP_T4)
  1126. my_ad_caps |= PHY_AD_T4;
  1127. if (my_phy_caps & PHY_STAT_CAP_TXF)
  1128. my_ad_caps |= PHY_AD_TX_FDX;
  1129. if (my_phy_caps & PHY_STAT_CAP_TXH)
  1130. my_ad_caps |= PHY_AD_TX_HDX;
  1131. if (my_phy_caps & PHY_STAT_CAP_TF)
  1132. my_ad_caps |= PHY_AD_10_FDX;
  1133. if (my_phy_caps & PHY_STAT_CAP_TH)
  1134. my_ad_caps |= PHY_AD_10_HDX;
  1135. /* Update our Auto-Neg Advertisement Register */
  1136. smc_write_phy_register (PHY_AD_REG, my_ad_caps);
  1137. /* Read the register back. Without this, it appears that when */
  1138. /* auto-negotiation is restarted, sometimes it isn't ready and */
  1139. /* the link does not come up. */
  1140. smc_read_phy_register(PHY_AD_REG);
  1141. PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
  1142. PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
  1143. /* Restart auto-negotiation process in order to advertise my caps */
  1144. smc_write_phy_register (PHY_CNTL_REG,
  1145. PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
  1146. /* Wait for the auto-negotiation to complete. This may take from */
  1147. /* 2 to 3 seconds. */
  1148. /* Wait for the reset to complete, or time out */
  1149. timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
  1150. while (timeout--) {
  1151. status = smc_read_phy_register (PHY_STAT_REG);
  1152. if (status & PHY_STAT_ANEG_ACK) {
  1153. /* auto-negotiate complete */
  1154. break;
  1155. }
  1156. smc_wait_ms (500); /* wait 500 millisecs */
  1157. /* Restart auto-negotiation if remote fault */
  1158. if (status & PHY_STAT_REM_FLT) {
  1159. printf ("%s: PHY remote fault detected\n",
  1160. SMC_DEV_NAME);
  1161. /* Restart auto-negotiation */
  1162. printf ("%s: PHY restarting auto-negotiation\n",
  1163. SMC_DEV_NAME);
  1164. smc_write_phy_register (PHY_CNTL_REG,
  1165. PHY_CNTL_ANEG_EN |
  1166. PHY_CNTL_ANEG_RST |
  1167. PHY_CNTL_SPEED |
  1168. PHY_CNTL_DPLX);
  1169. }
  1170. }
  1171. if (timeout < 1) {
  1172. printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
  1173. failed = 1;
  1174. }
  1175. /* Fail if we detected an auto-negotiate remote fault */
  1176. if (status & PHY_STAT_REM_FLT) {
  1177. printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
  1178. failed = 1;
  1179. }
  1180. /* Re-Configure the Receive/Phy Control register */
  1181. SMC_outw (RPC_DEFAULT, RPC_REG);
  1182. smc_phy_configure_exit: ;
  1183. }
  1184. #endif /* !CONFIG_SMC91111_EXT_PHY */
  1185. #if SMC_DEBUG > 2
  1186. static void print_packet( byte * buf, int length )
  1187. {
  1188. int i;
  1189. int remainder;
  1190. int lines;
  1191. printf("Packet of length %d \n", length );
  1192. #if SMC_DEBUG > 3
  1193. lines = length / 16;
  1194. remainder = length % 16;
  1195. for ( i = 0; i < lines ; i ++ ) {
  1196. int cur;
  1197. for ( cur = 0; cur < 8; cur ++ ) {
  1198. byte a, b;
  1199. a = *(buf ++ );
  1200. b = *(buf ++ );
  1201. printf("%02x%02x ", a, b );
  1202. }
  1203. printf("\n");
  1204. }
  1205. for ( i = 0; i < remainder/2 ; i++ ) {
  1206. byte a, b;
  1207. a = *(buf ++ );
  1208. b = *(buf ++ );
  1209. printf("%02x%02x ", a, b );
  1210. }
  1211. printf("\n");
  1212. #endif
  1213. }
  1214. #endif
  1215. int eth_init(bd_t *bd) {
  1216. return (smc_open(bd));
  1217. }
  1218. void eth_halt() {
  1219. smc_close();
  1220. }
  1221. int eth_rx() {
  1222. return smc_rcv();
  1223. }
  1224. int eth_send(volatile void *packet, int length) {
  1225. return smc_send_packet(packet, length);
  1226. }
  1227. int smc_get_ethaddr (bd_t * bd)
  1228. {
  1229. int env_size, rom_valid, env_present = 0, reg;
  1230. char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66";
  1231. uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6];
  1232. env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
  1233. if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */
  1234. printf ("\n*** ERROR: ethaddr is not set properly!!\n");
  1235. return (-1);
  1236. }
  1237. if (env_size > 0) {
  1238. env_present = 1;
  1239. s = s_env_mac;
  1240. }
  1241. for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */
  1242. v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0;
  1243. if (s)
  1244. s = (*e) ? e + 1 : e;
  1245. }
  1246. rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */
  1247. if (!env_present) { /* if NO env */
  1248. if (rom_valid) { /* but ROM is valid */
  1249. v_mac = v_rom_mac;
  1250. sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
  1251. v_mac[0], v_mac[1], v_mac[2], v_mac[3],
  1252. v_mac[4], v_mac[5]);
  1253. setenv ("ethaddr", s_env_mac);
  1254. } else { /* no env, bad ROM */
  1255. printf ("\n*** ERROR: ethaddr is NOT set !!\n");
  1256. return (-1);
  1257. }
  1258. } else { /* good env, don't care ROM */
  1259. v_mac = v_env_mac; /* always use a good env over a ROM */
  1260. }
  1261. if (env_present && rom_valid) { /* if both env and ROM are good */
  1262. if (memcmp (v_env_mac, v_rom_mac, 6) != 0) {
  1263. printf ("\nWarning: MAC addresses don't match:\n");
  1264. printf ("\tHW MAC address: "
  1265. "%02X:%02X:%02X:%02X:%02X:%02X\n",
  1266. v_rom_mac[0], v_rom_mac[1],
  1267. v_rom_mac[2], v_rom_mac[3],
  1268. v_rom_mac[4], v_rom_mac[5] );
  1269. printf ("\t\"ethaddr\" value: "
  1270. "%02X:%02X:%02X:%02X:%02X:%02X\n",
  1271. v_env_mac[0], v_env_mac[1],
  1272. v_env_mac[2], v_env_mac[3],
  1273. v_env_mac[4], v_env_mac[5]) ;
  1274. debug ("### Set MAC addr from environment\n");
  1275. }
  1276. }
  1277. memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */
  1278. smc_set_mac_addr (v_mac); /* use old function to update smc default */
  1279. PRINTK("Using MAC Address %02X:%02X:%02X:%02X:%02X:%02X\n", v_mac[0], v_mac[1],
  1280. v_mac[2], v_mac[3], v_mac[4], v_mac[5]);
  1281. return (0);
  1282. }
  1283. int get_rom_mac (char *v_rom_mac)
  1284. {
  1285. #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
  1286. char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
  1287. memcpy (v_rom_mac, hw_mac_addr, 6);
  1288. return (1);
  1289. #else
  1290. int i;
  1291. int valid_mac = 0;
  1292. SMC_SELECT_BANK (1);
  1293. for (i=0; i<6; i++)
  1294. {
  1295. v_rom_mac[i] = SMC_inb ((ADDR0_REG + i));
  1296. valid_mac |= v_rom_mac[i];
  1297. }
  1298. return (valid_mac ? 1 : 0);
  1299. #endif
  1300. }
  1301. #endif /* CONFIG_DRIVER_SMC91111 */