kirkwood_i2c.c 12 KB

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  1. /*
  2. * Driver for the i2c controller on the Marvell line of host bridges
  3. * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, Orion SoC family),
  4. * and Kirkwood family.
  5. *
  6. * Based on:
  7. * Author: Mark A. Greer <mgreer@mvista.com>
  8. *
  9. * 2005 (c) MontaVista, Software, Inc. This file is licensed under
  10. * the terms of the GNU General Public License version 2. This program
  11. * is licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. *
  14. * ported from Linux to u-boot
  15. * (C) Copyright 2009
  16. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  17. *
  18. */
  19. #include <common.h>
  20. #include <i2c.h>
  21. #include <asm/arch/kirkwood.h>
  22. #include <asm/errno.h>
  23. #include <asm/io.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
  26. #if defined(CONFIG_I2C_MUX)
  27. static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0;
  28. #endif
  29. /* Register defines */
  30. #define KW_I2C_REG_SLAVE_ADDR 0x00
  31. #define KW_I2C_REG_DATA 0x04
  32. #define KW_I2C_REG_CONTROL 0x08
  33. #define KW_I2C_REG_STATUS 0x0c
  34. #define KW_I2C_REG_BAUD 0x0c
  35. #define KW_I2C_REG_EXT_SLAVE_ADDR 0x10
  36. #define KW_I2C_REG_SOFT_RESET 0x1c
  37. #define KW_I2C_REG_CONTROL_ACK 0x00000004
  38. #define KW_I2C_REG_CONTROL_IFLG 0x00000008
  39. #define KW_I2C_REG_CONTROL_STOP 0x00000010
  40. #define KW_I2C_REG_CONTROL_START 0x00000020
  41. #define KW_I2C_REG_CONTROL_TWSIEN 0x00000040
  42. #define KW_I2C_REG_CONTROL_INTEN 0x00000080
  43. /* Ctlr status values */
  44. #define KW_I2C_STATUS_BUS_ERR 0x00
  45. #define KW_I2C_STATUS_MAST_START 0x08
  46. #define KW_I2C_STATUS_MAST_REPEAT_START 0x10
  47. #define KW_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
  48. #define KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
  49. #define KW_I2C_STATUS_MAST_WR_ACK 0x28
  50. #define KW_I2C_STATUS_MAST_WR_NO_ACK 0x30
  51. #define KW_I2C_STATUS_MAST_LOST_ARB 0x38
  52. #define KW_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
  53. #define KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
  54. #define KW_I2C_STATUS_MAST_RD_DATA_ACK 0x50
  55. #define KW_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
  56. #define KW_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
  57. #define KW_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
  58. #define KW_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
  59. #define KW_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
  60. #define KW_I2C_STATUS_NO_STATUS 0xf8
  61. /* Driver states */
  62. enum {
  63. KW_I2C_STATE_INVALID,
  64. KW_I2C_STATE_IDLE,
  65. KW_I2C_STATE_WAITING_FOR_START_COND,
  66. KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
  67. KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
  68. KW_I2C_STATE_WAITING_FOR_SLAVE_ACK,
  69. KW_I2C_STATE_WAITING_FOR_SLAVE_DATA,
  70. };
  71. /* Driver actions */
  72. enum {
  73. KW_I2C_ACTION_INVALID,
  74. KW_I2C_ACTION_CONTINUE,
  75. KW_I2C_ACTION_SEND_START,
  76. KW_I2C_ACTION_SEND_ADDR_1,
  77. KW_I2C_ACTION_SEND_ADDR_2,
  78. KW_I2C_ACTION_SEND_DATA,
  79. KW_I2C_ACTION_RCV_DATA,
  80. KW_I2C_ACTION_RCV_DATA_STOP,
  81. KW_I2C_ACTION_SEND_STOP,
  82. };
  83. /* defines to get compatible with Linux driver */
  84. #define IRQ_NONE 0x0
  85. #define IRQ_HANDLED 0x01
  86. #define I2C_M_TEN 0x01
  87. #define I2C_M_RD 0x02
  88. #define I2C_M_REV_DIR_ADDR 0x04;
  89. struct i2c_msg {
  90. u32 addr;
  91. u32 flags;
  92. u8 *buf;
  93. u32 len;
  94. };
  95. struct kirkwood_i2c_data {
  96. int irq;
  97. u32 state;
  98. u32 action;
  99. u32 aborting;
  100. u32 cntl_bits;
  101. void *reg_base;
  102. u32 reg_base_p;
  103. u32 reg_size;
  104. u32 addr1;
  105. u32 addr2;
  106. u32 bytes_left;
  107. u32 byte_posn;
  108. u32 block;
  109. int rc;
  110. u32 freq_m;
  111. u32 freq_n;
  112. struct i2c_msg *msg;
  113. };
  114. static struct kirkwood_i2c_data __drv_data __attribute__ ((section (".data")));
  115. static struct kirkwood_i2c_data *drv_data = &__drv_data;
  116. static struct i2c_msg __i2c_msg __attribute__ ((section (".data")));
  117. static struct i2c_msg *kirkwood_i2c_msg = &__i2c_msg;
  118. /*
  119. *****************************************************************************
  120. *
  121. * Finite State Machine & Interrupt Routines
  122. *
  123. *****************************************************************************
  124. */
  125. static inline int abs(int n)
  126. {
  127. if(n >= 0)
  128. return n;
  129. else
  130. return n * -1;
  131. }
  132. static void kirkwood_calculate_speed(int speed)
  133. {
  134. int calcspeed;
  135. int diff;
  136. int best_diff = CONFIG_SYS_TCLK;
  137. int best_speed = 0;
  138. int m, n;
  139. int tmp[8] = {2, 4, 8, 16, 32, 64, 128, 256};
  140. for (n = 0; n < 8; n++) {
  141. for (m = 0; m < 16; m++) {
  142. calcspeed = CONFIG_SYS_TCLK / (10 * (m + 1) * tmp[n]);
  143. diff = abs((speed - calcspeed));
  144. if ( diff < best_diff) {
  145. best_diff = diff;
  146. best_speed = calcspeed;
  147. drv_data->freq_m = m;
  148. drv_data->freq_n = n;
  149. }
  150. }
  151. }
  152. }
  153. /* Reset hardware and initialize FSM */
  154. static void
  155. kirkwood_i2c_hw_init(int speed, int slaveadd)
  156. {
  157. drv_data->state = KW_I2C_STATE_IDLE;
  158. kirkwood_calculate_speed(speed);
  159. writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SOFT_RESET);
  160. writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
  161. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_BAUD);
  162. writel(slaveadd, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SLAVE_ADDR);
  163. writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_EXT_SLAVE_ADDR);
  164. writel(KW_I2C_REG_CONTROL_TWSIEN | KW_I2C_REG_CONTROL_STOP,
  165. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  166. }
  167. static void
  168. kirkwood_i2c_fsm(u32 status)
  169. {
  170. /*
  171. * If state is idle, then this is likely the remnants of an old
  172. * operation that driver has given up on or the user has killed.
  173. * If so, issue the stop condition and go to idle.
  174. */
  175. if (drv_data->state == KW_I2C_STATE_IDLE) {
  176. drv_data->action = KW_I2C_ACTION_SEND_STOP;
  177. return;
  178. }
  179. /* The status from the ctlr [mostly] tells us what to do next */
  180. switch (status) {
  181. /* Start condition interrupt */
  182. case KW_I2C_STATUS_MAST_START: /* 0x08 */
  183. case KW_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
  184. drv_data->action = KW_I2C_ACTION_SEND_ADDR_1;
  185. drv_data->state = KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
  186. break;
  187. /* Performing a write */
  188. case KW_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
  189. if (drv_data->msg->flags & I2C_M_TEN) {
  190. drv_data->action = KW_I2C_ACTION_SEND_ADDR_2;
  191. drv_data->state =
  192. KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
  193. break;
  194. }
  195. /* FALLTHRU */
  196. case KW_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
  197. case KW_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
  198. if ((drv_data->bytes_left == 0)
  199. || (drv_data->aborting
  200. && (drv_data->byte_posn != 0))) {
  201. drv_data->action = KW_I2C_ACTION_SEND_STOP;
  202. drv_data->state = KW_I2C_STATE_IDLE;
  203. } else {
  204. drv_data->action = KW_I2C_ACTION_SEND_DATA;
  205. drv_data->state =
  206. KW_I2C_STATE_WAITING_FOR_SLAVE_ACK;
  207. drv_data->bytes_left--;
  208. }
  209. break;
  210. /* Performing a read */
  211. case KW_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
  212. if (drv_data->msg->flags & I2C_M_TEN) {
  213. drv_data->action = KW_I2C_ACTION_SEND_ADDR_2;
  214. drv_data->state =
  215. KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
  216. break;
  217. }
  218. /* FALLTHRU */
  219. case KW_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
  220. if (drv_data->bytes_left == 0) {
  221. drv_data->action = KW_I2C_ACTION_SEND_STOP;
  222. drv_data->state = KW_I2C_STATE_IDLE;
  223. break;
  224. }
  225. /* FALLTHRU */
  226. case KW_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
  227. if (status != KW_I2C_STATUS_MAST_RD_DATA_ACK)
  228. drv_data->action = KW_I2C_ACTION_CONTINUE;
  229. else {
  230. drv_data->action = KW_I2C_ACTION_RCV_DATA;
  231. drv_data->bytes_left--;
  232. }
  233. drv_data->state = KW_I2C_STATE_WAITING_FOR_SLAVE_DATA;
  234. if ((drv_data->bytes_left == 1) || drv_data->aborting)
  235. drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_ACK;
  236. break;
  237. case KW_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
  238. drv_data->action = KW_I2C_ACTION_RCV_DATA_STOP;
  239. drv_data->state = KW_I2C_STATE_IDLE;
  240. break;
  241. case KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
  242. case KW_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
  243. case KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
  244. /* Doesn't seem to be a device at other end */
  245. drv_data->action = KW_I2C_ACTION_SEND_STOP;
  246. drv_data->state = KW_I2C_STATE_IDLE;
  247. drv_data->rc = -ENODEV;
  248. break;
  249. default:
  250. printf("kirkwood_i2c_fsm: Ctlr Error -- state: 0x%x, "
  251. "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
  252. drv_data->state, status, drv_data->msg->addr,
  253. drv_data->msg->flags);
  254. drv_data->action = KW_I2C_ACTION_SEND_STOP;
  255. kirkwood_i2c_hw_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  256. drv_data->rc = -EIO;
  257. }
  258. }
  259. static void
  260. kirkwood_i2c_do_action(void)
  261. {
  262. switch(drv_data->action) {
  263. case KW_I2C_ACTION_CONTINUE:
  264. writel(drv_data->cntl_bits,
  265. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  266. break;
  267. case KW_I2C_ACTION_SEND_START:
  268. writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_START,
  269. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  270. break;
  271. case KW_I2C_ACTION_SEND_ADDR_1:
  272. writel(drv_data->addr1,
  273. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
  274. writel(drv_data->cntl_bits,
  275. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  276. break;
  277. case KW_I2C_ACTION_SEND_ADDR_2:
  278. writel(drv_data->addr2,
  279. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
  280. writel(drv_data->cntl_bits,
  281. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  282. break;
  283. case KW_I2C_ACTION_SEND_DATA:
  284. writel(drv_data->msg->buf[drv_data->byte_posn++],
  285. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
  286. writel(drv_data->cntl_bits,
  287. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  288. break;
  289. case KW_I2C_ACTION_RCV_DATA:
  290. drv_data->msg->buf[drv_data->byte_posn++] =
  291. readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
  292. writel(drv_data->cntl_bits,
  293. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  294. break;
  295. case KW_I2C_ACTION_RCV_DATA_STOP:
  296. drv_data->msg->buf[drv_data->byte_posn++] =
  297. readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA);
  298. drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN;
  299. writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP,
  300. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  301. drv_data->block = 0;
  302. break;
  303. case KW_I2C_ACTION_INVALID:
  304. default:
  305. printf("kirkwood_i2c_do_action: Invalid action: %d\n",
  306. drv_data->action);
  307. drv_data->rc = -EIO;
  308. /* FALLTHRU */
  309. case KW_I2C_ACTION_SEND_STOP:
  310. drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN;
  311. writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP,
  312. CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  313. drv_data->block = 0;
  314. break;
  315. }
  316. }
  317. static int
  318. kirkwood_i2c_intr(void)
  319. {
  320. u32 status;
  321. u32 ctrl;
  322. int rc = IRQ_NONE;
  323. ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  324. while ((ctrl & KW_I2C_REG_CONTROL_IFLG) &&
  325. (drv_data->rc == 0)) {
  326. status = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_STATUS);
  327. kirkwood_i2c_fsm(status);
  328. kirkwood_i2c_do_action();
  329. rc = IRQ_HANDLED;
  330. ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL);
  331. udelay(1000);
  332. }
  333. return rc;
  334. }
  335. static void
  336. kirkwood_i2c_doio(struct i2c_msg *msg)
  337. {
  338. int ret;
  339. while ((drv_data->rc == 0) && (drv_data->state != KW_I2C_STATE_IDLE)) {
  340. /* poll Status register */
  341. ret = kirkwood_i2c_intr();
  342. if (ret == IRQ_NONE)
  343. udelay(10);
  344. }
  345. }
  346. static void
  347. kirkwood_i2c_prepare_for_io(struct i2c_msg *msg)
  348. {
  349. u32 dir = 0;
  350. drv_data->msg = msg;
  351. drv_data->byte_posn = 0;
  352. drv_data->bytes_left = msg->len;
  353. drv_data->aborting = 0;
  354. drv_data->rc = 0;
  355. /* in u-boot we use no IRQs */
  356. drv_data->cntl_bits = KW_I2C_REG_CONTROL_ACK | KW_I2C_REG_CONTROL_TWSIEN;
  357. if (msg->flags & I2C_M_RD)
  358. dir = 1;
  359. if (msg->flags & I2C_M_TEN) {
  360. drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
  361. drv_data->addr2 = (u32)msg->addr & 0xff;
  362. } else {
  363. drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
  364. drv_data->addr2 = 0;
  365. }
  366. /* OK, no start it (from kirkwood_i2c_execute_msg())*/
  367. drv_data->action = KW_I2C_ACTION_SEND_START;
  368. drv_data->state = KW_I2C_STATE_WAITING_FOR_START_COND;
  369. drv_data->block = 1;
  370. kirkwood_i2c_do_action();
  371. }
  372. void
  373. i2c_init(int speed, int slaveadd)
  374. {
  375. kirkwood_i2c_hw_init(speed, slaveadd);
  376. }
  377. int
  378. i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
  379. {
  380. kirkwood_i2c_msg->buf = data;
  381. kirkwood_i2c_msg->len = length;
  382. kirkwood_i2c_msg->addr = dev;
  383. kirkwood_i2c_msg->flags = I2C_M_RD;
  384. kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg);
  385. kirkwood_i2c_doio(kirkwood_i2c_msg);
  386. return drv_data->rc;
  387. }
  388. int
  389. i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
  390. {
  391. kirkwood_i2c_msg->buf = data;
  392. kirkwood_i2c_msg->len = length;
  393. kirkwood_i2c_msg->addr = dev;
  394. kirkwood_i2c_msg->flags = 0;
  395. kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg);
  396. kirkwood_i2c_doio(kirkwood_i2c_msg);
  397. return drv_data->rc;
  398. }
  399. int
  400. i2c_probe(uchar chip)
  401. {
  402. return i2c_read(chip, 0, 0, NULL, 0);
  403. }
  404. int i2c_set_bus_num(unsigned int bus)
  405. {
  406. #if defined(CONFIG_I2C_MUX)
  407. if (bus < CONFIG_SYS_MAX_I2C_BUS) {
  408. i2c_bus_num = bus;
  409. } else {
  410. int ret;
  411. ret = i2x_mux_select_mux(bus);
  412. if (ret)
  413. return ret;
  414. i2c_bus_num = 0;
  415. }
  416. i2c_bus_num_mux = bus;
  417. #else
  418. if (bus > 0) {
  419. return -1;
  420. }
  421. i2c_bus_num = bus;
  422. #endif
  423. return 0;
  424. }
  425. unsigned int i2c_get_bus_num(void)
  426. {
  427. #if defined(CONFIG_I2C_MUX)
  428. return i2c_bus_num_mux;
  429. #else
  430. return i2c_bus_num;
  431. #endif
  432. }