mx25pdk.c 5.0 KB

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  1. /*
  2. * (C) Copyright 2011 Freescale Semiconductor, Inc.
  3. *
  4. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. */
  19. #include <common.h>
  20. #include <asm/io.h>
  21. #include <asm/gpio.h>
  22. #include <asm/arch/imx-regs.h>
  23. #include <asm/arch/iomux-mx25.h>
  24. #include <asm/arch/clock.h>
  25. #include <mmc.h>
  26. #include <fsl_esdhc.h>
  27. #include <i2c.h>
  28. #include <power/pmic.h>
  29. #include <fsl_pmic.h>
  30. #include <mc34704.h>
  31. #define FEC_RESET_B IMX_GPIO_NR(4, 8)
  32. #define FEC_ENABLE_B IMX_GPIO_NR(2, 3)
  33. #define CARD_DETECT IMX_GPIO_NR(2, 1)
  34. DECLARE_GLOBAL_DATA_PTR;
  35. #ifdef CONFIG_FSL_ESDHC
  36. struct fsl_esdhc_cfg esdhc_cfg[1] = {
  37. {IMX_MMC_SDHC1_BASE},
  38. };
  39. #endif
  40. /*
  41. * FIXME: need to revisit this
  42. * The original code enabled PUE and 100-k pull-down without PKE, so the right
  43. * value here is likely:
  44. * 0 for no pull
  45. * or:
  46. * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
  47. */
  48. #define FEC_OUT_PAD_CTRL 0
  49. #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
  50. PAD_CTL_ODE)
  51. static void mx25pdk_fec_init(void)
  52. {
  53. static const iomux_v3_cfg_t fec_pads[] = {
  54. MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
  55. MX25_PAD_FEC_RX_DV__FEC_RX_DV,
  56. MX25_PAD_FEC_RDATA0__FEC_RDATA0,
  57. NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
  58. NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
  59. NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
  60. MX25_PAD_FEC_MDIO__FEC_MDIO,
  61. MX25_PAD_FEC_RDATA1__FEC_RDATA1,
  62. NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
  63. NEW_PAD_CTRL(MX25_PAD_D12__GPIO_4_8, 0), /* FEC_RESET_B */
  64. NEW_PAD_CTRL(MX25_PAD_A17__GPIO_2_3, 0), /* FEC_ENABLE_B */
  65. };
  66. static const iomux_v3_cfg_t i2c_pads[] = {
  67. NEW_PAD_CTRL(MX25_PAD_I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
  68. NEW_PAD_CTRL(MX25_PAD_I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
  69. };
  70. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  71. /* Assert RESET and ENABLE low */
  72. gpio_direction_output(FEC_RESET_B, 0);
  73. gpio_direction_output(FEC_ENABLE_B, 0);
  74. udelay(10);
  75. /* Deassert RESET and ENABLE */
  76. gpio_set_value(FEC_RESET_B, 1);
  77. gpio_set_value(FEC_ENABLE_B, 1);
  78. /* Setup I2C pins so that PMIC can turn on PHY supply */
  79. imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
  80. }
  81. int dram_init(void)
  82. {
  83. /* dram_init must store complete ramsize in gd->ram_size */
  84. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  85. PHYS_SDRAM_1_SIZE);
  86. return 0;
  87. }
  88. /*
  89. * Set up input pins with hysteresis and 100-k pull-ups
  90. */
  91. #define UART1_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP)
  92. /*
  93. * FIXME: need to revisit this
  94. * The original code enabled PUE and 100-k pull-down without PKE, so the right
  95. * value here is likely:
  96. * 0 for no pull
  97. * or:
  98. * PAD_CTL_PUS_100K_DOWN for 100-k pull-down
  99. */
  100. #define UART1_OUT_PAD_CTRL 0
  101. static void mx25pdk_uart1_init(void)
  102. {
  103. static const iomux_v3_cfg_t uart1_pads[] = {
  104. NEW_PAD_CTRL(MX25_PAD_UART1_RXD__UART1_RXD, UART1_IN_PAD_CTRL),
  105. NEW_PAD_CTRL(MX25_PAD_UART1_TXD__UART1_TXD, UART1_OUT_PAD_CTRL),
  106. NEW_PAD_CTRL(MX25_PAD_UART1_RTS__UART1_RTS, UART1_OUT_PAD_CTRL),
  107. NEW_PAD_CTRL(MX25_PAD_UART1_CTS__UART1_CTS, UART1_IN_PAD_CTRL),
  108. };
  109. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  110. }
  111. int board_early_init_f(void)
  112. {
  113. mx25pdk_uart1_init();
  114. return 0;
  115. }
  116. int board_init(void)
  117. {
  118. /* address of boot parameters */
  119. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  120. return 0;
  121. }
  122. int board_late_init(void)
  123. {
  124. struct pmic *p;
  125. int ret;
  126. mx25pdk_fec_init();
  127. ret = pmic_init(I2C_PMIC);
  128. if (ret)
  129. return ret;
  130. p = pmic_get("FSL_PMIC");
  131. if (!p)
  132. return -ENODEV;
  133. /* Turn on Ethernet PHY supply */
  134. pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
  135. return 0;
  136. }
  137. #ifdef CONFIG_FSL_ESDHC
  138. int board_mmc_getcd(struct mmc *mmc)
  139. {
  140. /* Set up the Card Detect pin. */
  141. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_A15__GPIO_2_1, 0));
  142. gpio_direction_input(CARD_DETECT);
  143. return !gpio_get_value(CARD_DETECT);
  144. }
  145. int board_mmc_init(bd_t *bis)
  146. {
  147. static const iomux_v3_cfg_t sdhc1_pads[] = {
  148. NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
  149. NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
  150. NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
  151. NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
  152. NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
  153. NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
  154. };
  155. imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
  156. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  157. return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
  158. }
  159. #endif
  160. int checkboard(void)
  161. {
  162. puts("Board: MX25PDK\n");
  163. return 0;
  164. }