ether.c 15 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. /*
  25. * Ethernet test
  26. *
  27. * The Serial Communication Controllers (SCC) listed in ctlr_list array below
  28. * are tested in the loopback ethernet mode.
  29. * The controllers are configured accordingly and several packets
  30. * are transmitted. The configurable test parameters are:
  31. * MIN_PACKET_LENGTH - minimum size of packet to transmit
  32. * MAX_PACKET_LENGTH - maximum size of packet to transmit
  33. * TEST_NUM - number of tests
  34. */
  35. #include <post.h>
  36. #if CONFIG_POST & CONFIG_SYS_POST_ETHER
  37. #if defined(CONFIG_8xx)
  38. #include <commproc.h>
  39. #elif defined(CONFIG_MPC8260)
  40. #include <asm/cpm_8260.h>
  41. #else
  42. #error "Apparently a bad configuration, please fix."
  43. #endif
  44. #include <command.h>
  45. #include <net.h>
  46. #include <serial.h>
  47. DECLARE_GLOBAL_DATA_PTR;
  48. #define MIN_PACKET_LENGTH 64
  49. #define MAX_PACKET_LENGTH 256
  50. #define TEST_NUM 1
  51. #define CTLR_SCC 0
  52. extern void spi_init_f (void);
  53. extern void spi_init_r (void);
  54. /* The list of controllers to test */
  55. #if defined(CONFIG_MPC823)
  56. static int ctlr_list[][2] = { {CTLR_SCC, 1} };
  57. #else
  58. static int ctlr_list[][2] = { };
  59. #endif
  60. static struct {
  61. void (*init) (int index);
  62. void (*halt) (int index);
  63. int (*send) (int index, volatile void *packet, int length);
  64. int (*recv) (int index, void *packet, int length);
  65. } ctlr_proc[1];
  66. static char *ctlr_name[1] = { "SCC" };
  67. /* Ethernet Transmit and Receive Buffers */
  68. #define DBUF_LENGTH 1520
  69. #define TX_BUF_CNT 2
  70. #define TOUT_LOOP 100
  71. static char txbuf[DBUF_LENGTH];
  72. static uint rxIdx; /* index of the current RX buffer */
  73. static uint txIdx; /* index of the current TX buffer */
  74. /*
  75. * SCC Ethernet Tx and Rx buffer descriptors allocated at the
  76. * immr->udata_bd address on Dual-Port RAM
  77. * Provide for Double Buffering
  78. */
  79. typedef volatile struct CommonBufferDescriptor {
  80. cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
  81. cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
  82. } RTXBD;
  83. static RTXBD *rtx;
  84. /*
  85. * SCC callbacks
  86. */
  87. static void scc_init (int scc_index)
  88. {
  89. uchar ea[6];
  90. static int proff[] = {
  91. PROFF_SCC1,
  92. PROFF_SCC2,
  93. PROFF_SCC3,
  94. PROFF_SCC4,
  95. };
  96. static unsigned int cpm_cr[] = {
  97. CPM_CR_CH_SCC1,
  98. CPM_CR_CH_SCC2,
  99. CPM_CR_CH_SCC3,
  100. CPM_CR_CH_SCC4,
  101. };
  102. int i;
  103. scc_enet_t *pram_ptr;
  104. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  105. immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
  106. ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  107. #if defined(CONFIG_FADS)
  108. #if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS)
  109. /* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */
  110. *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
  111. *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL;
  112. *((uint *) BCSR1) &= ~BCSR1_ETHEN;
  113. #else
  114. *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN);
  115. *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE;
  116. *((uint *) BCSR1) &= ~BCSR1_ETHEN;
  117. #endif
  118. #endif
  119. pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]);
  120. rxIdx = 0;
  121. txIdx = 0;
  122. #ifdef CONFIG_SYS_ALLOC_DPRAM
  123. rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
  124. dpram_alloc_align (sizeof (RTXBD), 8));
  125. #else
  126. rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
  127. #endif
  128. #if 0
  129. #if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
  130. /* Configure port A pins for Txd and Rxd.
  131. */
  132. immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD);
  133. immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
  134. immr->im_ioport.iop_paodr &= ~PA_ENET_TXD;
  135. #elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
  136. /* Configure port B pins for Txd and Rxd.
  137. */
  138. immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD);
  139. immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
  140. immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD;
  141. #else
  142. #error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
  143. #endif
  144. #if defined(PC_ENET_LBK)
  145. /* Configure port C pins to disable External Loopback
  146. */
  147. immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
  148. immr->im_ioport.iop_pcdir |= PC_ENET_LBK;
  149. immr->im_ioport.iop_pcso &= ~PC_ENET_LBK;
  150. immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
  151. #endif /* PC_ENET_LBK */
  152. /* Configure port C pins to enable CLSN and RENA.
  153. */
  154. immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
  155. immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
  156. immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA);
  157. /* Configure port A for TCLK and RCLK.
  158. */
  159. immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK);
  160. immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
  161. /*
  162. * Configure Serial Interface clock routing -- see section 16.7.5.3
  163. * First, clear all SCC bits to zero, then set the ones we want.
  164. */
  165. immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
  166. immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
  167. #else
  168. /*
  169. * SCC2 receive clock is BRG2
  170. * SCC2 transmit clock is BRG3
  171. */
  172. immr->im_cpm.cp_brgc2 = 0x0001000C;
  173. immr->im_cpm.cp_brgc3 = 0x0001000C;
  174. immr->im_cpm.cp_sicr &= ~0x00003F00;
  175. immr->im_cpm.cp_sicr |= 0x00000a00;
  176. #endif /* 0 */
  177. /*
  178. * Initialize SDCR -- see section 16.9.23.7
  179. * SDMA configuration register
  180. */
  181. immr->im_siu_conf.sc_sdcr = 0x01;
  182. /*
  183. * Setup SCC Ethernet Parameter RAM
  184. */
  185. pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */
  186. pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */
  187. pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */
  188. pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */
  189. pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */
  190. /*
  191. * Setup Receiver Buffer Descriptors (13.14.24.18)
  192. * Settings:
  193. * Empty, Wrap
  194. */
  195. for (i = 0; i < PKTBUFSRX; i++) {
  196. rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  197. rtx->rxbd[i].cbd_datlen = 0; /* Reset */
  198. rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
  199. }
  200. rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  201. /*
  202. * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  203. * Settings:
  204. * Add PADs to Short FRAMES, Wrap, Last, Tx CRC
  205. */
  206. for (i = 0; i < TX_BUF_CNT; i++) {
  207. rtx->txbd[i].cbd_sc =
  208. (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
  209. rtx->txbd[i].cbd_datlen = 0; /* Reset */
  210. rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
  211. }
  212. rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
  213. /*
  214. * Enter Command: Initialize Rx Params for SCC
  215. */
  216. do { /* Spin until ready to issue command */
  217. __asm__ ("eieio");
  218. } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
  219. /* Issue command */
  220. immr->im_cpm.cp_cpcr =
  221. ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) |
  222. CPM_CR_FLG);
  223. do { /* Spin until command processed */
  224. __asm__ ("eieio");
  225. } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
  226. /*
  227. * Ethernet Specific Parameter RAM
  228. * see table 13-16, pg. 660,
  229. * pg. 681 (example with suggested settings)
  230. */
  231. pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
  232. pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
  233. pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
  234. pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */
  235. pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
  236. pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
  237. pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
  238. pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
  239. pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
  240. pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
  241. pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
  242. pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
  243. pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
  244. pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
  245. pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
  246. eth_getenv_enetaddr("ethaddr", ea);
  247. pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
  248. pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
  249. pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
  250. pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
  251. pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
  252. pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
  253. pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
  254. pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
  255. pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
  256. pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
  257. pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
  258. /*
  259. * Enter Command: Initialize Tx Params for SCC
  260. */
  261. do { /* Spin until ready to issue command */
  262. __asm__ ("eieio");
  263. } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
  264. /* Issue command */
  265. immr->im_cpm.cp_cpcr =
  266. ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) |
  267. CPM_CR_FLG);
  268. do { /* Spin until command processed */
  269. __asm__ ("eieio");
  270. } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
  271. /*
  272. * Mask all Events in SCCM - we use polling mode
  273. */
  274. immr->im_cpm.cp_scc[scc_index].scc_sccm = 0;
  275. /*
  276. * Clear Events in SCCE -- Clear bits by writing 1's
  277. */
  278. immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0);
  279. /*
  280. * Initialize GSMR High 32-Bits
  281. * Settings: Normal Mode
  282. */
  283. immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0;
  284. /*
  285. * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
  286. * Settings:
  287. * TCI = Invert
  288. * TPL = 48 bits
  289. * TPP = Repeating 10's
  290. * LOOP = Loopback
  291. * MODE = Ethernet
  292. */
  293. immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI |
  294. SCC_GSMRL_TPL_48 |
  295. SCC_GSMRL_TPP_10 |
  296. SCC_GSMRL_DIAG_LOOP |
  297. SCC_GSMRL_MODE_ENET);
  298. /*
  299. * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
  300. */
  301. immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555;
  302. /*
  303. * Initialize the PSMR
  304. * Settings:
  305. * CRC = 32-Bit CCITT
  306. * NIB = Begin searching for SFD 22 bits after RENA
  307. * LPB = Loopback Enable (Needed when FDE is set)
  308. */
  309. immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC |
  310. SCC_PSMR_NIB22 | SCC_PSMR_LPB;
  311. #ifdef CONFIG_RPXCLASSIC
  312. *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
  313. *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
  314. #endif
  315. #ifdef CONFIG_RPXLITE
  316. *((uchar *) BCSR0) |= BCSR0_ETHEN;
  317. #endif
  318. #ifdef CONFIG_MBX
  319. board_ether_init ();
  320. #endif
  321. /*
  322. * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
  323. */
  324. immr->im_cpm.cp_scc[scc_index].scc_gsmrl |=
  325. (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  326. /*
  327. * Work around transmit problem with first eth packet
  328. */
  329. #if defined (CONFIG_FADS)
  330. udelay (10000); /* wait 10 ms */
  331. #elif defined(CONFIG_RPXCLASSIC)
  332. udelay (100000); /* wait 100 ms */
  333. #endif
  334. }
  335. static void scc_halt (int scc_index)
  336. {
  337. volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
  338. immr->im_cpm.cp_scc[scc_index].scc_gsmrl &=
  339. ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
  340. immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA);
  341. }
  342. static int scc_send (int index, volatile void *packet, int length)
  343. {
  344. int i, j = 0;
  345. while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
  346. udelay (1); /* will also trigger Wd if needed */
  347. j++;
  348. }
  349. if (j >= TOUT_LOOP)
  350. printf ("TX not ready\n");
  351. rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
  352. rtx->txbd[txIdx].cbd_datlen = length;
  353. rtx->txbd[txIdx].cbd_sc |=
  354. (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP);
  355. while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) {
  356. udelay (1); /* will also trigger Wd if needed */
  357. j++;
  358. }
  359. if (j >= TOUT_LOOP)
  360. printf ("TX timeout\n");
  361. i = (rtx->txbd[txIdx].
  362. cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ;
  363. return i;
  364. }
  365. static int scc_recv (int index, void *packet, int max_length)
  366. {
  367. int length = -1;
  368. if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
  369. goto Done; /* nothing received */
  370. }
  371. if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) {
  372. length = rtx->rxbd[rxIdx].cbd_datlen - 4;
  373. memcpy (packet,
  374. (void *) (NetRxPackets[rxIdx]),
  375. length < max_length ? length : max_length);
  376. }
  377. /* Give the buffer back to the SCC. */
  378. rtx->rxbd[rxIdx].cbd_datlen = 0;
  379. /* wrap around buffer index when necessary */
  380. if ((rxIdx + 1) >= PKTBUFSRX) {
  381. rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
  382. (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
  383. rxIdx = 0;
  384. } else {
  385. rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
  386. rxIdx++;
  387. }
  388. Done:
  389. return length;
  390. }
  391. /*
  392. * Test routines
  393. */
  394. static void packet_fill (char *packet, int length)
  395. {
  396. char c = (char) length;
  397. int i;
  398. packet[0] = 0xFF;
  399. packet[1] = 0xFF;
  400. packet[2] = 0xFF;
  401. packet[3] = 0xFF;
  402. packet[4] = 0xFF;
  403. packet[5] = 0xFF;
  404. for (i = 6; i < length; i++) {
  405. packet[i] = c++;
  406. }
  407. }
  408. static int packet_check (char *packet, int length)
  409. {
  410. char c = (char) length;
  411. int i;
  412. for (i = 6; i < length; i++) {
  413. if (packet[i] != c++)
  414. return -1;
  415. }
  416. return 0;
  417. }
  418. static int test_ctlr (int ctlr, int index)
  419. {
  420. int res = -1;
  421. char packet_send[MAX_PACKET_LENGTH];
  422. char packet_recv[MAX_PACKET_LENGTH];
  423. int length;
  424. int i;
  425. int l;
  426. ctlr_proc[ctlr].init (index);
  427. for (i = 0; i < TEST_NUM; i++) {
  428. for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
  429. packet_fill (packet_send, l);
  430. ctlr_proc[ctlr].send (index, packet_send, l);
  431. length = ctlr_proc[ctlr].recv (index, packet_recv,
  432. MAX_PACKET_LENGTH);
  433. if (length != l || packet_check (packet_recv, length) < 0) {
  434. goto Done;
  435. }
  436. }
  437. }
  438. res = 0;
  439. Done:
  440. ctlr_proc[ctlr].halt (index);
  441. /*
  442. * SCC2 Ethernet parameter RAM space overlaps
  443. * the SPI parameter RAM space. So we need to restore
  444. * the SPI configuration after SCC2 ethernet test.
  445. */
  446. #if defined(CONFIG_SPI)
  447. if (ctlr == CTLR_SCC && index == 1) {
  448. spi_init_f ();
  449. spi_init_r ();
  450. }
  451. #endif
  452. if (res != 0) {
  453. post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr],
  454. index + 1);
  455. }
  456. return res;
  457. }
  458. int ether_post_test (int flags)
  459. {
  460. int res = 0;
  461. int i;
  462. ctlr_proc[CTLR_SCC].init = scc_init;
  463. ctlr_proc[CTLR_SCC].halt = scc_halt;
  464. ctlr_proc[CTLR_SCC].send = scc_send;
  465. ctlr_proc[CTLR_SCC].recv = scc_recv;
  466. for (i = 0; i < ARRAY_SIZE(ctlr_list); i++) {
  467. if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
  468. res = -1;
  469. }
  470. }
  471. #if !defined(CONFIG_8xx_CONS_NONE)
  472. serial_reinit_all ();
  473. #endif
  474. return res;
  475. }
  476. #endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */