omap730p2.c 7.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277
  1. /*
  2. * (C) Copyright 2002
  3. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Marius Groeger <mgroeger@sysgo.de>
  5. *
  6. * (C) Copyright 2002
  7. * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  8. *
  9. * (C) Copyright 2003
  10. * Texas Instruments, <www.ti.com>
  11. * Kshitij Gupta <Kshitij@ti.com>
  12. *
  13. * See file CREDITS for list of people who contributed to this
  14. * project.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29. * MA 02111-1307 USA
  30. */
  31. #include <common.h>
  32. #include <netdev.h>
  33. #if defined(CONFIG_OMAP730)
  34. #include <./configs/omap730.h>
  35. #endif
  36. DECLARE_GLOBAL_DATA_PTR;
  37. int test_boot_mode(void);
  38. void spin_up_leds(void);
  39. void flash__init (void);
  40. void ether__init (void);
  41. void set_muxconf_regs (void);
  42. void peripheral_power_enable (void);
  43. #define FLASH_ON_CS0 1
  44. #define FLASH_ON_CS3 0
  45. static inline void delay (unsigned long loops)
  46. {
  47. __asm__ volatile ("1:\n"
  48. "subs %0, %1, #1\n"
  49. "bne 1b":"=r" (loops):"0" (loops));
  50. }
  51. int test_boot_mode(void)
  52. {
  53. /* Check for CS0 and CS3 address decode swapping */
  54. if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
  55. return(FLASH_ON_CS3);
  56. else
  57. return(FLASH_ON_CS0);
  58. }
  59. /* Toggle backup LED indication */
  60. void toggle_backup_led(void)
  61. {
  62. static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */
  63. volatile unsigned int *IOConfReg;
  64. IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
  65. if (backupLEDState != 0) {
  66. *IOConfReg &= (0xFFFFEFFF);
  67. backupLEDState = 0;
  68. } else {
  69. *IOConfReg |= (0x00001000);
  70. backupLEDState = 1;
  71. }
  72. }
  73. /*
  74. * Miscellaneous platform dependent initialisations
  75. */
  76. int board_init (void)
  77. {
  78. /* arch number of OMAP 730 P2 Board - Same as the Innovator! */
  79. gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2;
  80. /* adress of boot parameters */
  81. gd->bd->bi_boot_params = 0x10000100;
  82. /* Configure MUX settings */
  83. set_muxconf_regs ();
  84. peripheral_power_enable ();
  85. /* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
  86. toggle_backup_led();
  87. /* Hold GSM in reset until needed */
  88. *((volatile unsigned short *)M_CTL) &= ~1;
  89. /*
  90. * CSx timings, GPIO Mux ... setup
  91. */
  92. /* Flash: CS0 timings setup */
  93. *((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
  94. *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
  95. /* Ethernet support trough the debug board */
  96. /* CS1 timings setup */
  97. *((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
  98. *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
  99. /* this speeds up your boot a quite a bit. However to make it
  100. * work, you need make sure your kernel startup flush bug is fixed.
  101. * ... rkw ...
  102. */
  103. icache_enable ();
  104. flash__init ();
  105. ether__init ();
  106. return 0;
  107. }
  108. int misc_init_r (void)
  109. {
  110. /* currently empty */
  111. return (0);
  112. }
  113. /******************************
  114. Routine:
  115. Description:
  116. ******************************/
  117. void flash__init (void)
  118. {
  119. unsigned int regval;
  120. regval = *((volatile unsigned int *) EMIFS_CONFIG);
  121. /* Turn off write protection for flash devices. */
  122. regval = regval | 0x0001;
  123. *((volatile unsigned int *) EMIFS_CONFIG) = regval;
  124. }
  125. /*************************************************************
  126. Routine:ether__init
  127. Description: take the Ethernet controller out of reset and wait
  128. for the EEPROM load to complete.
  129. *************************************************************/
  130. void ether__init (void)
  131. {
  132. #define LAN_RESET_REGISTER 0x0400001c
  133. *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
  134. do {
  135. *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
  136. udelay (100);
  137. } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
  138. do {
  139. *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
  140. udelay (100);
  141. } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
  142. #define ETH_CONTROL_REG 0x0400030b
  143. *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
  144. udelay (100);
  145. }
  146. /******************************
  147. Routine:
  148. Description:
  149. ******************************/
  150. int dram_init (void)
  151. {
  152. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  153. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  154. return 0;
  155. }
  156. /******************************************************
  157. Routine: set_muxconf_regs
  158. Description: Setting up the configuration Mux registers
  159. specific to the hardware
  160. *******************************************************/
  161. void set_muxconf_regs (void)
  162. {
  163. volatile unsigned int *MuxConfReg;
  164. /* set each registers to its reset value; */
  165. /*
  166. * Backup LED Indication
  167. */
  168. /* Configure MUXed pin. Mode 6: GPIO_140 */
  169. MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
  170. *MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */
  171. *MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */
  172. /* Configure GPIO_140 as output */
  173. MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
  174. *MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */
  175. /*
  176. * Configure GPIOs for battery charge & feedback
  177. */
  178. /* Configure MUXed pin. Mode 6: GPIO_35 */
  179. MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
  180. *MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */
  181. *MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */
  182. /* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
  183. MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
  184. *MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */
  185. *MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */
  186. MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
  187. *MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */
  188. *MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */
  189. /*
  190. * Allow battery charge
  191. */
  192. MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
  193. *MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */
  194. /*
  195. * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
  196. * It is used as the Ethernet controller interrupt
  197. */
  198. MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
  199. *MuxConfReg &= 0x1FFFFFFF;
  200. }
  201. /******************************************************
  202. Routine: peripheral_power_enable
  203. Description: Enable the power for UART1
  204. *******************************************************/
  205. void peripheral_power_enable (void)
  206. {
  207. volatile unsigned int *MuxConfReg;
  208. /* Set up pins used by UART */
  209. /* Start UART clock (48MHz) */
  210. MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
  211. *MuxConfReg &= (0xFFFFFFF7);
  212. *MuxConfReg |= (0x00000008);
  213. /* Get the UART pin in mode0 */
  214. MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
  215. *MuxConfReg &= (0xFF1FFFFF);
  216. *MuxConfReg &= (0xF1FFFFFF);
  217. }
  218. #ifdef CONFIG_CMD_NET
  219. int board_eth_init(bd_t *bis)
  220. {
  221. int rc = 0;
  222. #ifdef CONFIG_LAN91C96
  223. rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
  224. #endif
  225. return rc;
  226. }
  227. #endif