M5329EVB.h 8.0 KB

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  1. /*
  2. * Configuation settings for the Freescale MCF5329 FireEngine board.
  3. *
  4. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * board/config.h - configuration options, board specific
  27. */
  28. #ifndef _M5329EVB_H
  29. #define _M5329EVB_H
  30. /*
  31. * High Level Configuration Options
  32. * (easy to change)
  33. */
  34. #define CONFIG_MCF532x /* define processor family */
  35. #define CONFIG_M5329 /* define processor type */
  36. #undef DEBUG
  37. #define CONFIG_MCFUART
  38. #define CFG_UART_PORT (0)
  39. #define CONFIG_BAUDRATE 115200
  40. #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  41. #undef CONFIG_WATCHDOG
  42. #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
  43. #define DEFAULT_COMMANDS ( CONFIG_CMD_DFL | \
  44. CFG_CMD_CACHE | \
  45. CFG_CMD_DATE | \
  46. CFG_CMD_ELF | \
  47. CFG_CMD_FLASH | \
  48. CFG_CMD_I2C | \
  49. (CFG_CMD_LOADB | CFG_CMD_LOADS) | \
  50. CFG_CMD_MEMORY | \
  51. CFG_CMD_MISC | \
  52. CFG_CMD_MII | \
  53. CFG_CMD_NET | \
  54. CFG_CMD_PING | \
  55. CFG_CMD_REGINFO \
  56. )
  57. #ifdef NANDFLASH_SIZE
  58. # define CONFIG_COMMANDS (DEFAULT_COMMANDS | CFG_CMD_NAND)
  59. #else
  60. # define CONFIG_COMMANDS (DEFAULT_COMMANDS)
  61. #endif
  62. #define CFG_UNIFY_CACHE
  63. #define CONFIG_MCFFEC
  64. #ifdef CONFIG_MCFFEC
  65. # define CONFIG_NET_MULTI 1
  66. # define CONFIG_MII 1
  67. # define CFG_DISCOVER_PHY
  68. # define CFG_RX_ETH_BUFFER 8
  69. # define CFG_FAULT_ECHO_LINK_DOWN
  70. # define CFG_FEC0_PINMUX 0
  71. # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
  72. # define MCFFEC_TOUT_LOOP 50000
  73. /* If CFG_DISCOVER_PHY is not defined - hardcoded */
  74. # ifndef CFG_DISCOVER_PHY
  75. # define FECDUPLEX FULL
  76. # define FECSPEED _100BASET
  77. # else
  78. # ifndef CFG_FAULT_ECHO_LINK_DOWN
  79. # define CFG_FAULT_ECHO_LINK_DOWN
  80. # endif
  81. # endif /* CFG_DISCOVER_PHY */
  82. #endif
  83. #define CONFIG_MCFRTC
  84. #undef RTC_DEBUG
  85. /* Timer */
  86. #define CONFIG_MCFTMR
  87. #undef CONFIG_MCFPIT
  88. /* I2C */
  89. #define CONFIG_FSL_I2C
  90. #define CONFIG_HARD_I2C /* I2C with hw support */
  91. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  92. #define CFG_I2C_SPEED 80000
  93. #define CFG_I2C_SLAVE 0x7F
  94. #define CFG_I2C_OFFSET 0x58000
  95. #define CFG_IMMR CFG_MBAR
  96. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  97. #include <cmd_confdefs.h>
  98. #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
  99. #ifdef CONFIG_MCFFEC
  100. # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
  101. # define CONFIG_IPADDR 192.162.1.2
  102. # define CONFIG_NETMASK 255.255.255.0
  103. # define CONFIG_SERVERIP 192.162.1.1
  104. # define CONFIG_GATEWAYIP 192.162.1.1
  105. # define CONFIG_OVERWRITE_ETHADDR_ONCE
  106. #endif /* FEC_ENET */
  107. #define CONFIG_HOSTNAME M5329EVB
  108. #define CONFIG_EXTRA_ENV_SETTINGS \
  109. "netdev=eth0\0" \
  110. "loadaddr=40010000\0" \
  111. "u-boot=u-boot.bin\0" \
  112. "load=tftp ${loadaddr) ${u-boot}\0" \
  113. "upd=run load; run prog\0" \
  114. "prog=prot off 0 2ffff;" \
  115. "era 0 2ffff;" \
  116. "cp.b ${loadaddr} 0 ${filesize};" \
  117. "save\0" \
  118. ""
  119. #define CONFIG_PRAM 512 /* 512 KB */
  120. #define CFG_PROMPT "-> "
  121. #define CFG_LONGHELP /* undef to save memory */
  122. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  123. # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  124. #else
  125. # define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  126. #endif
  127. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  128. #define CFG_MAXARGS 16 /* max number of command args */
  129. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  130. #define CFG_LOAD_ADDR 0x40010000
  131. #define CFG_HZ 1000
  132. #define CFG_CLK 80000000
  133. #define CFG_CPU_CLK CFG_CLK * 3
  134. #define CFG_MBAR 0xFC000000
  135. #define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000)
  136. /*
  137. * Low Level Configuration Settings
  138. * (address mappings, register initial values, etc.)
  139. * You should know what you are doing if you make changes here.
  140. */
  141. /*-----------------------------------------------------------------------
  142. * Definitions for initial stack pointer and data area (in DPRAM)
  143. */
  144. #define CFG_INIT_RAM_ADDR 0x80000000
  145. #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
  146. #define CFG_INIT_RAM_CTRL 0x221
  147. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  148. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  149. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  150. /*-----------------------------------------------------------------------
  151. * Start addresses for the final memory configuration
  152. * (Set up by the startup code)
  153. * Please note that CFG_SDRAM_BASE _must_ start at 0
  154. */
  155. #define CFG_SDRAM_BASE 0x40000000
  156. #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
  157. #define CFG_SDRAM_CFG1 0x53722730
  158. #define CFG_SDRAM_CFG2 0x56670000
  159. #define CFG_SDRAM_CTRL 0xE1092000
  160. #define CFG_SDRAM_EMOD 0x40010000
  161. #define CFG_SDRAM_MODE 0x018D0000
  162. #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
  163. #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
  164. #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
  165. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  166. #define CFG_BOOTPARAMS_LEN 64*1024
  167. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  168. /*
  169. * For booting Linux, the board info and command line data
  170. * have to be in the first 8 MB of memory, since this is
  171. * the maximum mapped by the Linux kernel during initialization ??
  172. */
  173. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  174. /*-----------------------------------------------------------------------
  175. * FLASH organization
  176. */
  177. #define CFG_FLASH_CFI
  178. #ifdef CFG_FLASH_CFI
  179. # define CFG_FLASH_CFI_DRIVER 1
  180. # define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */
  181. # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  182. # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  183. # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  184. # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  185. #endif
  186. #ifdef NANDFLASH_SIZE
  187. # define CFG_MAX_NAND_DEVICE 1
  188. # define CFG_NAND_BASE (CFG_CS2_BASE << 16)
  189. # define CFG_NAND_SIZE 1
  190. # define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
  191. # define NAND_MAX_CHIPS 1
  192. # define NAND_ALLOW_ERASE_ALL 1
  193. # define CONFIG_JFFS2_NAND 1
  194. # define CONFIG_JFFS2_DEV "nand0"
  195. # define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1)
  196. # define CONFIG_JFFS2_PART_OFFSET 0x00000000
  197. #endif
  198. #define CFG_FLASH_BASE 0
  199. #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
  200. /* Configuration for environment
  201. * Environment is embedded in u-boot in the second sector of the flash
  202. */
  203. #define CFG_ENV_OFFSET 0x4000
  204. #define CFG_ENV_SECT_SIZE 0x2000
  205. #define CFG_ENV_IS_IN_FLASH 1
  206. #define CFG_ENV_IS_EMBEDDED 1
  207. /*-----------------------------------------------------------------------
  208. * Cache Configuration
  209. */
  210. #define CFG_CACHELINE_SIZE 16
  211. /*-----------------------------------------------------------------------
  212. * Chipselect bank definitions
  213. */
  214. /*
  215. * CS0 - NOR Flash 1, 2, 4, or 8MB
  216. * CS1 - CompactFlash and registers
  217. * CS2 - NAND Flash 16, 32, or 64MB
  218. * CS3 - Available
  219. * CS4 - Available
  220. * CS5 - Available
  221. */
  222. #define CFG_CS0_BASE 0
  223. #define CFG_CS0_MASK 0x007f0001
  224. #define CFG_CS0_CTRL 0x00001fa0
  225. #define CFG_CS1_BASE 0x1000
  226. #define CFG_CS1_MASK 0x001f0001
  227. #define CFG_CS1_CTRL 0x002A3780
  228. #ifdef NANDFLASH_SIZE
  229. #define CFG_CS2_BASE 0x2000
  230. #define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
  231. #define CFG_CS2_CTRL 0x00001f60
  232. #endif
  233. #define CONFIG_UDP_CHECKSUM
  234. #endif /* _M5329EVB_H */