fsl_i2c.c 6.2 KB

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  1. /*
  2. * Copyright 2006 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * Version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  16. * MA 02111-1307 USA
  17. */
  18. #include <common.h>
  19. #ifdef CONFIG_FSL_I2C
  20. #ifdef CONFIG_HARD_I2C
  21. #include <command.h>
  22. #include <i2c.h> /* Functional interface */
  23. #include <asm/io.h>
  24. #include <asm/fsl_i2c.h> /* HW definitions */
  25. #define I2C_TIMEOUT (CFG_HZ / 4)
  26. #define I2C_READ_BIT 1
  27. #define I2C_WRITE_BIT 0
  28. /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
  29. * Default is bus 0. This is necessary because the DDR initialization
  30. * runs from ROM, and we can't switch buses because we can't modify
  31. * the global variables.
  32. */
  33. #ifdef CFG_SPD_BUS_NUM
  34. static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
  35. #else
  36. static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
  37. #endif
  38. static volatile struct fsl_i2c *i2c_dev[2] = {
  39. (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
  40. #ifdef CFG_I2C2_OFFSET
  41. (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
  42. #endif
  43. };
  44. void
  45. i2c_init(int speed, int slaveadd)
  46. {
  47. volatile struct fsl_i2c *dev;
  48. dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
  49. writeb(0, &dev->cr); /* stop I2C controller */
  50. udelay(5); /* let it shutdown in peace */
  51. writeb(0x3F, &dev->fdr); /* set bus speed */
  52. writeb(0x3F, &dev->dfsrr); /* set default filter */
  53. writeb(slaveadd << 1, &dev->adr); /* write slave address */
  54. writeb(0x0, &dev->sr); /* clear status register */
  55. writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
  56. #ifdef CFG_I2C2_OFFSET
  57. dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
  58. writeb(0, &dev->cr); /* stop I2C controller */
  59. writeb(0x3F, &dev->fdr); /* set bus speed */
  60. writeb(0x3F, &dev->dfsrr); /* set default filter */
  61. writeb(slaveadd, &dev->adr); /* write slave address */
  62. writeb(0x0, &dev->sr); /* clear status register */
  63. writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
  64. #endif /* CFG_I2C2_OFFSET */
  65. }
  66. static __inline__ int
  67. i2c_wait4bus(void)
  68. {
  69. ulong timeval = get_timer(0);
  70. while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
  71. if (get_timer(timeval) > I2C_TIMEOUT) {
  72. return -1;
  73. }
  74. }
  75. return 0;
  76. }
  77. static __inline__ int
  78. i2c_wait(int write)
  79. {
  80. u32 csr;
  81. ulong timeval = get_timer(0);
  82. do {
  83. csr = readb(&i2c_dev[i2c_bus_num]->sr);
  84. if (!(csr & I2C_SR_MIF))
  85. continue;
  86. writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
  87. if (csr & I2C_SR_MAL) {
  88. debug("i2c_wait: MAL\n");
  89. return -1;
  90. }
  91. if (!(csr & I2C_SR_MCF)) {
  92. debug("i2c_wait: unfinished\n");
  93. return -1;
  94. }
  95. if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
  96. debug("i2c_wait: No RXACK\n");
  97. return -1;
  98. }
  99. return 0;
  100. } while (get_timer (timeval) < I2C_TIMEOUT);
  101. debug("i2c_wait: timed out\n");
  102. return -1;
  103. }
  104. static __inline__ int
  105. i2c_write_addr (u8 dev, u8 dir, int rsta)
  106. {
  107. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
  108. | (rsta ? I2C_CR_RSTA : 0),
  109. &i2c_dev[i2c_bus_num]->cr);
  110. writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
  111. if (i2c_wait(I2C_WRITE_BIT) < 0)
  112. return 0;
  113. return 1;
  114. }
  115. static __inline__ int
  116. __i2c_write(u8 *data, int length)
  117. {
  118. int i;
  119. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
  120. &i2c_dev[i2c_bus_num]->cr);
  121. for (i = 0; i < length; i++) {
  122. writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
  123. if (i2c_wait(I2C_WRITE_BIT) < 0)
  124. break;
  125. }
  126. return i;
  127. }
  128. static __inline__ int
  129. __i2c_read(u8 *data, int length)
  130. {
  131. int i;
  132. writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
  133. &i2c_dev[i2c_bus_num]->cr);
  134. /* dummy read */
  135. readb(&i2c_dev[i2c_bus_num]->dr);
  136. for (i = 0; i < length; i++) {
  137. if (i2c_wait(I2C_READ_BIT) < 0)
  138. break;
  139. /* Generate ack on last next to last byte */
  140. if (i == length - 2)
  141. writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
  142. &i2c_dev[i2c_bus_num]->cr);
  143. /* Generate stop on last byte */
  144. if (i == length - 1)
  145. writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
  146. data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
  147. }
  148. return i;
  149. }
  150. int
  151. i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
  152. {
  153. int i = -1; /* signal error */
  154. u8 *a = (u8*)&addr;
  155. if (i2c_wait4bus() >= 0
  156. && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
  157. && __i2c_write(&a[4 - alen], alen) == alen)
  158. i = 0; /* No error so far */
  159. if (length
  160. && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
  161. i = __i2c_read(data, length);
  162. writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
  163. if (i == length)
  164. return 0;
  165. return -1;
  166. }
  167. int
  168. i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
  169. {
  170. int i = -1; /* signal error */
  171. u8 *a = (u8*)&addr;
  172. if (i2c_wait4bus() >= 0
  173. && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
  174. && __i2c_write(&a[4 - alen], alen) == alen) {
  175. i = __i2c_write(data, length);
  176. }
  177. writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
  178. if (i == length)
  179. return 0;
  180. return -1;
  181. }
  182. int
  183. i2c_probe(uchar chip)
  184. {
  185. /* For unknow reason the controller will ACK when
  186. * probing for a slave with the same address, so skip
  187. * it.
  188. */
  189. if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
  190. return -1;
  191. return i2c_read(chip, 0, 0, NULL, 0);
  192. }
  193. uchar
  194. i2c_reg_read(uchar i2c_addr, uchar reg)
  195. {
  196. uchar buf[1];
  197. i2c_read(i2c_addr, reg, 1, buf, 1);
  198. return buf[0];
  199. }
  200. void
  201. i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
  202. {
  203. i2c_write(i2c_addr, reg, 1, &val, 1);
  204. }
  205. int i2c_set_bus_num(unsigned int bus)
  206. {
  207. #ifdef CFG_I2C2_OFFSET
  208. if (bus > 1) {
  209. #else
  210. if (bus > 0) {
  211. #endif
  212. return -1;
  213. }
  214. i2c_bus_num = bus;
  215. return 0;
  216. }
  217. int i2c_set_bus_speed(unsigned int speed)
  218. {
  219. return -1;
  220. }
  221. unsigned int i2c_get_bus_num(void)
  222. {
  223. return i2c_bus_num;
  224. }
  225. unsigned int i2c_get_bus_speed(void)
  226. {
  227. return 0;
  228. }
  229. #endif /* CONFIG_HARD_I2C */
  230. #endif /* CONFIG_FSL_I2C */