nand.c 15 KB

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  1. /*
  2. * (C) Copyright 2006 DENX Software Engineering
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #if defined(CONFIG_CMD_NAND)
  24. #ifdef CONFIG_NEW_NAND_CODE
  25. #include <nand.h>
  26. #include <asm/arch/pxa-regs.h>
  27. #ifdef CONFIG_SYS_DFC_DEBUG1
  28. # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
  29. #else
  30. # define DFC_DEBUG1(fmt, args...)
  31. #endif
  32. #ifdef CONFIG_SYS_DFC_DEBUG2
  33. # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
  34. #else
  35. # define DFC_DEBUG2(fmt, args...)
  36. #endif
  37. #ifdef CONFIG_SYS_DFC_DEBUG3
  38. # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
  39. #else
  40. # define DFC_DEBUG3(fmt, args...)
  41. #endif
  42. /* These really don't belong here, as they are specific to the NAND Model */
  43. static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
  44. static struct nand_bbt_descr delta_bbt_descr = {
  45. .options = 0,
  46. .offs = 0,
  47. .len = 2,
  48. .pattern = scan_ff_pattern
  49. };
  50. static struct nand_ecclayout delta_oob = {
  51. .eccbytes = 6,
  52. .eccpos = {2, 3, 4, 5, 6, 7},
  53. .oobfree = { {8, 2}, {12, 4} }
  54. };
  55. /*
  56. * not required for Monahans DFC
  57. */
  58. static void dfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  59. {
  60. return;
  61. }
  62. #if 0
  63. /* read device ready pin */
  64. static int dfc_device_ready(struct mtd_info *mtdinfo)
  65. {
  66. if(NDSR & NDSR_RDY)
  67. return 1;
  68. else
  69. return 0;
  70. return 0;
  71. }
  72. #endif
  73. /*
  74. * Write buf to the DFC Controller Data Buffer
  75. */
  76. static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  77. {
  78. unsigned long bytes_multi = len & 0xfffffffc;
  79. unsigned long rest = len & 0x3;
  80. unsigned long *long_buf;
  81. int i;
  82. DFC_DEBUG2("dfc_write_buf: writing %d bytes starting with 0x%x.\n", len, *((unsigned long*) buf));
  83. if(bytes_multi) {
  84. for(i=0; i<bytes_multi; i+=4) {
  85. long_buf = (unsigned long*) &buf[i];
  86. NDDB = *long_buf;
  87. }
  88. }
  89. if(rest) {
  90. printf("dfc_write_buf: ERROR, writing non 4-byte aligned data.\n");
  91. }
  92. return;
  93. }
  94. /* The original:
  95. * static void dfc_read_buf(struct mtd_info *mtd, const u_char *buf, int len)
  96. *
  97. * Shouldn't this be "u_char * const buf" ?
  98. */
  99. static void dfc_read_buf(struct mtd_info *mtd, u_char* const buf, int len)
  100. {
  101. int i=0, j;
  102. /* we have to be carefull not to overflow the buffer if len is
  103. * not a multiple of 4 */
  104. unsigned long bytes_multi = len & 0xfffffffc;
  105. unsigned long rest = len & 0x3;
  106. unsigned long *long_buf;
  107. DFC_DEBUG3("dfc_read_buf: reading %d bytes.\n", len);
  108. /* if there are any, first copy multiple of 4 bytes */
  109. if(bytes_multi) {
  110. for(i=0; i<bytes_multi; i+=4) {
  111. long_buf = (unsigned long*) &buf[i];
  112. *long_buf = NDDB;
  113. }
  114. }
  115. /* ...then the rest */
  116. if(rest) {
  117. unsigned long rest_data = NDDB;
  118. for(j=0;j<rest; j++)
  119. buf[i+j] = (u_char) ((rest_data>>j) & 0xff);
  120. }
  121. return;
  122. }
  123. /*
  124. * read a word. Not implemented as not used in NAND code.
  125. */
  126. static u16 dfc_read_word(struct mtd_info *mtd)
  127. {
  128. printf("dfc_read_word: UNIMPLEMENTED.\n");
  129. return 0;
  130. }
  131. /* global var, too bad: mk@tbd: move to ->priv pointer */
  132. static unsigned long read_buf = 0;
  133. static int bytes_read = -1;
  134. /*
  135. * read a byte from NDDB Because we can only read 4 bytes from NDDB at
  136. * a time, we buffer the remaining bytes. The buffer is reset when a
  137. * new command is sent to the chip.
  138. *
  139. * WARNING:
  140. * This function is currently only used to read status and id
  141. * bytes. For these commands always 8 bytes need to be read from
  142. * NDDB. So we read and discard these bytes right now. In case this
  143. * function is used for anything else in the future, we must check
  144. * what was the last command issued and read the appropriate amount of
  145. * bytes respectively.
  146. */
  147. static u_char dfc_read_byte(struct mtd_info *mtd)
  148. {
  149. unsigned char byte;
  150. unsigned long dummy;
  151. if(bytes_read < 0) {
  152. read_buf = NDDB;
  153. dummy = NDDB;
  154. bytes_read = 0;
  155. }
  156. byte = (unsigned char) (read_buf>>(8 * bytes_read++));
  157. if(bytes_read >= 4)
  158. bytes_read = -1;
  159. DFC_DEBUG2("dfc_read_byte: byte %u: 0x%x of (0x%x).\n", bytes_read - 1, byte, read_buf);
  160. return byte;
  161. }
  162. /* calculate delta between OSCR values start and now */
  163. static unsigned long get_delta(unsigned long start)
  164. {
  165. unsigned long cur = OSCR;
  166. if(cur < start) /* OSCR overflowed */
  167. return (cur + (start^0xffffffff));
  168. else
  169. return (cur - start);
  170. }
  171. /* delay function, this doesn't belong here */
  172. static void wait_us(unsigned long us)
  173. {
  174. unsigned long start = OSCR;
  175. us *= OSCR_CLK_FREQ;
  176. while (get_delta(start) < us) {
  177. /* do nothing */
  178. }
  179. }
  180. static void dfc_clear_nddb(void)
  181. {
  182. NDCR &= ~NDCR_ND_RUN;
  183. wait_us(CONFIG_SYS_NAND_OTHER_TO);
  184. }
  185. /* wait_event with timeout */
  186. static unsigned long dfc_wait_event(unsigned long event)
  187. {
  188. unsigned long ndsr, timeout, start = OSCR;
  189. if(!event)
  190. return 0xff000000;
  191. else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
  192. timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
  193. else
  194. timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
  195. while(1) {
  196. ndsr = NDSR;
  197. if(ndsr & event) {
  198. NDSR |= event;
  199. break;
  200. }
  201. if(get_delta(start) > timeout) {
  202. DFC_DEBUG1("dfc_wait_event: TIMEOUT waiting for event: 0x%lx.\n", event);
  203. return 0xff000000;
  204. }
  205. }
  206. return ndsr;
  207. }
  208. /* we don't always wan't to do this */
  209. static void dfc_new_cmd(void)
  210. {
  211. int retry = 0;
  212. unsigned long status;
  213. while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
  214. /* Clear NDSR */
  215. NDSR = 0xFFF;
  216. /* set NDCR[NDRUN] */
  217. if(!(NDCR & NDCR_ND_RUN))
  218. NDCR |= NDCR_ND_RUN;
  219. status = dfc_wait_event(NDSR_WRCMDREQ);
  220. if(status & NDSR_WRCMDREQ)
  221. return;
  222. DFC_DEBUG2("dfc_new_cmd: FAILED to get WRITECMDREQ, retry: %d.\n", retry);
  223. dfc_clear_nddb();
  224. }
  225. DFC_DEBUG1("dfc_new_cmd: giving up after %d retries.\n", retry);
  226. }
  227. /* this function is called after Programm and Erase Operations to
  228. * check for success or failure */
  229. static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this)
  230. {
  231. unsigned long ndsr=0, event=0;
  232. int state = this->state;
  233. if(state == FL_WRITING) {
  234. event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
  235. } else if(state == FL_ERASING) {
  236. event = NDSR_CS0_CMDD | NDSR_CS0_BBD;
  237. }
  238. ndsr = dfc_wait_event(event);
  239. if((ndsr & NDSR_CS0_BBD) || (ndsr & 0xff000000))
  240. return(0x1); /* Status Read error */
  241. return 0;
  242. }
  243. /* cmdfunc send commands to the DFC */
  244. static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command,
  245. int column, int page_addr)
  246. {
  247. /* register struct nand_chip *this = mtd->priv; */
  248. unsigned long ndcb0=0, ndcb1=0, ndcb2=0, event=0;
  249. /* clear the ugly byte read buffer */
  250. bytes_read = -1;
  251. read_buf = 0;
  252. switch (command) {
  253. case NAND_CMD_READ0:
  254. DFC_DEBUG3("dfc_cmdfunc: NAND_CMD_READ0, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
  255. dfc_new_cmd();
  256. ndcb0 = (NAND_CMD_READ0 | (4<<16));
  257. column >>= 1; /* adjust for 16 bit bus */
  258. ndcb1 = (((column>>1) & 0xff) |
  259. ((page_addr<<8) & 0xff00) |
  260. ((page_addr<<8) & 0xff0000) |
  261. ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
  262. event = NDSR_RDDREQ;
  263. goto write_cmd;
  264. case NAND_CMD_READ1:
  265. DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READ1 unimplemented!\n");
  266. goto end;
  267. case NAND_CMD_READOOB:
  268. DFC_DEBUG1("dfc_cmdfunc: NAND_CMD_READOOB unimplemented!\n");
  269. goto end;
  270. case NAND_CMD_READID:
  271. dfc_new_cmd();
  272. DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_READID.\n");
  273. ndcb0 = (NAND_CMD_READID | (3 << 21) | (1 << 16)); /* addr cycles*/
  274. event = NDSR_RDDREQ;
  275. goto write_cmd;
  276. case NAND_CMD_PAGEPROG:
  277. /* sent as a multicommand in NAND_CMD_SEQIN */
  278. DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_PAGEPROG empty due to multicmd.\n");
  279. goto end;
  280. case NAND_CMD_ERASE1:
  281. DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE1, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
  282. dfc_new_cmd();
  283. ndcb0 = (0xd060 | (1<<25) | (2<<21) | (1<<19) | (3<<16));
  284. ndcb1 = (page_addr & 0x00ffffff);
  285. goto write_cmd;
  286. case NAND_CMD_ERASE2:
  287. DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_ERASE2 empty due to multicmd.\n");
  288. goto end;
  289. case NAND_CMD_SEQIN:
  290. /* send PAGE_PROG command(0x1080) */
  291. dfc_new_cmd();
  292. DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, page_addr: 0x%x, column: 0x%x.\n", page_addr, (column>>1));
  293. ndcb0 = (0x1080 | (1<<25) | (1<<21) | (1<<19) | (4<<16));
  294. column >>= 1; /* adjust for 16 bit bus */
  295. ndcb1 = (((column>>1) & 0xff) |
  296. ((page_addr<<8) & 0xff00) |
  297. ((page_addr<<8) & 0xff0000) |
  298. ((page_addr<<8) & 0xff000000)); /* make this 0x01000000 ? */
  299. event = NDSR_WRDREQ;
  300. goto write_cmd;
  301. case NAND_CMD_STATUS:
  302. DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_STATUS.\n");
  303. dfc_new_cmd();
  304. ndcb0 = NAND_CMD_STATUS | (4<<21);
  305. event = NDSR_RDDREQ;
  306. goto write_cmd;
  307. case NAND_CMD_RESET:
  308. DFC_DEBUG2("dfc_cmdfunc: NAND_CMD_RESET.\n");
  309. ndcb0 = NAND_CMD_RESET | (5<<21);
  310. event = NDSR_CS0_CMDD;
  311. goto write_cmd;
  312. default:
  313. printk("dfc_cmdfunc: error, unsupported command.\n");
  314. goto end;
  315. }
  316. write_cmd:
  317. NDCB0 = ndcb0;
  318. NDCB0 = ndcb1;
  319. NDCB0 = ndcb2;
  320. /* wait_event: */
  321. dfc_wait_event(event);
  322. end:
  323. return;
  324. }
  325. static void dfc_gpio_init(void)
  326. {
  327. DFC_DEBUG2("Setting up DFC GPIO's.\n");
  328. /* no idea what is done here, see zylonite.c */
  329. GPIO4 = 0x1;
  330. DF_ALE_WE1 = 0x00000001;
  331. DF_ALE_WE2 = 0x00000001;
  332. DF_nCS0 = 0x00000001;
  333. DF_nCS1 = 0x00000001;
  334. DF_nWE = 0x00000001;
  335. DF_nRE = 0x00000001;
  336. DF_IO0 = 0x00000001;
  337. DF_IO8 = 0x00000001;
  338. DF_IO1 = 0x00000001;
  339. DF_IO9 = 0x00000001;
  340. DF_IO2 = 0x00000001;
  341. DF_IO10 = 0x00000001;
  342. DF_IO3 = 0x00000001;
  343. DF_IO11 = 0x00000001;
  344. DF_IO4 = 0x00000001;
  345. DF_IO12 = 0x00000001;
  346. DF_IO5 = 0x00000001;
  347. DF_IO13 = 0x00000001;
  348. DF_IO6 = 0x00000001;
  349. DF_IO14 = 0x00000001;
  350. DF_IO7 = 0x00000001;
  351. DF_IO15 = 0x00000001;
  352. DF_nWE = 0x1901;
  353. DF_nRE = 0x1901;
  354. DF_CLE_NOE = 0x1900;
  355. DF_ALE_WE1 = 0x1901;
  356. DF_INT_RnB = 0x1900;
  357. }
  358. /*
  359. * Board-specific NAND initialization. The following members of the
  360. * argument are board-specific (per include/linux/mtd/nand_new.h):
  361. * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
  362. * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
  363. * - cmd_ctrl: hardwarespecific function for accesing control-lines
  364. * - dev_ready: hardwarespecific function for accesing device ready/busy line
  365. * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
  366. * only be provided if a hardware ECC is available
  367. * - ecc.mode: mode of ecc, see defines
  368. * - chip_delay: chip dependent delay for transfering data from array to
  369. * read regs (tR)
  370. * - options: various chip options. They can partly be set to inform
  371. * nand_scan about special functionality. See the defines for further
  372. * explanation
  373. * Members with a "?" were not set in the merged testing-NAND branch,
  374. * so they are not set here either.
  375. */
  376. int board_nand_init(struct nand_chip *nand)
  377. {
  378. unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
  379. /* set up GPIO Control Registers */
  380. dfc_gpio_init();
  381. /* turn on the NAND Controller Clock (104 MHz @ D0) */
  382. CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
  383. #undef CONFIG_SYS_TIMING_TIGHT
  384. #ifndef CONFIG_SYS_TIMING_TIGHT
  385. tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
  386. DFC_MAX_tCH);
  387. tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
  388. DFC_MAX_tCS);
  389. tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US) + 1),
  390. DFC_MAX_tWH);
  391. tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US) + 1),
  392. DFC_MAX_tWP);
  393. tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US) + 1),
  394. DFC_MAX_tRH);
  395. tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US) + 1),
  396. DFC_MAX_tRP);
  397. tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) + 1),
  398. DFC_MAX_tR);
  399. tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) + 1),
  400. DFC_MAX_tWHR);
  401. tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) + 1),
  402. DFC_MAX_tAR);
  403. #else /* this is the tight timing */
  404. tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US)),
  405. DFC_MAX_tCH);
  406. tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US)),
  407. DFC_MAX_tCS);
  408. tWH = MIN(((unsigned long) (NAND_TIMING_tWH * DFC_CLK_PER_US)),
  409. DFC_MAX_tWH);
  410. tWP = MIN(((unsigned long) (NAND_TIMING_tWP * DFC_CLK_PER_US)),
  411. DFC_MAX_tWP);
  412. tRH = MIN(((unsigned long) (NAND_TIMING_tRH * DFC_CLK_PER_US)),
  413. DFC_MAX_tRH);
  414. tRP = MIN(((unsigned long) (NAND_TIMING_tRP * DFC_CLK_PER_US)),
  415. DFC_MAX_tRP);
  416. tR = MIN(((unsigned long) (NAND_TIMING_tR * DFC_CLK_PER_US) - tCH - 2),
  417. DFC_MAX_tR);
  418. tWHR = MIN(((unsigned long) (NAND_TIMING_tWHR * DFC_CLK_PER_US) - tCH - 2),
  419. DFC_MAX_tWHR);
  420. tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
  421. DFC_MAX_tAR);
  422. #endif /* CONFIG_SYS_TIMING_TIGHT */
  423. DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
  424. /* tRP value is split in the register */
  425. if(tRP & (1 << 4)) {
  426. tRP_high = 1;
  427. tRP &= ~(1 << 4);
  428. } else {
  429. tRP_high = 0;
  430. }
  431. NDTR0CS0 = (tCH << 19) |
  432. (tCS << 16) |
  433. (tWH << 11) |
  434. (tWP << 8) |
  435. (tRP_high << 6) |
  436. (tRH << 3) |
  437. (tRP << 0);
  438. NDTR1CS0 = (tR << 16) |
  439. (tWHR << 4) |
  440. (tAR << 0);
  441. /* If it doesn't work (unlikely) think about:
  442. * - ecc enable
  443. * - chip select don't care
  444. * - read id byte count
  445. *
  446. * Intentionally enabled by not setting bits:
  447. * - dma (DMA_EN)
  448. * - page size = 512
  449. * - cs don't care, see if we can enable later!
  450. * - row address start position (after second cycle)
  451. * - pages per block = 32
  452. * - ND_RDY : clears command buffer
  453. */
  454. /* NDCR_NCSX | /\* Chip select busy don't care *\/ */
  455. NDCR = (NDCR_SPARE_EN | /* use the spare area */
  456. NDCR_DWIDTH_C | /* 16bit DFC data bus width */
  457. NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */
  458. (2 << 16) | /* read id count = 7 ???? mk@tbd */
  459. NDCR_ND_ARB_EN | /* enable bus arbiter */
  460. NDCR_RDYM | /* flash device ready ir masked */
  461. NDCR_CS0_PAGEDM | /* ND_nCSx page done ir masked */
  462. NDCR_CS1_PAGEDM |
  463. NDCR_CS0_CMDDM | /* ND_CSx command done ir masked */
  464. NDCR_CS1_CMDDM |
  465. NDCR_CS0_BBDM | /* ND_CSx bad block detect ir masked */
  466. NDCR_CS1_BBDM |
  467. NDCR_DBERRM | /* double bit error ir masked */
  468. NDCR_SBERRM | /* single bit error ir masked */
  469. NDCR_WRDREQM | /* write data request ir masked */
  470. NDCR_RDDREQM | /* read data request ir masked */
  471. NDCR_WRCMDREQM); /* write command request ir masked */
  472. /* wait 10 us due to cmd buffer clear reset */
  473. /* wait(10); */
  474. nand->cmd_ctrl = dfc_hwcontrol;
  475. /* nand->dev_ready = dfc_device_ready; */
  476. nand->ecc.mode = NAND_ECC_SOFT;
  477. nand->ecc.layout = &delta_oob;
  478. nand->options = NAND_BUSWIDTH_16;
  479. nand->waitfunc = dfc_wait;
  480. nand->read_byte = dfc_read_byte;
  481. nand->read_word = dfc_read_word;
  482. nand->read_buf = dfc_read_buf;
  483. nand->write_buf = dfc_write_buf;
  484. nand->cmdfunc = dfc_cmdfunc;
  485. nand->badblock_pattern = &delta_bbt_descr;
  486. return 0;
  487. }
  488. #else
  489. #error "U-Boot legacy NAND support not available for Monahans DFC."
  490. #endif
  491. #endif