sbc8260.h 35 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Murray Jensen <Murray.Jensen@cmst.csiro.au>
  4. *
  5. * (C) Copyright 2000
  6. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. * Marius Groeger <mgroeger@sysgo.de>
  8. *
  9. * (C) Copyright 2001
  10. * Advent Networks, Inc. <http://www.adventnetworks.com>
  11. * Jay Monkman <jtm@smoothsmoothie.com>
  12. *
  13. * Configuration settings for the WindRiver SBC8260 board.
  14. * See http://www.windriver.com/products/html/sbc8260.html
  15. *
  16. * See file CREDITS for list of people who contributed to this
  17. * project.
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License as
  21. * published by the Free Software Foundation; either version 2 of
  22. * the License, or (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32. * MA 02111-1307 USA
  33. */
  34. #ifndef __CONFIG_H
  35. #define __CONFIG_H
  36. /* Enable debug prints */
  37. #undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
  38. /*****************************************************************************
  39. *
  40. * These settings must match the way _your_ board is set up
  41. *
  42. *****************************************************************************/
  43. /* What is the oscillator's (UX2) frequency in Hz? */
  44. #define CONFIG_8260_CLKIN (66 * 1000 * 1000)
  45. /*-----------------------------------------------------------------------
  46. * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  47. *-----------------------------------------------------------------------
  48. * What should MODCK_H be? It is dependent on the oscillator
  49. * frequency, MODCK[1-3], and desired CPM and core frequencies.
  50. * Here are some example values (all frequencies are in MHz):
  51. *
  52. * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
  53. * ------- ---------- --- --- ---- ----- ----- -----
  54. * 0x1 0x5 33 100 133 Open Close Open
  55. * 0x1 0x6 33 100 166 Open Open Close
  56. * 0x1 0x7 33 100 200 Open Open Open
  57. *
  58. * 0x2 0x2 33 133 133 Close Open Close
  59. * 0x2 0x3 33 133 166 Close Open Open
  60. * 0x2 0x4 33 133 200 Open Close Close
  61. * 0x2 0x5 33 133 233 Open Close Open
  62. * 0x2 0x6 33 133 266 Open Open Close
  63. *
  64. * 0x5 0x5 66 133 133 Open Close Open
  65. * 0x5 0x6 66 133 166 Open Open Close
  66. * 0x5 0x7 66 133 200 Open Open Open
  67. * 0x6 0x0 66 133 233 Close Close Close
  68. * 0x6 0x1 66 133 266 Close Close Open
  69. * 0x6 0x2 66 133 300 Close Open Close
  70. */
  71. #define CONFIG_SYS_SBC_MODCK_H 0x05
  72. /* Define this if you want to boot from 0x00000100. If you don't define
  73. * this, you will need to program the bootloader to 0xfff00000, and
  74. * get the hardware reset config words at 0xfe000000. The simplest
  75. * way to do that is to program the bootloader at both addresses.
  76. * It is suggested that you just let U-Boot live at 0x00000000.
  77. */
  78. #define CONFIG_SYS_SBC_BOOT_LOW 1
  79. /* What should the base address of the main FLASH be and how big is
  80. * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
  81. * The main FLASH is whichever is connected to *CS0. U-Boot expects
  82. * this to be the SIMM.
  83. */
  84. #define CONFIG_SYS_FLASH0_BASE 0x40000000
  85. #define CONFIG_SYS_FLASH0_SIZE 4
  86. /* What should the base address of the secondary FLASH be and how big
  87. * is it (in Mbytes)? The secondary FLASH is whichever is connected
  88. * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
  89. * want it enabled, don't define these constants.
  90. */
  91. #define CONFIG_SYS_FLASH1_BASE 0x60000000
  92. #define CONFIG_SYS_FLASH1_SIZE 2
  93. /* What should be the base address of SDRAM DIMM and how big is
  94. * it (in Mbytes)?
  95. */
  96. #define CONFIG_SYS_SDRAM0_BASE 0x00000000
  97. #define CONFIG_SYS_SDRAM0_SIZE 64
  98. /* What should be the base address of the LEDs and switch S0?
  99. * If you don't want them enabled, don't define this.
  100. */
  101. #define CONFIG_SYS_LED_BASE 0xa0000000
  102. /*
  103. * SBC8260 with 16 MB DIMM:
  104. *
  105. * 0x0000 0000 Exception Vector code, 8k
  106. * :
  107. * 0x0000 1FFF
  108. * 0x0000 2000 Free for Application Use
  109. * :
  110. * :
  111. *
  112. * :
  113. * :
  114. * 0x00F5 FF30 Monitor Stack (Growing downward)
  115. * Monitor Stack Buffer (0x80)
  116. * 0x00F5 FFB0 Board Info Data
  117. * 0x00F6 0000 Malloc Arena
  118. * : CONFIG_ENV_SECT_SIZE, 256k
  119. * : CONFIG_SYS_MALLOC_LEN, 128k
  120. * 0x00FC 0000 RAM Copy of Monitor Code
  121. * : CONFIG_SYS_MONITOR_LEN, 256k
  122. * 0x00FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
  123. */
  124. /*
  125. * SBC8260 with 64 MB DIMM:
  126. *
  127. * 0x0000 0000 Exception Vector code, 8k
  128. * :
  129. * 0x0000 1FFF
  130. * 0x0000 2000 Free for Application Use
  131. * :
  132. * :
  133. *
  134. * :
  135. * :
  136. * 0x03F5 FF30 Monitor Stack (Growing downward)
  137. * Monitor Stack Buffer (0x80)
  138. * 0x03F5 FFB0 Board Info Data
  139. * 0x03F6 0000 Malloc Arena
  140. * : CONFIG_ENV_SECT_SIZE, 256k
  141. * : CONFIG_SYS_MALLOC_LEN, 128k
  142. * 0x03FC 0000 RAM Copy of Monitor Code
  143. * : CONFIG_SYS_MONITOR_LEN, 256k
  144. * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
  145. */
  146. /*
  147. * select serial console configuration
  148. *
  149. * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  150. * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  151. * for SCC).
  152. *
  153. * if CONFIG_CONS_NONE is defined, then the serial console routines must
  154. * defined elsewhere.
  155. */
  156. #define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
  157. #undef CONFIG_CONS_ON_SCC /* define if console on SCC */
  158. #undef CONFIG_CONS_NONE /* define if console on neither */
  159. #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
  160. /*
  161. * select ethernet configuration
  162. *
  163. * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  164. * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  165. * for FCC)
  166. *
  167. * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  168. * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  169. */
  170. #undef CONFIG_ETHER_ON_SCC
  171. #define CONFIG_ETHER_ON_FCC
  172. #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
  173. #ifdef CONFIG_ETHER_ON_SCC
  174. #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
  175. #endif /* CONFIG_ETHER_ON_SCC */
  176. #ifdef CONFIG_ETHER_ON_FCC
  177. #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
  178. #undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
  179. #define CONFIG_MII /* MII PHY management */
  180. #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  181. /*
  182. * Port pins used for bit-banged MII communictions (if applicable).
  183. */
  184. #define MDIO_PORT 2 /* Port C */
  185. #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
  186. (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
  187. #define MDC_DECLARE MDIO_DECLARE
  188. #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
  189. #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
  190. #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
  191. #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
  192. else iop->pdat &= ~0x00400000
  193. #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
  194. else iop->pdat &= ~0x00200000
  195. #define MIIDELAY udelay(1)
  196. #endif /* CONFIG_ETHER_ON_FCC */
  197. #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
  198. /*
  199. * - RX clk is CLK11
  200. * - TX clk is CLK12
  201. */
  202. # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
  203. #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  204. /*
  205. * - Rx-CLK is CLK13
  206. * - Tx-CLK is CLK14
  207. * - Select bus for bd/buffers (see 28-13)
  208. * - Enable Full Duplex in FSMR
  209. */
  210. # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  211. # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  212. # define CONFIG_SYS_CPMFCR_RAMTYPE 0
  213. # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
  214. #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  215. /*
  216. * Select SPI support configuration
  217. */
  218. #undef CONFIG_SPI /* Disable SPI driver */
  219. /*
  220. * Select i2c support configuration
  221. *
  222. * Supported configurations are {none, software, hardware} drivers.
  223. * If the software driver is chosen, there are some additional
  224. * configuration items that the driver uses to drive the port pins.
  225. */
  226. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  227. #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  228. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  229. #define CONFIG_SYS_I2C_SLAVE 0x7F
  230. /*
  231. * Software (bit-bang) I2C driver configuration
  232. */
  233. #ifdef CONFIG_SOFT_I2C
  234. #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
  235. #define I2C_ACTIVE (iop->pdir |= 0x00010000)
  236. #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
  237. #define I2C_READ ((iop->pdat & 0x00010000) != 0)
  238. #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
  239. else iop->pdat &= ~0x00010000
  240. #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
  241. else iop->pdat &= ~0x00020000
  242. #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
  243. #endif /* CONFIG_SOFT_I2C */
  244. /* Define this to reserve an entire FLASH sector (256 KB) for
  245. * environment variables. Otherwise, the environment will be
  246. * put in the same sector as U-Boot, and changing variables
  247. * will erase U-Boot temporarily
  248. */
  249. #define CONFIG_ENV_IN_OWN_SECT 1
  250. /* Define to allow the user to overwrite serial and ethaddr */
  251. #define CONFIG_ENV_OVERWRITE
  252. /* What should the console's baud rate be? */
  253. #define CONFIG_BAUDRATE 9600
  254. /* Ethernet MAC address
  255. * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx)
  256. * http://standards.ieee.org/regauth/oui/index.shtml
  257. */
  258. #define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb
  259. /*
  260. * Define this to set the last octet of the ethernet address from the
  261. * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7
  262. * switch and the LEDs are backwards with respect to each other. DS7
  263. * is on the board edge side of both the LED strip and the DS0-DS7
  264. * switch.
  265. */
  266. #undef CONFIG_MISC_INIT_R
  267. /* Set to a positive value to delay for running BOOTCOMMAND */
  268. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  269. /* Be selective on what keys can delay or stop the autoboot process
  270. * To stop use: " "
  271. */
  272. #undef CONFIG_AUTOBOOT_KEYED
  273. #ifdef CONFIG_AUTOBOOT_KEYED
  274. # define CONFIG_AUTOBOOT_PROMPT \
  275. "Autobooting in %d seconds, press \" \" to stop\n", bootdelay
  276. # define CONFIG_AUTOBOOT_STOP_STR " "
  277. # undef CONFIG_AUTOBOOT_DELAY_STR
  278. # define DEBUG_BOOTKEYS 0
  279. #endif
  280. /* Define this to contain any number of null terminated strings that
  281. * will be part of the default enviroment compiled into the boot image.
  282. *
  283. * Variable Usage
  284. * -------------- -------------------------------------------------------
  285. * serverip server IP address
  286. * ipaddr my IP address
  287. * reprog Reload flash with a new copy of U-Boot
  288. * zapenv Erase the environment area in flash
  289. * root-on-initrd Set the bootcmd variable to allow booting of an initial
  290. * ram disk.
  291. * root-on-nfs Set the bootcmd variable to allow booting of a NFS
  292. * mounted root filesystem.
  293. * boot-hook Convenient stub to do something useful before the
  294. * bootm command is executed.
  295. *
  296. * Example usage of root-on-initrd and root-on-nfs :
  297. *
  298. * Note: The lines have been wrapped to improved its readability.
  299. *
  300. * => printenv bootcmd
  301. * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
  302. * nfsroot=${serverip}:${rootpath}
  303. * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
  304. *
  305. * => run root-on-initrd
  306. * => printenv bootcmd
  307. * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw
  308. * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
  309. *
  310. * => run root-on-nfs
  311. * => printenv bootcmd
  312. * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
  313. * nfsroot=${serverip}:${rootpath}
  314. * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
  315. *
  316. */
  317. #define CONFIG_EXTRA_ENV_SETTINGS \
  318. "serverip=192.168.123.205\0" \
  319. "ipaddr=192.168.123.213\0" \
  320. "reprog="\
  321. "bootp;" \
  322. "tftpboot 0x140000 /bdi2000/u-boot.bin;" \
  323. "protect off 1:0;" \
  324. "erase 1:0;" \
  325. "cp.b 140000 40000000 ${filesize};" \
  326. "protect on 1:0\0" \
  327. "zapenv="\
  328. "protect off 1:1;" \
  329. "erase 1:1;" \
  330. "protect on 1:1\0" \
  331. "root-on-initrd="\
  332. "setenv bootcmd "\
  333. "version;" \
  334. "echo;" \
  335. "bootp;" \
  336. "setenv bootargs root=/dev/ram0 rw " \
  337. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
  338. "run boot-hook;" \
  339. "bootm\0" \
  340. "root-on-nfs="\
  341. "setenv bootcmd "\
  342. "version;" \
  343. "echo;" \
  344. "bootp;" \
  345. "setenv bootargs root=/dev/nfs rw " \
  346. "nfsroot=${serverip}:${rootpath} " \
  347. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
  348. "run boot-hook;" \
  349. "bootm\0" \
  350. "boot-hook=echo\0"
  351. /* Define a command string that is automatically executed when no character
  352. * is read on the console interface withing "Boot Delay" after reset.
  353. */
  354. #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
  355. #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
  356. #ifdef CONFIG_BOOT_ROOT_INITRD
  357. #define CONFIG_BOOTCOMMAND \
  358. "version;" \
  359. "echo;" \
  360. "bootp;" \
  361. "setenv bootargs root=/dev/ram0 rw " \
  362. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
  363. "bootm"
  364. #endif /* CONFIG_BOOT_ROOT_INITRD */
  365. #ifdef CONFIG_BOOT_ROOT_NFS
  366. #define CONFIG_BOOTCOMMAND \
  367. "version;" \
  368. "echo;" \
  369. "bootp;" \
  370. "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  371. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
  372. "bootm"
  373. #endif /* CONFIG_BOOT_ROOT_NFS */
  374. /*
  375. * BOOTP options
  376. */
  377. #define CONFIG_BOOTP_SUBNETMASK
  378. #define CONFIG_BOOTP_GATEWAY
  379. #define CONFIG_BOOTP_HOSTNAME
  380. #define CONFIG_BOOTP_BOOTPATH
  381. #define CONFIG_BOOTP_BOOTFILESIZE
  382. #define CONFIG_BOOTP_DNS
  383. #define CONFIG_BOOTP_DNS2
  384. #define CONFIG_BOOTP_SEND_HOSTNAME
  385. /* undef this to save memory */
  386. #define CONFIG_SYS_LONGHELP
  387. /* Monitor Command Prompt */
  388. #define CONFIG_SYS_PROMPT "=> "
  389. #undef CONFIG_SYS_HUSH_PARSER
  390. #ifdef CONFIG_SYS_HUSH_PARSER
  391. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  392. #endif
  393. /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
  394. * of an image is printed by image commands like bootm or iminfo.
  395. */
  396. #define CONFIG_TIMESTAMP
  397. /* If this variable is defined, an environment variable named "ver"
  398. * is created by U-Boot showing the U-Boot version.
  399. */
  400. #define CONFIG_VERSION_VARIABLE
  401. /*
  402. * Command line configuration.
  403. */
  404. #include <config_cmd_default.h>
  405. #define CONFIG_CMD_ASKENV
  406. #define CONFIG_CMD_ELF
  407. #define CONFIG_CMD_I2C
  408. #define CONFIG_CMD_IMMAP
  409. #define CONFIG_CMD_PING
  410. #define CONFIG_CMD_REGINFO
  411. #define CONFIG_CMD_SDRAM
  412. #undef CONFIG_CMD_KGDB
  413. #if defined(CONFIG_ETHER_ON_FCC)
  414. #define CONFIG_CMD_CMD_MII
  415. #endif
  416. #undef CONFIG_WATCHDOG /* disable the watchdog */
  417. /* Where do the internal registers live? */
  418. #define CONFIG_SYS_IMMR 0xF0000000
  419. /*****************************************************************************
  420. *
  421. * You should not have to modify any of the following settings
  422. *
  423. *****************************************************************************/
  424. #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
  425. #define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
  426. #define CONFIG_CPM2 1 /* Has a CPM2 */
  427. /*
  428. * Miscellaneous configurable options
  429. */
  430. #if defined(CONFIG_CMD_KGDB)
  431. # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  432. #else
  433. # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  434. #endif
  435. /* Print Buffer Size */
  436. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
  437. #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
  438. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  439. #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
  440. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  441. #define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */
  442. #define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
  443. /* the exception vector table */
  444. /* to the end of the DRAM */
  445. /* less monitor and malloc area */
  446. #define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
  447. #define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
  448. + CONFIG_SYS_MALLOC_LEN \
  449. + CONFIG_ENV_SECT_SIZE \
  450. + CONFIG_SYS_STACK_USAGE )
  451. #define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
  452. - CONFIG_SYS_MEM_END_USAGE )
  453. /* valid baudrates */
  454. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  455. /*
  456. * Low Level Configuration Settings
  457. * (address mappings, register initial values, etc.)
  458. * You should know what you are doing if you make changes here.
  459. */
  460. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
  461. #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
  462. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
  463. #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
  464. /*-----------------------------------------------------------------------
  465. * Hard Reset Configuration Words
  466. */
  467. #if defined(CONFIG_SYS_SBC_BOOT_LOW)
  468. # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
  469. #else
  470. # define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
  471. #endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
  472. /* get the HRCW ISB field from CONFIG_SYS_IMMR */
  473. #define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
  474. ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
  475. ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
  476. #define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS11 | \
  477. HRCW_DPPC11 | \
  478. CONFIG_SYS_SBC_HRCW_IMMR | \
  479. HRCW_MMR00 | \
  480. HRCW_LBPC11 | \
  481. HRCW_APPC10 | \
  482. HRCW_CS10PC00 | \
  483. (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
  484. CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
  485. /* no slaves */
  486. #define CONFIG_SYS_HRCW_SLAVE1 0
  487. #define CONFIG_SYS_HRCW_SLAVE2 0
  488. #define CONFIG_SYS_HRCW_SLAVE3 0
  489. #define CONFIG_SYS_HRCW_SLAVE4 0
  490. #define CONFIG_SYS_HRCW_SLAVE5 0
  491. #define CONFIG_SYS_HRCW_SLAVE6 0
  492. #define CONFIG_SYS_HRCW_SLAVE7 0
  493. /*-----------------------------------------------------------------------
  494. * Definitions for initial stack pointer and data area (in DPRAM)
  495. */
  496. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  497. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
  498. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
  499. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  500. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  501. /*-----------------------------------------------------------------------
  502. * Start addresses for the final memory configuration
  503. * (Set up by the startup code)
  504. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  505. * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
  506. */
  507. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
  508. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  509. # define CONFIG_SYS_RAMBOOT
  510. #endif
  511. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  512. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  513. /*
  514. * For booting Linux, the board info and command line data
  515. * have to be in the first 8 MB of memory, since this is
  516. * the maximum mapped by the Linux kernel during initialization.
  517. */
  518. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  519. /*-----------------------------------------------------------------------
  520. * FLASH and environment organization
  521. */
  522. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  523. #define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
  524. #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
  525. #define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
  526. #ifndef CONFIG_SYS_RAMBOOT
  527. # define CONFIG_ENV_IS_IN_FLASH 1
  528. # ifdef CONFIG_ENV_IN_OWN_SECT
  529. # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  530. # define CONFIG_ENV_SECT_SIZE 0x40000
  531. # else
  532. # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
  533. # define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
  534. # define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
  535. # endif /* CONFIG_ENV_IN_OWN_SECT */
  536. #else
  537. # define CONFIG_ENV_IS_IN_NVRAM 1
  538. # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  539. # define CONFIG_ENV_SIZE 0x200
  540. #endif /* CONFIG_SYS_RAMBOOT */
  541. /*-----------------------------------------------------------------------
  542. * Cache Configuration
  543. */
  544. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
  545. #if defined(CONFIG_CMD_KGDB)
  546. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  547. #endif
  548. /*-----------------------------------------------------------------------
  549. * HIDx - Hardware Implementation-dependent Registers 2-11
  550. *-----------------------------------------------------------------------
  551. * HID0 also contains cache control - initially enable both caches and
  552. * invalidate contents, then the final state leaves only the instruction
  553. * cache enabled. Note that Power-On and Hard reset invalidate the caches,
  554. * but Soft reset does not.
  555. *
  556. * HID1 has only read-only information - nothing to set.
  557. */
  558. #define CONFIG_SYS_HID0_INIT (HID0_ICE |\
  559. HID0_DCE |\
  560. HID0_ICFI |\
  561. HID0_DCI |\
  562. HID0_IFEM |\
  563. HID0_ABE)
  564. #define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
  565. HID0_IFEM |\
  566. HID0_ABE |\
  567. HID0_EMCP)
  568. #define CONFIG_SYS_HID2 0
  569. /*-----------------------------------------------------------------------
  570. * RMR - Reset Mode Register
  571. *-----------------------------------------------------------------------
  572. */
  573. #define CONFIG_SYS_RMR 0
  574. /*-----------------------------------------------------------------------
  575. * BCR - Bus Configuration 4-25
  576. *-----------------------------------------------------------------------
  577. */
  578. #define CONFIG_SYS_BCR (BCR_ETM)
  579. /*-----------------------------------------------------------------------
  580. * SIUMCR - SIU Module Configuration 4-31
  581. *-----------------------------------------------------------------------
  582. */
  583. #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
  584. SIUMCR_L2CPC00 |\
  585. SIUMCR_APPC10 |\
  586. SIUMCR_MMR00)
  587. /*-----------------------------------------------------------------------
  588. * SYPCR - System Protection Control 11-9
  589. * SYPCR can only be written once after reset!
  590. *-----------------------------------------------------------------------
  591. * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  592. */
  593. #if defined(CONFIG_WATCHDOG)
  594. #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
  595. SYPCR_BMT |\
  596. SYPCR_PBME |\
  597. SYPCR_LBME |\
  598. SYPCR_SWRI |\
  599. SYPCR_SWP |\
  600. SYPCR_SWE)
  601. #else
  602. #define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
  603. SYPCR_BMT |\
  604. SYPCR_PBME |\
  605. SYPCR_LBME |\
  606. SYPCR_SWRI |\
  607. SYPCR_SWP)
  608. #endif /* CONFIG_WATCHDOG */
  609. /*-----------------------------------------------------------------------
  610. * TMCNTSC - Time Counter Status and Control 4-40
  611. *-----------------------------------------------------------------------
  612. * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  613. * and enable Time Counter
  614. */
  615. #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
  616. TMCNTSC_ALR |\
  617. TMCNTSC_TCF |\
  618. TMCNTSC_TCE)
  619. /*-----------------------------------------------------------------------
  620. * PISCR - Periodic Interrupt Status and Control 4-42
  621. *-----------------------------------------------------------------------
  622. * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  623. * Periodic timer
  624. */
  625. #define CONFIG_SYS_PISCR (PISCR_PS |\
  626. PISCR_PTF |\
  627. PISCR_PTE)
  628. /*-----------------------------------------------------------------------
  629. * SCCR - System Clock Control 9-8
  630. *-----------------------------------------------------------------------
  631. */
  632. #define CONFIG_SYS_SCCR 0
  633. /*-----------------------------------------------------------------------
  634. * RCCR - RISC Controller Configuration 13-7
  635. *-----------------------------------------------------------------------
  636. */
  637. #define CONFIG_SYS_RCCR 0
  638. /*
  639. * Initialize Memory Controller:
  640. *
  641. * Bank Bus Machine PortSz Device
  642. * ---- --- ------- ------ ------
  643. * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) *
  644. * 1 60x GPCM 32 bit FLASH (SIMM - Unused)
  645. * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
  646. * 3 60x SDRAM 64 bit SDRAM (DIMM - Unused)
  647. * 4 Local SDRAM 32 bit SDRAM (on board - 4MB)
  648. * 5 60x GPCM 8 bit EEPROM (8KB)
  649. * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
  650. * 7 60x GPCM 8 bit LEDs, switches
  651. *
  652. * (*) This configuration requires the SBC8260 be configured
  653. * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
  654. * the on board FLASH. In other words, JP24 should have
  655. * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
  656. *
  657. */
  658. /*-----------------------------------------------------------------------
  659. * BR0,BR1 - Base Register
  660. * Ref: Section 10.3.1 on page 10-14
  661. * OR0,OR1 - Option Register
  662. * Ref: Section 10.3.2 on page 10-18
  663. *-----------------------------------------------------------------------
  664. */
  665. /* Bank 0,1 - FLASH SIMM
  666. *
  667. * This expects the FLASH SIMM to be connected to *CS0
  668. * It consists of 4 AM29F080B parts.
  669. *
  670. * Note: For the 4 MB SIMM, *CS1 is unused.
  671. */
  672. /* BR0 is configured as follows:
  673. *
  674. * - Base address of 0x40000000
  675. * - 32 bit port size
  676. * - Data errors checking is disabled
  677. * - Read and write access
  678. * - GPCM 60x bus
  679. * - Access are handled by the memory controller according to MSEL
  680. * - Not used for atomic operations
  681. * - No data pipelining is done
  682. * - Valid
  683. */
  684. #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
  685. BRx_PS_32 |\
  686. BRx_MS_GPCM_P |\
  687. BRx_V)
  688. /* OR0 is configured as follows:
  689. *
  690. * - 4 MB
  691. * - *BCTL0 is asserted upon access to the current memory bank
  692. * - *CW / *WE are negated a quarter of a clock earlier
  693. * - *CS is output at the same time as the address lines
  694. * - Uses a clock cycle length of 5
  695. * - *PSDVAL is generated internally by the memory controller
  696. * unless *GTA is asserted earlier externally.
  697. * - Relaxed timing is generated by the GPCM for accesses
  698. * initiated to this memory region.
  699. * - One idle clock is inserted between a read access from the
  700. * current bank and the next access.
  701. */
  702. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
  703. ORxG_CSNT |\
  704. ORxG_ACS_DIV1 |\
  705. ORxG_SCY_5_CLK |\
  706. ORxG_TRLX |\
  707. ORxG_EHTR)
  708. /*-----------------------------------------------------------------------
  709. * BR2,BR3 - Base Register
  710. * Ref: Section 10.3.1 on page 10-14
  711. * OR2,OR3 - Option Register
  712. * Ref: Section 10.3.2 on page 10-16
  713. *-----------------------------------------------------------------------
  714. */
  715. /* Bank 2,3 - SDRAM DIMM
  716. *
  717. * 16MB DIMM: P/N
  718. * 64MB DIMM: P/N 1W-8864X8-4-P1-EST
  719. *
  720. * Note: *CS3 is unused for this DIMM
  721. */
  722. /* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
  723. *
  724. * - Base address of 0x00000000
  725. * - 64 bit port size (60x bus only)
  726. * - Data errors checking is disabled
  727. * - Read and write access
  728. * - SDRAM 60x bus
  729. * - Access are handled by the memory controller according to MSEL
  730. * - Not used for atomic operations
  731. * - No data pipelining is done
  732. * - Valid
  733. */
  734. #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
  735. BRx_PS_64 |\
  736. BRx_MS_SDRAM_P |\
  737. BRx_V)
  738. #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
  739. BRx_PS_64 |\
  740. BRx_MS_SDRAM_P |\
  741. BRx_V)
  742. /* With a 16 MB DIMM, the OR2 is configured as follows:
  743. *
  744. * - 16 MB
  745. * - 2 internal banks per device
  746. * - Row start address bit is A9 with PSDMR[PBI] = 0
  747. * - 11 row address lines
  748. * - Back-to-back page mode
  749. * - Internal bank interleaving within save device enabled
  750. */
  751. #if (CONFIG_SYS_SDRAM0_SIZE == 16)
  752. #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
  753. ORxS_BPD_2 |\
  754. ORxS_ROWST_PBI0_A9 |\
  755. ORxS_NUMR_11)
  756. #endif
  757. /* With a 64 MB DIMM, the OR2 is configured as follows:
  758. *
  759. * - 64 MB
  760. * - 4 internal banks per device
  761. * - Row start address bit is A8 with PSDMR[PBI] = 0
  762. * - 12 row address lines
  763. * - Back-to-back page mode
  764. * - Internal bank interleaving within save device enabled
  765. */
  766. #if (CONFIG_SYS_SDRAM0_SIZE == 64)
  767. #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
  768. ORxS_BPD_4 |\
  769. ORxS_ROWST_PBI0_A8 |\
  770. ORxS_NUMR_12)
  771. #endif
  772. /*-----------------------------------------------------------------------
  773. * PSDMR - 60x Bus SDRAM Mode Register
  774. * Ref: Section 10.3.3 on page 10-21
  775. *-----------------------------------------------------------------------
  776. */
  777. /* Address that the DIMM SPD memory lives at.
  778. */
  779. #define SDRAM_SPD_ADDR 0x54
  780. #if (CONFIG_SYS_SDRAM0_SIZE == 16)
  781. /* With a 16 MB DIMM, the PSDMR is configured as follows:
  782. *
  783. * - Bank Based Interleaving,
  784. * - Refresh Enable,
  785. * - Address Multiplexing where A5 is output on A14 pin
  786. * (A6 on A15, and so on),
  787. * - use address pins A16-A18 as bank select,
  788. * - A9 is output on SDA10 during an ACTIVATE command,
  789. * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
  790. * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
  791. * is 3 clocks,
  792. * - earliest timing for READ/WRITE command after ACTIVATE command is
  793. * 2 clocks,
  794. * - earliest timing for PRECHARGE after last data was read is 1 clock,
  795. * - earliest timing for PRECHARGE after last data was written is 1 clock,
  796. * - CAS Latency is 2.
  797. */
  798. #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
  799. PSDMR_SDAM_A14_IS_A5 |\
  800. PSDMR_BSMA_A16_A18 |\
  801. PSDMR_SDA10_PBI0_A9 |\
  802. PSDMR_RFRC_7_CLK |\
  803. PSDMR_PRETOACT_3W |\
  804. PSDMR_ACTTORW_2W |\
  805. PSDMR_LDOTOPRE_1C |\
  806. PSDMR_WRC_1C |\
  807. PSDMR_CL_2)
  808. #endif
  809. #if (CONFIG_SYS_SDRAM0_SIZE == 64)
  810. /* With a 64 MB DIMM, the PSDMR is configured as follows:
  811. *
  812. * - Bank Based Interleaving,
  813. * - Refresh Enable,
  814. * - Address Multiplexing where A5 is output on A14 pin
  815. * (A6 on A15, and so on),
  816. * - use address pins A14-A16 as bank select,
  817. * - A9 is output on SDA10 during an ACTIVATE command,
  818. * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
  819. * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
  820. * is 3 clocks,
  821. * - earliest timing for READ/WRITE command after ACTIVATE command is
  822. * 2 clocks,
  823. * - earliest timing for PRECHARGE after last data was read is 1 clock,
  824. * - earliest timing for PRECHARGE after last data was written is 1 clock,
  825. * - CAS Latency is 2.
  826. */
  827. #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
  828. PSDMR_SDAM_A14_IS_A5 |\
  829. PSDMR_BSMA_A14_A16 |\
  830. PSDMR_SDA10_PBI0_A9 |\
  831. PSDMR_RFRC_7_CLK |\
  832. PSDMR_PRETOACT_3W |\
  833. PSDMR_ACTTORW_2W |\
  834. PSDMR_LDOTOPRE_1C |\
  835. PSDMR_WRC_1C |\
  836. PSDMR_CL_2)
  837. #endif
  838. /*
  839. * Shoot for approximately 1MHz on the prescaler.
  840. */
  841. #if (CONFIG_8260_CLKIN == (66 * 1000 * 1000))
  842. #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64
  843. #elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000))
  844. #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
  845. #else
  846. #warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
  847. #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
  848. #endif
  849. #define CONFIG_SYS_PSRT 14
  850. /* Bank 4 - On board SDRAM
  851. *
  852. * This is not implemented yet.
  853. */
  854. /*-----------------------------------------------------------------------
  855. * BR6 - Base Register
  856. * Ref: Section 10.3.1 on page 10-14
  857. * OR6 - Option Register
  858. * Ref: Section 10.3.2 on page 10-18
  859. *-----------------------------------------------------------------------
  860. */
  861. /* Bank 6 - On board FLASH
  862. *
  863. * This expects the on board FLASH SIMM to be connected to *CS6
  864. * It consists of 1 AM29F016A part.
  865. */
  866. #if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
  867. /* BR6 is configured as follows:
  868. *
  869. * - Base address of 0x60000000
  870. * - 8 bit port size
  871. * - Data errors checking is disabled
  872. * - Read and write access
  873. * - GPCM 60x bus
  874. * - Access are handled by the memory controller according to MSEL
  875. * - Not used for atomic operations
  876. * - No data pipelining is done
  877. * - Valid
  878. */
  879. # define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
  880. BRx_PS_8 |\
  881. BRx_MS_GPCM_P |\
  882. BRx_V)
  883. /* OR6 is configured as follows:
  884. *
  885. * - 2 MB
  886. * - *BCTL0 is asserted upon access to the current memory bank
  887. * - *CW / *WE are negated a quarter of a clock earlier
  888. * - *CS is output at the same time as the address lines
  889. * - Uses a clock cycle length of 5
  890. * - *PSDVAL is generated internally by the memory controller
  891. * unless *GTA is asserted earlier externally.
  892. * - Relaxed timing is generated by the GPCM for accesses
  893. * initiated to this memory region.
  894. * - One idle clock is inserted between a read access from the
  895. * current bank and the next access.
  896. */
  897. # define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\
  898. ORxG_CSNT |\
  899. ORxG_ACS_DIV1 |\
  900. ORxG_SCY_5_CLK |\
  901. ORxG_TRLX |\
  902. ORxG_EHTR)
  903. #endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
  904. /*-----------------------------------------------------------------------
  905. * BR7 - Base Register
  906. * Ref: Section 10.3.1 on page 10-14
  907. * OR7 - Option Register
  908. * Ref: Section 10.3.2 on page 10-18
  909. *-----------------------------------------------------------------------
  910. */
  911. /* Bank 7 - LEDs and switches
  912. *
  913. * LEDs are at 0x00001 (write only)
  914. * switches are at 0x00001 (read only)
  915. */
  916. #ifdef CONFIG_SYS_LED_BASE
  917. /* BR7 is configured as follows:
  918. *
  919. * - Base address of 0xA0000000
  920. * - 8 bit port size
  921. * - Data errors checking is disabled
  922. * - Read and write access
  923. * - GPCM 60x bus
  924. * - Access are handled by the memory controller according to MSEL
  925. * - Not used for atomic operations
  926. * - No data pipelining is done
  927. * - Valid
  928. */
  929. # define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_LED_BASE & BRx_BA_MSK) |\
  930. BRx_PS_8 |\
  931. BRx_MS_GPCM_P |\
  932. BRx_V)
  933. /* OR7 is configured as follows:
  934. *
  935. * - 1 byte
  936. * - *BCTL0 is asserted upon access to the current memory bank
  937. * - *CW / *WE are negated a quarter of a clock earlier
  938. * - *CS is output at the same time as the address lines
  939. * - Uses a clock cycle length of 15
  940. * - *PSDVAL is generated internally by the memory controller
  941. * unless *GTA is asserted earlier externally.
  942. * - Relaxed timing is generated by the GPCM for accesses
  943. * initiated to this memory region.
  944. * - One idle clock is inserted between a read access from the
  945. * current bank and the next access.
  946. */
  947. # define CONFIG_SYS_OR7_PRELIM (ORxG_AM_MSK |\
  948. ORxG_CSNT |\
  949. ORxG_ACS_DIV1 |\
  950. ORxG_SCY_15_CLK |\
  951. ORxG_TRLX |\
  952. ORxG_EHTR)
  953. #endif /* CONFIG_SYS_LED_BASE */
  954. /*
  955. * Internal Definitions
  956. *
  957. * Boot Flags
  958. */
  959. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  960. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  961. #endif /* __CONFIG_H */