afeb9260.c 6.1 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian.pop@leadtechdesign.com>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include <asm/arch/at91sam9260.h>
  27. #include <asm/arch/at91sam9260_matrix.h>
  28. #include <asm/arch/at91sam9_smc.h>
  29. #include <asm/arch/at91_common.h>
  30. #include <asm/arch/at91_pmc.h>
  31. #include <asm/arch/at91_rstc.h>
  32. #include <asm/arch/gpio.h>
  33. #include <asm/arch/io.h>
  34. #include <asm/arch/hardware.h>
  35. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  36. #include <netdev.h>
  37. #include <net.h>
  38. #endif
  39. DECLARE_GLOBAL_DATA_PTR;
  40. /* ------------------------------------------------------------------------- */
  41. /*
  42. * Miscelaneous platform dependent initialisations
  43. */
  44. static void afeb9260_nand_hw_init(void)
  45. {
  46. unsigned long csa;
  47. /* Enable CS3 */
  48. csa = at91_sys_read(AT91_MATRIX_EBICSA);
  49. at91_sys_write(AT91_MATRIX_EBICSA,
  50. csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  51. /* Configure SMC CS3 for NAND/SmartMedia */
  52. at91_sys_write(AT91_SMC_SETUP(3),
  53. AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
  54. AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
  55. at91_sys_write(AT91_SMC_PULSE(3),
  56. AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  57. AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  58. at91_sys_write(AT91_SMC_CYCLE(3),
  59. AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  60. at91_sys_write(AT91_SMC_MODE(3),
  61. AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  62. AT91_SMC_EXNWMODE_DISABLE |
  63. AT91_SMC_DBW_8 |
  64. AT91_SMC_TDF_(2));
  65. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
  66. /* Configure RDY/BSY */
  67. at91_set_gpio_input(AT91_PIN_PC13, 1);
  68. /* Enable NandFlash */
  69. at91_set_gpio_output(AT91_PIN_PC14, 1);
  70. }
  71. static void afeb9260_spi_hw_init(void)
  72. {
  73. at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
  74. at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */
  75. at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
  76. at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
  77. at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
  78. /* Enable clock */
  79. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
  80. }
  81. #ifdef CONFIG_MACB
  82. static void afeb9260_macb_hw_init(void)
  83. {
  84. /* Enable clock */
  85. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
  86. /*
  87. * Disable pull-up on:
  88. * RXDV (PA17) => PHY normal mode (not Test mode)
  89. * ERX0 (PA14) => PHY ADDR0
  90. * ERX1 (PA15) => PHY ADDR1
  91. * ERX2 (PA25) => PHY ADDR2
  92. * ERX3 (PA26) => PHY ADDR3
  93. * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
  94. *
  95. * PHY has internal pull-down
  96. */
  97. writel(pin_to_mask(AT91_PIN_PA14) |
  98. pin_to_mask(AT91_PIN_PA15) |
  99. pin_to_mask(AT91_PIN_PA17) |
  100. pin_to_mask(AT91_PIN_PA25) |
  101. pin_to_mask(AT91_PIN_PA26) |
  102. pin_to_mask(AT91_PIN_PA28),
  103. pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
  104. /* Need to reset PHY -> 500ms reset */
  105. at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
  106. AT91_RSTC_ERSTL | (0x0D << 8) |
  107. AT91_RSTC_URSTEN);
  108. at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
  109. /* Wait for end hardware reset */
  110. while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
  111. /* Restore NRST value */
  112. at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
  113. AT91_RSTC_ERSTL | (0x0 << 8) |
  114. AT91_RSTC_URSTEN);
  115. /* Re-enable pull-up */
  116. writel(pin_to_mask(AT91_PIN_PA14) |
  117. pin_to_mask(AT91_PIN_PA15) |
  118. pin_to_mask(AT91_PIN_PA17) |
  119. pin_to_mask(AT91_PIN_PA25) |
  120. pin_to_mask(AT91_PIN_PA26) |
  121. pin_to_mask(AT91_PIN_PA28),
  122. pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
  123. at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
  124. at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
  125. at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
  126. at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
  127. at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
  128. at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
  129. at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
  130. at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
  131. at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
  132. at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
  133. #ifndef CONFIG_RMII
  134. at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
  135. at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
  136. at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
  137. at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
  138. at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
  139. at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
  140. at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
  141. at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
  142. #endif
  143. }
  144. #endif
  145. int board_init(void)
  146. {
  147. /* Enable Ctrlc */
  148. console_init_f();
  149. /* arch number of AT91SAM9260EK-Board */
  150. gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
  151. /* adress of boot parameters */
  152. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  153. at91_serial_hw_init();
  154. #ifdef CONFIG_CMD_NAND
  155. afeb9260_nand_hw_init();
  156. #endif
  157. afeb9260_spi_hw_init();
  158. #ifdef CONFIG_MACB
  159. afeb9260_macb_hw_init();
  160. #endif
  161. return 0;
  162. }
  163. int dram_init(void)
  164. {
  165. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  166. gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  167. return 0;
  168. }
  169. #ifdef CONFIG_RESET_PHY_R
  170. void reset_phy(void)
  171. {
  172. #ifdef CONFIG_MACB
  173. /*
  174. * Initialize ethernet HW addr prior to starting Linux,
  175. * needed for nfsroot
  176. */
  177. eth_init(gd->bd);
  178. #endif
  179. }
  180. #endif
  181. int board_eth_init(bd_t *bis)
  182. {
  183. int rc = 0;
  184. #ifdef CONFIG_MACB
  185. rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
  186. #endif
  187. return rc;
  188. }