uboot-vybrid_public/board/denx/m53evk/imximage.cfg

/*
 * DENX M53 DRAM init values
 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not write to the Free Software
 * Foundation Inc. 51 Franklin Street Fifth Floor Boston,
 * MA 02110-1301 USA
 *
 * Refer docs/README.imxmage for more details about how-to configure
 * and create imximage boot image
 *
 * The syntax is taken as close as possible with the kwbimage
 */
#include <asm/imx-common/imximage.cfg>

/* image version */
IMAGE_VERSION	2


/* Boot Offset 0x400, valid for both SD and NAND boot. */
BOOT_OFFSET	FLASH_OFFSET_STANDARD

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
 */
DATA 4 0x53fa86f4 0x00000000	 /* GRP_DDRMODE_CTL */
DATA 4 0x53fa8714 0x00000000	 /* GRP_DDRMODE */
DATA 4 0x53fa86fc 0x00000000	 /* GRP_DDRPKE */
DATA 4 0x53fa8724 0x04000000	 /* GRP_DDR_TYPE */

DATA 4 0x53fa872c 0x00300000	 /* GRP_B3DS */
DATA 4 0x53fa8554 0x00300000	 /* DRAM_DQM3 */
DATA 4 0x53fa8558 0x00300040	 /* DRAM_SDQS3 */

DATA 4 0x53fa8728 0x00300000	 /* GRP_B2DS */
DATA 4 0x53fa8560 0x00300000	 /* DRAM_DQM2 */
DATA 4 0x53fa8568 0x00300040	 /* DRAM_SDQS2 */

DATA 4 0x53fa871c 0x00300000	 /* GRP_B1DS */
DATA 4 0x53fa8594 0x00300000	 /* DRAM_DQM1 */
DATA 4 0x53fa8590 0x00300040	 /* DRAM_SDQS1 */

DATA 4 0x53fa8718 0x00300000	 /* GRP_B0DS */
DATA 4 0x53fa8584 0x00300000	 /* DRAM_DQM0 */
DATA 4 0x53fa857c 0x00300040	 /* DRAM_SDQS0 */

DATA 4 0x53fa8578 0x00300000	 /* DRAM_SDCLK_0 */
DATA 4 0x53fa8570 0x00300000	 /* DRAM_SDCLK_1 */

DATA 4 0x53fa8574 0x00300000	 /* DRAM_CAS */
DATA 4 0x53fa8588 0x00300000	 /* DRAM_RAS */
DATA 4 0x53fa86f0 0x00300000	 /* GRP_ADDDS */
DATA 4 0x53fa8720 0x00300000	 /* GRP_CTLDS */

DATA 4 0x53fa8564 0x00300040	 /* DRAM_SDODT1 */
DATA 4 0x53fa8580 0x00300040	 /* DRAM_SDODT0 */

/* ESDCTL */
DATA 4 0x63fd9088 0x32383535
DATA 4 0x63fd9090 0x40383538
DATA 4 0x63fd907c 0x0136014d
DATA 4 0x63fd9080 0x01510141

DATA 4 0x63fd9018 0x00011740
DATA 4 0x63fd9000 0xc3190000
DATA 4 0x63fd900c 0x555952e3
DATA 4 0x63fd9010 0xb68e8b63
DATA 4 0x63fd9014 0x01ff00db
DATA 4 0x63fd902c 0x000026d2
DATA 4 0x63fd9030 0x009f0e21
DATA 4 0x63fd9008 0x12273030
DATA 4 0x63fd9004 0x0002002d
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x092080b0
DATA 4 0x63fd901c 0x04008040
DATA 4 0x63fd901c 0x0000803a
DATA 4 0x63fd901c 0x0000803b
DATA 4 0x63fd901c 0x00028039
DATA 4 0x63fd901c 0x09208138
DATA 4 0x63fd901c 0x04008048
DATA 4 0x63fd9020 0x00001800
DATA 4 0x63fd9040 0x04b80003
DATA 4 0x63fd9058 0x00022227
DATA 4 0x63fd901c 0x00000000