video.c 6.8 KB

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  1. /*
  2. * video.c - run splash screen on lcd
  3. *
  4. * Copyright (c) 2007-2008 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <stdarg.h>
  9. #include <common.h>
  10. #include <config.h>
  11. #include <malloc.h>
  12. #include <asm/blackfin.h>
  13. #include <asm/mach-common/bits/dma.h>
  14. #include <i2c.h>
  15. #include <linux/types.h>
  16. #include <devices.h>
  17. int gunzip(void *, int, unsigned char *, unsigned long *);
  18. #define DMA_SIZE16 2
  19. #include <asm/mach-common/bits/ppi.h>
  20. #include <asm/mach-common/bits/timer.h>
  21. #include <asm/bfin_logo_230x230.h>
  22. #define LCD_X_RES 320 /* Horizontal Resolution */
  23. #define LCD_Y_RES 240 /* Vertical Resolution */
  24. #define LCD_BPP 24 /* Bit Per Pixel */
  25. #define LCD_PIXEL_SIZE (LCD_BPP / 8)
  26. #define DMA_BUS_SIZE 16
  27. #define LCD_CLK (12*1000*1000) /* 12MHz */
  28. #define CLOCKS_PER_PIX 3
  29. /* HS and VS timing parameters (all in number of PPI clk ticks) */
  30. #define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */
  31. #define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */
  32. #define H_PULSE 90 /* HS pulse width */
  33. #define H_START 204 /* first valid pixel */
  34. #define U_LINE 1 /* Blanking Lines */
  35. #define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
  36. #define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
  37. #define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
  38. #define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
  39. #define PPI_TX_MODE 0x2
  40. #define PPI_XFER_TYPE_11 0xC
  41. #define PPI_PORT_CFG_01 0x10
  42. #define PPI_PACK_EN 0x80
  43. #define PPI_POLS_1 0x8000
  44. /* enable and disable PPI functions */
  45. void EnablePPI(void)
  46. {
  47. *pPPI_CONTROL |= PORT_EN;
  48. }
  49. void DisablePPI(void)
  50. {
  51. *pPPI_CONTROL &= ~PORT_EN;
  52. }
  53. void Init_Ports(void)
  54. {
  55. *pPORTF_MUX &= ~PORT_x_MUX_0_MASK;
  56. *pPORTF_MUX |= PORT_x_MUX_0_FUNC_1;
  57. *pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7;
  58. *pPORTG_MUX &= ~PORT_x_MUX_1_MASK;
  59. *pPORTG_MUX |= PORT_x_MUX_1_FUNC_1;
  60. *pPORTG_FER |= PG5;
  61. }
  62. void Init_PPI(void)
  63. {
  64. *pPPI_DELAY = H_START;
  65. *pPPI_COUNT = (H_ACTPIX-1);
  66. *pPPI_FRAME = 0;
  67. /* PPI control, to be replaced with definitions */
  68. *pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */
  69. PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
  70. PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
  71. PPI_PACK_EN | /* packing enabled PACK_EN */
  72. PPI_POLS_1; /* faling edge syncs POLS */
  73. }
  74. void Init_DMA(void *dst)
  75. {
  76. *pDMA0_START_ADDR = dst;
  77. /* X count */
  78. *pDMA0_X_COUNT = H_ACTPIX / 2;
  79. *pDMA0_X_MODIFY = DMA_BUS_SIZE / 8;
  80. /* Y count */
  81. *pDMA0_Y_COUNT = V_LINES;
  82. *pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8;
  83. /* DMA Config */
  84. *pDMA0_CONFIG =
  85. WDSIZE_16 | /* 16 bit DMA */
  86. DMA2D | /* 2D DMA */
  87. FLOW_AUTO; /* autobuffer mode */
  88. }
  89. void EnableDMA(void)
  90. {
  91. *pDMA0_CONFIG |= DMAEN;
  92. }
  93. void DisableDMA(void)
  94. {
  95. *pDMA0_CONFIG &= ~DMAEN;
  96. }
  97. /* Init TIMER0 as Frame Sync 1 generator */
  98. void InitTIMER0(void)
  99. {
  100. *pTIMER_DISABLE |= TIMDIS0; /* disable Timer */
  101. SSYNC();
  102. *pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */
  103. SSYNC();
  104. *pTIMER0_PERIOD = H_PERIOD;
  105. SSYNC();
  106. *pTIMER0_WIDTH = H_PULSE;
  107. SSYNC();
  108. *pTIMER0_CONFIG = PWM_OUT |
  109. PERIOD_CNT |
  110. TIN_SEL |
  111. CLK_SEL |
  112. EMU_RUN;
  113. SSYNC();
  114. }
  115. void EnableTIMER0(void)
  116. {
  117. *pTIMER_ENABLE |= TIMEN0;
  118. SSYNC();
  119. }
  120. void DisableTIMER0(void)
  121. {
  122. *pTIMER_DISABLE |= TIMDIS0;
  123. SSYNC();
  124. }
  125. void InitTIMER1(void)
  126. {
  127. *pTIMER_DISABLE |= TIMDIS1; /* disable Timer */
  128. SSYNC();
  129. *pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */
  130. SSYNC();
  131. *pTIMER1_PERIOD = V_PERIOD;
  132. SSYNC();
  133. *pTIMER1_WIDTH = V_PULSE;
  134. SSYNC();
  135. *pTIMER1_CONFIG = PWM_OUT |
  136. PERIOD_CNT |
  137. TIN_SEL |
  138. CLK_SEL |
  139. EMU_RUN;
  140. SSYNC();
  141. }
  142. void EnableTIMER1(void)
  143. {
  144. *pTIMER_ENABLE |= TIMEN1;
  145. SSYNC();
  146. }
  147. void DisableTIMER1(void)
  148. {
  149. *pTIMER_DISABLE |= TIMDIS1;
  150. SSYNC();
  151. }
  152. int video_init(void *dst)
  153. {
  154. Init_Ports();
  155. Init_DMA(dst);
  156. EnableDMA();
  157. InitTIMER0();
  158. InitTIMER1();
  159. Init_PPI();
  160. EnablePPI();
  161. /* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
  162. EnableTIMER1();
  163. /* Add Some Delay ... */
  164. SSYNC();
  165. SSYNC();
  166. SSYNC();
  167. SSYNC();
  168. /* now start frame sync 1 */
  169. EnableTIMER0();
  170. return 0;
  171. }
  172. static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
  173. {
  174. if (dcache_status())
  175. blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
  176. bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
  177. /* Setup destination start address */
  178. bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
  179. + (y * LCD_X_RES * LCD_PIXEL_SIZE));
  180. /* Setup destination xcount */
  181. bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
  182. /* Setup destination xmodify */
  183. bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
  184. /* Setup destination ycount */
  185. bfin_write_MDMA_D0_Y_COUNT(logo->height);
  186. /* Setup destination ymodify */
  187. bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
  188. /* Setup Source start address */
  189. bfin_write_MDMA_S0_START_ADDR(logo->data);
  190. /* Setup Source xcount */
  191. bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
  192. /* Setup Source xmodify */
  193. bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
  194. /* Setup Source ycount */
  195. bfin_write_MDMA_S0_Y_COUNT(logo->height);
  196. /* Setup Source ymodify */
  197. bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
  198. /* Enable source DMA */
  199. bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
  200. SSYNC();
  201. bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
  202. while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
  203. bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
  204. bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
  205. }
  206. void video_putc(const char c)
  207. {
  208. }
  209. void video_puts(const char *s)
  210. {
  211. }
  212. int drv_video_init(void)
  213. {
  214. int error, devices = 1;
  215. device_t videodev;
  216. u8 *dst;
  217. u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
  218. dst = malloc(fbmem_size);
  219. if (dst == NULL) {
  220. printf("Failed to alloc FB memory\n");
  221. return -1;
  222. }
  223. #ifdef EASYLOGO_ENABLE_GZIP
  224. unsigned char *data = EASYLOGO_DECOMP_BUFFER;
  225. unsigned long src_len = EASYLOGO_ENABLE_GZIP;
  226. if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
  227. puts("Failed to decompress logo\n");
  228. free(dst);
  229. return -1;
  230. }
  231. bfin_logo.data = data;
  232. #endif
  233. memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
  234. dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
  235. (LCD_X_RES - bfin_logo.width) / 2,
  236. (LCD_Y_RES - bfin_logo.height) / 2);
  237. video_init(dst); /* Video initialization */
  238. memset(&videodev, 0, sizeof(videodev));
  239. strcpy(videodev.name, "video");
  240. videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
  241. videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
  242. videodev.putc = video_putc; /* 'putc' function */
  243. videodev.puts = video_puts; /* 'puts' function */
  244. error = device_register(&videodev);
  245. return (error == 0) ? devices : error;
  246. }