arm-ebi.h 2.0 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162
  1. /*
  2. * (C) Copyright 2011
  3. * Linaro
  4. * Linus Walleij <linus.walleij@linaro.org>
  5. * Register definitions for the External Bus Interface (EBI)
  6. * found in the ARM Integrator AP and CP reference designs
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #ifndef __ARM_EBI_H
  27. #define __ARM_EBI_H
  28. #define EBI_BASE 0x12000000
  29. #define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */
  30. #define EBI_CSR1_REG 0x04 /* CS1 = Flash */
  31. #define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */
  32. #define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */
  33. /*
  34. * The four upper bits are the waitstates for each chip select
  35. * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
  36. */
  37. #define EBI_CSR_WAIT_MASK 0xF0
  38. /* Whether memory is synchronous or asynchronous */
  39. #define EBI_CSR_SYNC_MASK 0xF7
  40. #define EBI_CSR_ASYNC 0x00
  41. #define EBI_CSR_SYNC 0x08
  42. /* Whether memory is write enabled or not */
  43. #define EBI_CSR_WREN_MASK 0xFB
  44. #define EBI_CSR_WREN_DISABLE 0x00
  45. #define EBI_CSR_WREN_ENABLE 0x04
  46. /* Memory bit width for each chip select */
  47. #define EBI_CSR_MEMSIZE_MASK 0xFC
  48. #define EBI_CSR_MEMSIZE_8BIT 0x00
  49. #define EBI_CSR_MEMSIZE_16BIT 0x01
  50. #define EBI_CSR_MEMSIZE_32BIT 0x02
  51. /*
  52. * The lock register need to be written with 0xa05f before anything in the
  53. * EBI can be changed.
  54. */
  55. #define EBI_LOCK_REG 0x20
  56. #define EBI_UNLOCK_MAGIC 0xA05F
  57. #endif