s3c_udc_otg.c 21 KB

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  1. /*
  2. * drivers/usb/gadget/s3c_udc_otg.c
  3. * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
  4. *
  5. * Copyright (C) 2008 for Samsung Electronics
  6. *
  7. * BSP Support for Samsung's UDC driver
  8. * available at:
  9. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10. *
  11. * State machine bugfixes:
  12. * Marek Szyprowski <m.szyprowski@samsung.com>
  13. *
  14. * Ported to u-boot:
  15. * Marek Szyprowski <m.szyprowski@samsung.com>
  16. * Lukasz Majewski <l.majewski@samsumg.com>
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License as published by
  20. * the Free Software Foundation; either version 2 of the License, or
  21. * (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  31. *
  32. */
  33. #include <common.h>
  34. #include <asm/errno.h>
  35. #include <linux/list.h>
  36. #include <malloc.h>
  37. #include <linux/usb/ch9.h>
  38. #include <linux/usb/gadget.h>
  39. #include <asm/byteorder.h>
  40. #include <asm/unaligned.h>
  41. #include <asm/io.h>
  42. #include <asm/mach-types.h>
  43. #include <asm/arch/gpio.h>
  44. #include "regs-otg.h"
  45. #include <usb/lin_gadget_compat.h>
  46. /***********************************************************/
  47. #define OTG_DMA_MODE 1
  48. #undef DEBUG_S3C_UDC_SETUP
  49. #undef DEBUG_S3C_UDC_EP0
  50. #undef DEBUG_S3C_UDC_ISR
  51. #undef DEBUG_S3C_UDC_OUT_EP
  52. #undef DEBUG_S3C_UDC_IN_EP
  53. #undef DEBUG_S3C_UDC
  54. /* #define DEBUG_S3C_UDC_SETUP */
  55. /* #define DEBUG_S3C_UDC_EP0 */
  56. /* #define DEBUG_S3C_UDC_ISR */
  57. /* #define DEBUG_S3C_UDC_OUT_EP */
  58. /* #define DEBUG_S3C_UDC_IN_EP */
  59. /* #define DEBUG_S3C_UDC */
  60. #include <usb/s3c_udc.h>
  61. #define EP0_CON 0
  62. #define EP_MASK 0xF
  63. static char *state_names[] = {
  64. "WAIT_FOR_SETUP",
  65. "DATA_STATE_XMIT",
  66. "DATA_STATE_NEED_ZLP",
  67. "WAIT_FOR_OUT_STATUS",
  68. "DATA_STATE_RECV",
  69. "WAIT_FOR_COMPLETE",
  70. "WAIT_FOR_OUT_COMPLETE",
  71. "WAIT_FOR_IN_COMPLETE",
  72. "WAIT_FOR_NULL_COMPLETE",
  73. };
  74. #define DRIVER_DESC "S3C HS USB OTG Device Driver, (c) Samsung Electronics"
  75. #define DRIVER_VERSION "15 March 2009"
  76. struct s3c_udc *the_controller;
  77. static const char driver_name[] = "s3c-udc";
  78. static const char driver_desc[] = DRIVER_DESC;
  79. static const char ep0name[] = "ep0-control";
  80. /* Max packet size*/
  81. static unsigned int ep0_fifo_size = 64;
  82. static unsigned int ep_fifo_size = 512;
  83. static unsigned int ep_fifo_size2 = 1024;
  84. static int reset_available = 1;
  85. static struct usb_ctrlrequest *usb_ctrl;
  86. static dma_addr_t usb_ctrl_dma_addr;
  87. /*
  88. Local declarations.
  89. */
  90. static int s3c_ep_enable(struct usb_ep *ep,
  91. const struct usb_endpoint_descriptor *);
  92. static int s3c_ep_disable(struct usb_ep *ep);
  93. static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
  94. gfp_t gfp_flags);
  95. static void s3c_free_request(struct usb_ep *ep, struct usb_request *);
  96. static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
  97. static int s3c_dequeue(struct usb_ep *ep, struct usb_request *);
  98. static int s3c_fifo_status(struct usb_ep *ep);
  99. static void s3c_fifo_flush(struct usb_ep *ep);
  100. static void s3c_ep0_read(struct s3c_udc *dev);
  101. static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep);
  102. static void s3c_handle_ep0(struct s3c_udc *dev);
  103. static int s3c_ep0_write(struct s3c_udc *dev);
  104. static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req);
  105. static void done(struct s3c_ep *ep, struct s3c_request *req, int status);
  106. static void stop_activity(struct s3c_udc *dev,
  107. struct usb_gadget_driver *driver);
  108. static int udc_enable(struct s3c_udc *dev);
  109. static void udc_set_address(struct s3c_udc *dev, unsigned char address);
  110. static void reconfig_usbd(void);
  111. static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
  112. static void nuke(struct s3c_ep *ep, int status);
  113. static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
  114. static void s3c_udc_set_nak(struct s3c_ep *ep);
  115. static struct usb_ep_ops s3c_ep_ops = {
  116. .enable = s3c_ep_enable,
  117. .disable = s3c_ep_disable,
  118. .alloc_request = s3c_alloc_request,
  119. .free_request = s3c_free_request,
  120. .queue = s3c_queue,
  121. .dequeue = s3c_dequeue,
  122. .set_halt = s3c_udc_set_halt,
  123. .fifo_status = s3c_fifo_status,
  124. .fifo_flush = s3c_fifo_flush,
  125. };
  126. #define create_proc_files() do {} while (0)
  127. #define remove_proc_files() do {} while (0)
  128. /***********************************************************/
  129. void __iomem *regs_otg;
  130. struct s3c_usbotg_reg *reg;
  131. struct s3c_usbotg_phy *phy;
  132. static unsigned int usb_phy_ctrl;
  133. void otg_phy_init(struct s3c_udc *dev)
  134. {
  135. dev->pdata->phy_control(1);
  136. /*USB PHY0 Enable */
  137. printf("USB PHY0 Enable\n");
  138. /* Enable PHY */
  139. writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
  140. if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
  141. writel((readl(&phy->phypwr)
  142. &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
  143. &~FORCE_SUSPEND_0), &phy->phypwr);
  144. else /* C110 GONI */
  145. writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
  146. &~FORCE_SUSPEND_0), &phy->phypwr);
  147. writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
  148. CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
  149. writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
  150. | PHY_SW_RST0, &phy->rstcon);
  151. udelay(10);
  152. writel(readl(&phy->rstcon)
  153. &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
  154. udelay(10);
  155. }
  156. void otg_phy_off(struct s3c_udc *dev)
  157. {
  158. /* reset controller just in case */
  159. writel(PHY_SW_RST0, &phy->rstcon);
  160. udelay(20);
  161. writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
  162. udelay(20);
  163. writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
  164. | FORCE_SUSPEND_0, &phy->phypwr);
  165. writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
  166. writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
  167. &phy->phyclk);
  168. udelay(10000);
  169. dev->pdata->phy_control(0);
  170. }
  171. /***********************************************************/
  172. #include "s3c_udc_otg_xfer_dma.c"
  173. /*
  174. * udc_disable - disable USB device controller
  175. */
  176. static void udc_disable(struct s3c_udc *dev)
  177. {
  178. DEBUG_SETUP("%s: %p\n", __func__, dev);
  179. udc_set_address(dev, 0);
  180. dev->ep0state = WAIT_FOR_SETUP;
  181. dev->gadget.speed = USB_SPEED_UNKNOWN;
  182. dev->usb_address = 0;
  183. otg_phy_off(dev);
  184. }
  185. /*
  186. * udc_reinit - initialize software state
  187. */
  188. static void udc_reinit(struct s3c_udc *dev)
  189. {
  190. unsigned int i;
  191. DEBUG_SETUP("%s: %p\n", __func__, dev);
  192. /* device/ep0 records init */
  193. INIT_LIST_HEAD(&dev->gadget.ep_list);
  194. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  195. dev->ep0state = WAIT_FOR_SETUP;
  196. /* basic endpoint records init */
  197. for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
  198. struct s3c_ep *ep = &dev->ep[i];
  199. if (i != 0)
  200. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  201. ep->desc = 0;
  202. ep->stopped = 0;
  203. INIT_LIST_HEAD(&ep->queue);
  204. ep->pio_irqs = 0;
  205. }
  206. /* the rest was statically initialized, and is read-only */
  207. }
  208. #define BYTES2MAXP(x) (x / 8)
  209. #define MAXP2BYTES(x) (x * 8)
  210. /* until it's enabled, this UDC should be completely invisible
  211. * to any USB host.
  212. */
  213. static int udc_enable(struct s3c_udc *dev)
  214. {
  215. DEBUG_SETUP("%s: %p\n", __func__, dev);
  216. otg_phy_init(dev);
  217. reconfig_usbd();
  218. DEBUG_SETUP("S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
  219. readl(&reg->gintmsk));
  220. dev->gadget.speed = USB_SPEED_UNKNOWN;
  221. return 0;
  222. }
  223. /*
  224. Register entry point for the peripheral controller driver.
  225. */
  226. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  227. {
  228. struct s3c_udc *dev = the_controller;
  229. int retval = 0;
  230. unsigned long flags;
  231. DEBUG_SETUP("%s: %s\n", __func__, "no name");
  232. if (!driver
  233. || (driver->speed != USB_SPEED_FULL
  234. && driver->speed != USB_SPEED_HIGH)
  235. || !driver->bind || !driver->disconnect || !driver->setup)
  236. return -EINVAL;
  237. if (!dev)
  238. return -ENODEV;
  239. if (dev->driver)
  240. return -EBUSY;
  241. spin_lock_irqsave(&dev->lock, flags);
  242. /* first hook up the driver ... */
  243. dev->driver = driver;
  244. spin_unlock_irqrestore(&dev->lock, flags);
  245. if (retval) { /* TODO */
  246. printf("target device_add failed, error %d\n", retval);
  247. return retval;
  248. }
  249. retval = driver->bind(&dev->gadget);
  250. if (retval) {
  251. DEBUG_SETUP("%s: bind to driver --> error %d\n",
  252. dev->gadget.name, retval);
  253. dev->driver = 0;
  254. return retval;
  255. }
  256. enable_irq(IRQ_OTG);
  257. DEBUG_SETUP("Registered gadget driver %s\n", dev->gadget.name);
  258. udc_enable(dev);
  259. return 0;
  260. }
  261. /*
  262. * Unregister entry point for the peripheral controller driver.
  263. */
  264. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  265. {
  266. struct s3c_udc *dev = the_controller;
  267. unsigned long flags;
  268. if (!dev)
  269. return -ENODEV;
  270. if (!driver || driver != dev->driver)
  271. return -EINVAL;
  272. spin_lock_irqsave(&dev->lock, flags);
  273. dev->driver = 0;
  274. stop_activity(dev, driver);
  275. spin_unlock_irqrestore(&dev->lock, flags);
  276. driver->unbind(&dev->gadget);
  277. disable_irq(IRQ_OTG);
  278. udc_disable(dev);
  279. return 0;
  280. }
  281. /*
  282. * done - retire a request; caller blocked irqs
  283. */
  284. static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
  285. {
  286. unsigned int stopped = ep->stopped;
  287. debug("%s: %s %p, req = %p, stopped = %d\n",
  288. __func__, ep->ep.name, ep, &req->req, stopped);
  289. list_del_init(&req->queue);
  290. if (likely(req->req.status == -EINPROGRESS))
  291. req->req.status = status;
  292. else
  293. status = req->req.status;
  294. if (status && status != -ESHUTDOWN) {
  295. debug("complete %s req %p stat %d len %u/%u\n",
  296. ep->ep.name, &req->req, status,
  297. req->req.actual, req->req.length);
  298. }
  299. /* don't modify queue heads during completion callback */
  300. ep->stopped = 1;
  301. #ifdef DEBUG_S3C_UDC
  302. printf("calling complete callback\n");
  303. {
  304. int i, len = req->req.length;
  305. printf("pkt[%d] = ", req->req.length);
  306. if (len > 64)
  307. len = 64;
  308. for (i = 0; i < len; i++) {
  309. printf("%02x", ((u8 *)req->req.buf)[i]);
  310. if ((i & 7) == 7)
  311. printf(" ");
  312. }
  313. printf("\n");
  314. }
  315. #endif
  316. spin_unlock(&ep->dev->lock);
  317. req->req.complete(&ep->ep, &req->req);
  318. spin_lock(&ep->dev->lock);
  319. debug("callback completed\n");
  320. ep->stopped = stopped;
  321. }
  322. /*
  323. * nuke - dequeue ALL requests
  324. */
  325. static void nuke(struct s3c_ep *ep, int status)
  326. {
  327. struct s3c_request *req;
  328. debug("%s: %s %p\n", __func__, ep->ep.name, ep);
  329. /* called with irqs blocked */
  330. while (!list_empty(&ep->queue)) {
  331. req = list_entry(ep->queue.next, struct s3c_request, queue);
  332. done(ep, req, status);
  333. }
  334. }
  335. static void stop_activity(struct s3c_udc *dev,
  336. struct usb_gadget_driver *driver)
  337. {
  338. int i;
  339. /* don't disconnect drivers more than once */
  340. if (dev->gadget.speed == USB_SPEED_UNKNOWN)
  341. driver = 0;
  342. dev->gadget.speed = USB_SPEED_UNKNOWN;
  343. /* prevent new request submissions, kill any outstanding requests */
  344. for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
  345. struct s3c_ep *ep = &dev->ep[i];
  346. ep->stopped = 1;
  347. nuke(ep, -ESHUTDOWN);
  348. }
  349. /* report disconnect; the driver is already quiesced */
  350. if (driver) {
  351. spin_unlock(&dev->lock);
  352. driver->disconnect(&dev->gadget);
  353. spin_lock(&dev->lock);
  354. }
  355. /* re-init driver-visible data structures */
  356. udc_reinit(dev);
  357. }
  358. static void reconfig_usbd(void)
  359. {
  360. /* 2. Soft-reset OTG Core and then unreset again. */
  361. int i;
  362. unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
  363. debug("Reseting OTG controller\n");
  364. writel(0<<15 /* PHY Low Power Clock sel*/
  365. |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
  366. |0x5<<10 /* Turnaround time*/
  367. |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
  368. /* 1:SRP enable] H1= 1,1*/
  369. |0<<7 /* Ulpi DDR sel*/
  370. |0<<6 /* 0: high speed utmi+, 1: full speed serial*/
  371. |0<<4 /* 0: utmi+, 1:ulpi*/
  372. |1<<3 /* phy i/f 0:8bit, 1:16bit*/
  373. |0x7<<0, /* HS/FS Timeout**/
  374. &reg->gusbcfg);
  375. /* 3. Put the OTG device core in the disconnected state.*/
  376. uTemp = readl(&reg->dctl);
  377. uTemp |= SOFT_DISCONNECT;
  378. writel(uTemp, &reg->dctl);
  379. udelay(20);
  380. /* 4. Make the OTG device core exit from the disconnected state.*/
  381. uTemp = readl(&reg->dctl);
  382. uTemp = uTemp & ~SOFT_DISCONNECT;
  383. writel(uTemp, &reg->dctl);
  384. /* 5. Configure OTG Core to initial settings of device mode.*/
  385. /* [][1: full speed(30Mhz) 0:high speed]*/
  386. writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->dcfg);
  387. mdelay(1);
  388. /* 6. Unmask the core interrupts*/
  389. writel(GINTMSK_INIT, &reg->gintmsk);
  390. /* 7. Set NAK bit of EP0, EP1, EP2*/
  391. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
  392. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
  393. for (i = 1; i < S3C_MAX_ENDPOINTS; i++) {
  394. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
  395. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
  396. }
  397. /* 8. Unmask EPO interrupts*/
  398. writel(((1 << EP0_CON) << DAINT_OUT_BIT)
  399. | (1 << EP0_CON), &reg->daintmsk);
  400. /* 9. Unmask device OUT EP common interrupts*/
  401. writel(DOEPMSK_INIT, &reg->doepmsk);
  402. /* 10. Unmask device IN EP common interrupts*/
  403. writel(DIEPMSK_INIT, &reg->diepmsk);
  404. /* 11. Set Rx FIFO Size (in 32-bit words) */
  405. writel(RX_FIFO_SIZE >> 2, &reg->grxfsiz);
  406. /* 12. Set Non Periodic Tx FIFO Size */
  407. writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
  408. &reg->gnptxfsiz);
  409. for (i = 1; i < S3C_MAX_HW_ENDPOINTS; i++)
  410. writel((PTX_FIFO_SIZE >> 2) << 16 |
  411. ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
  412. PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
  413. &reg->dieptxf[i-1]);
  414. /* Flush the RX FIFO */
  415. writel(RX_FIFO_FLUSH, &reg->grstctl);
  416. while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
  417. debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
  418. /* Flush all the Tx FIFO's */
  419. writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
  420. writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
  421. while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
  422. debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
  423. /* 13. Clear NAK bit of EP0, EP1, EP2*/
  424. /* For Slave mode*/
  425. /* EP0: Control OUT */
  426. writel(DEPCTL_EPDIS | DEPCTL_CNAK,
  427. &reg->out_endp[EP0_CON].doepctl);
  428. /* 14. Initialize OTG Link Core.*/
  429. writel(GAHBCFG_INIT, &reg->gahbcfg);
  430. }
  431. static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed)
  432. {
  433. unsigned int ep_ctrl;
  434. int i;
  435. if (speed == USB_SPEED_HIGH) {
  436. ep0_fifo_size = 64;
  437. ep_fifo_size = 512;
  438. ep_fifo_size2 = 1024;
  439. dev->gadget.speed = USB_SPEED_HIGH;
  440. } else {
  441. ep0_fifo_size = 64;
  442. ep_fifo_size = 64;
  443. ep_fifo_size2 = 64;
  444. dev->gadget.speed = USB_SPEED_FULL;
  445. }
  446. dev->ep[0].ep.maxpacket = ep0_fifo_size;
  447. for (i = 1; i < S3C_MAX_ENDPOINTS; i++)
  448. dev->ep[i].ep.maxpacket = ep_fifo_size;
  449. /* EP0 - Control IN (64 bytes)*/
  450. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  451. writel(ep_ctrl|(0<<0), &reg->in_endp[EP0_CON].diepctl);
  452. /* EP0 - Control OUT (64 bytes)*/
  453. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  454. writel(ep_ctrl|(0<<0), &reg->out_endp[EP0_CON].doepctl);
  455. }
  456. static int s3c_ep_enable(struct usb_ep *_ep,
  457. const struct usb_endpoint_descriptor *desc)
  458. {
  459. struct s3c_ep *ep;
  460. struct s3c_udc *dev;
  461. unsigned long flags;
  462. debug("%s: %p\n", __func__, _ep);
  463. ep = container_of(_ep, struct s3c_ep, ep);
  464. if (!_ep || !desc || ep->desc || _ep->name == ep0name
  465. || desc->bDescriptorType != USB_DT_ENDPOINT
  466. || ep->bEndpointAddress != desc->bEndpointAddress
  467. || ep_maxpacket(ep) <
  468. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
  469. debug("%s: bad ep or descriptor\n", __func__);
  470. return -EINVAL;
  471. }
  472. /* xfer types must match, except that interrupt ~= bulk */
  473. if (ep->bmAttributes != desc->bmAttributes
  474. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  475. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  476. debug("%s: %s type mismatch\n", __func__, _ep->name);
  477. return -EINVAL;
  478. }
  479. /* hardware _could_ do smaller, but driver doesn't */
  480. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
  481. && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) !=
  482. ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
  483. debug("%s: bad %s maxpacket\n", __func__, _ep->name);
  484. return -ERANGE;
  485. }
  486. dev = ep->dev;
  487. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
  488. debug("%s: bogus device state\n", __func__);
  489. return -ESHUTDOWN;
  490. }
  491. ep->stopped = 0;
  492. ep->desc = desc;
  493. ep->pio_irqs = 0;
  494. ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
  495. /* Reset halt state */
  496. s3c_udc_set_nak(ep);
  497. s3c_udc_set_halt(_ep, 0);
  498. spin_lock_irqsave(&ep->dev->lock, flags);
  499. s3c_udc_ep_activate(ep);
  500. spin_unlock_irqrestore(&ep->dev->lock, flags);
  501. debug("%s: enabled %s, stopped = %d, maxpacket = %d\n",
  502. __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
  503. return 0;
  504. }
  505. /*
  506. * Disable EP
  507. */
  508. static int s3c_ep_disable(struct usb_ep *_ep)
  509. {
  510. struct s3c_ep *ep;
  511. unsigned long flags;
  512. debug("%s: %p\n", __func__, _ep);
  513. ep = container_of(_ep, struct s3c_ep, ep);
  514. if (!_ep || !ep->desc) {
  515. debug("%s: %s not enabled\n", __func__,
  516. _ep ? ep->ep.name : NULL);
  517. return -EINVAL;
  518. }
  519. spin_lock_irqsave(&ep->dev->lock, flags);
  520. /* Nuke all pending requests */
  521. nuke(ep, -ESHUTDOWN);
  522. ep->desc = 0;
  523. ep->stopped = 1;
  524. spin_unlock_irqrestore(&ep->dev->lock, flags);
  525. debug("%s: disabled %s\n", __func__, _ep->name);
  526. return 0;
  527. }
  528. static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
  529. gfp_t gfp_flags)
  530. {
  531. struct s3c_request *req;
  532. debug("%s: %s %p\n", __func__, ep->name, ep);
  533. req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req));
  534. if (!req)
  535. return 0;
  536. memset(req, 0, sizeof *req);
  537. INIT_LIST_HEAD(&req->queue);
  538. return &req->req;
  539. }
  540. static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req)
  541. {
  542. struct s3c_request *req;
  543. debug("%s: %p\n", __func__, ep);
  544. req = container_of(_req, struct s3c_request, req);
  545. WARN_ON(!list_empty(&req->queue));
  546. kfree(req);
  547. }
  548. /* dequeue JUST ONE request */
  549. static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  550. {
  551. struct s3c_ep *ep;
  552. struct s3c_request *req;
  553. unsigned long flags;
  554. debug("%s: %p\n", __func__, _ep);
  555. ep = container_of(_ep, struct s3c_ep, ep);
  556. if (!_ep || ep->ep.name == ep0name)
  557. return -EINVAL;
  558. spin_lock_irqsave(&ep->dev->lock, flags);
  559. /* make sure it's actually queued on this endpoint */
  560. list_for_each_entry(req, &ep->queue, queue) {
  561. if (&req->req == _req)
  562. break;
  563. }
  564. if (&req->req != _req) {
  565. spin_unlock_irqrestore(&ep->dev->lock, flags);
  566. return -EINVAL;
  567. }
  568. done(ep, req, -ECONNRESET);
  569. spin_unlock_irqrestore(&ep->dev->lock, flags);
  570. return 0;
  571. }
  572. /*
  573. * Return bytes in EP FIFO
  574. */
  575. static int s3c_fifo_status(struct usb_ep *_ep)
  576. {
  577. int count = 0;
  578. struct s3c_ep *ep;
  579. ep = container_of(_ep, struct s3c_ep, ep);
  580. if (!_ep) {
  581. debug("%s: bad ep\n", __func__);
  582. return -ENODEV;
  583. }
  584. debug("%s: %d\n", __func__, ep_index(ep));
  585. /* LPD can't report unclaimed bytes from IN fifos */
  586. if (ep_is_in(ep))
  587. return -EOPNOTSUPP;
  588. return count;
  589. }
  590. /*
  591. * Flush EP FIFO
  592. */
  593. static void s3c_fifo_flush(struct usb_ep *_ep)
  594. {
  595. struct s3c_ep *ep;
  596. ep = container_of(_ep, struct s3c_ep, ep);
  597. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  598. debug("%s: bad ep\n", __func__);
  599. return;
  600. }
  601. debug("%s: %d\n", __func__, ep_index(ep));
  602. }
  603. static const struct usb_gadget_ops s3c_udc_ops = {
  604. /* current versions must always be self-powered */
  605. };
  606. static struct s3c_udc memory = {
  607. .usb_address = 0,
  608. .gadget = {
  609. .ops = &s3c_udc_ops,
  610. .ep0 = &memory.ep[0].ep,
  611. .name = driver_name,
  612. },
  613. /* control endpoint */
  614. .ep[0] = {
  615. .ep = {
  616. .name = ep0name,
  617. .ops = &s3c_ep_ops,
  618. .maxpacket = EP0_FIFO_SIZE,
  619. },
  620. .dev = &memory,
  621. .bEndpointAddress = 0,
  622. .bmAttributes = 0,
  623. .ep_type = ep_control,
  624. },
  625. /* first group of endpoints */
  626. .ep[1] = {
  627. .ep = {
  628. .name = "ep1in-bulk",
  629. .ops = &s3c_ep_ops,
  630. .maxpacket = EP_FIFO_SIZE,
  631. },
  632. .dev = &memory,
  633. .bEndpointAddress = USB_DIR_IN | 1,
  634. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  635. .ep_type = ep_bulk_out,
  636. .fifo_num = 1,
  637. },
  638. .ep[2] = {
  639. .ep = {
  640. .name = "ep2out-bulk",
  641. .ops = &s3c_ep_ops,
  642. .maxpacket = EP_FIFO_SIZE,
  643. },
  644. .dev = &memory,
  645. .bEndpointAddress = USB_DIR_OUT | 2,
  646. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  647. .ep_type = ep_bulk_in,
  648. .fifo_num = 2,
  649. },
  650. .ep[3] = {
  651. .ep = {
  652. .name = "ep3in-int",
  653. .ops = &s3c_ep_ops,
  654. .maxpacket = EP_FIFO_SIZE,
  655. },
  656. .dev = &memory,
  657. .bEndpointAddress = USB_DIR_IN | 3,
  658. .bmAttributes = USB_ENDPOINT_XFER_INT,
  659. .ep_type = ep_interrupt,
  660. .fifo_num = 3,
  661. },
  662. };
  663. /*
  664. * probe - binds to the platform device
  665. */
  666. int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
  667. {
  668. struct s3c_udc *dev = &memory;
  669. int retval = 0, i;
  670. debug("%s: %p\n", __func__, pdata);
  671. dev->pdata = pdata;
  672. phy = (struct s3c_usbotg_phy *)pdata->regs_phy;
  673. reg = (struct s3c_usbotg_reg *)pdata->regs_otg;
  674. usb_phy_ctrl = pdata->usb_phy_ctrl;
  675. /* regs_otg = (void *)pdata->regs_otg; */
  676. dev->gadget.is_dualspeed = 1; /* Hack only*/
  677. dev->gadget.is_otg = 0;
  678. dev->gadget.is_a_peripheral = 0;
  679. dev->gadget.b_hnp_enable = 0;
  680. dev->gadget.a_hnp_support = 0;
  681. dev->gadget.a_alt_hnp_support = 0;
  682. the_controller = dev;
  683. for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) {
  684. dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE,
  685. DMA_BUFFER_SIZE);
  686. dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i];
  687. invalidate_dcache_range((unsigned long) dev->dma_buf[i],
  688. (unsigned long) (dev->dma_buf[i]
  689. + DMA_BUFFER_SIZE));
  690. }
  691. usb_ctrl = dev->dma_buf[0];
  692. usb_ctrl_dma_addr = dev->dma_addr[0];
  693. udc_reinit(dev);
  694. return retval;
  695. }
  696. int usb_gadget_handle_interrupts()
  697. {
  698. u32 intr_status = readl(&reg->gintsts);
  699. u32 gintmsk = readl(&reg->gintmsk);
  700. if (intr_status & gintmsk)
  701. return s3c_udc_irq(1, (void *)the_controller);
  702. return 0;
  703. }