fsl_upm.c 4.2 KB

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  1. /*
  2. * FSL UPM NAND driver
  3. *
  4. * Copyright (C) 2007 MontaVista Software, Inc.
  5. * Anton Vorontsov <avorontsov@ru.mvista.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. */
  12. #include <config.h>
  13. #include <common.h>
  14. #include <asm/io.h>
  15. #include <asm/errno.h>
  16. #include <linux/mtd/mtd.h>
  17. #include <linux/mtd/fsl_upm.h>
  18. #include <nand.h>
  19. static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset)
  20. {
  21. clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset);
  22. }
  23. static void fsl_upm_end_pattern(struct fsl_upm *upm)
  24. {
  25. clrbits_be32(upm->mxmr, MxMR_OP_RUNP);
  26. while (in_be32(upm->mxmr) & MxMR_OP_RUNP)
  27. eieio();
  28. }
  29. static void fsl_upm_run_pattern(struct fsl_upm *upm, int width,
  30. void __iomem *io_addr, u32 mar)
  31. {
  32. out_be32(upm->mar, mar);
  33. switch (width) {
  34. case 8:
  35. out_8(io_addr, 0x0);
  36. break;
  37. case 16:
  38. out_be16(io_addr, 0x0);
  39. break;
  40. case 32:
  41. out_be32(io_addr, 0x0);
  42. break;
  43. }
  44. }
  45. #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  46. static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
  47. {
  48. struct nand_chip *chip = mtd->priv;
  49. struct fsl_upm_nand *fun = chip->priv;
  50. if (chip_nr >= 0) {
  51. fun->chip_nr = chip_nr;
  52. chip->IO_ADDR_R = chip->IO_ADDR_W =
  53. fun->upm.io_addr + fun->chip_offset * chip_nr;
  54. } else if (chip_nr == -1) {
  55. chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  56. }
  57. }
  58. #endif
  59. static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  60. {
  61. struct nand_chip *chip = mtd->priv;
  62. struct fsl_upm_nand *fun = chip->priv;
  63. void __iomem *io_addr;
  64. u32 mar;
  65. if (!(ctrl & fun->last_ctrl)) {
  66. fsl_upm_end_pattern(&fun->upm);
  67. if (cmd == NAND_CMD_NONE)
  68. return;
  69. fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
  70. }
  71. if (ctrl & NAND_CTRL_CHANGE) {
  72. if (ctrl & NAND_ALE)
  73. fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
  74. else if (ctrl & NAND_CLE)
  75. fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
  76. }
  77. mar = cmd << (32 - fun->width);
  78. io_addr = fun->upm.io_addr;
  79. #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  80. if (fun->chip_nr > 0) {
  81. io_addr += fun->chip_offset * fun->chip_nr;
  82. if (fun->upm_mar_chip_offset)
  83. mar |= fun->upm_mar_chip_offset * fun->chip_nr;
  84. }
  85. #endif
  86. fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
  87. /*
  88. * Some boards/chips needs this. At least on MPC8360E-RDK we
  89. * need it. Probably weird chip, because I don't see any need
  90. * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are
  91. * 0-2 unexpected busy states per block read.
  92. */
  93. if (fun->wait_pattern) {
  94. while (!fun->dev_ready(fun->chip_nr))
  95. debug("unexpected busy state\n");
  96. }
  97. }
  98. static u8 nand_read_byte(struct mtd_info *mtd)
  99. {
  100. struct nand_chip *chip = mtd->priv;
  101. return in_8(chip->IO_ADDR_R);
  102. }
  103. static void nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
  104. {
  105. int i;
  106. struct nand_chip *chip = mtd->priv;
  107. for (i = 0; i < len; i++)
  108. out_8(chip->IO_ADDR_W, buf[i]);
  109. }
  110. static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  111. {
  112. int i;
  113. struct nand_chip *chip = mtd->priv;
  114. for (i = 0; i < len; i++)
  115. buf[i] = in_8(chip->IO_ADDR_R);
  116. }
  117. static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
  118. {
  119. int i;
  120. struct nand_chip *chip = mtd->priv;
  121. for (i = 0; i < len; i++) {
  122. if (buf[i] != in_8(chip->IO_ADDR_R))
  123. return -EFAULT;
  124. }
  125. return 0;
  126. }
  127. static int nand_dev_ready(struct mtd_info *mtd)
  128. {
  129. struct nand_chip *chip = mtd->priv;
  130. struct fsl_upm_nand *fun = chip->priv;
  131. return fun->dev_ready(fun->chip_nr);
  132. }
  133. int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
  134. {
  135. if (fun->width != 8 && fun->width != 16 && fun->width != 32)
  136. return -ENOSYS;
  137. fun->last_ctrl = NAND_CLE;
  138. chip->priv = fun;
  139. chip->chip_delay = fun->chip_delay;
  140. chip->ecc.mode = NAND_ECC_SOFT;
  141. chip->cmd_ctrl = fun_cmd_ctrl;
  142. #if CONFIG_SYS_NAND_MAX_CHIPS > 1
  143. chip->select_chip = fun_select_chip;
  144. #endif
  145. chip->read_byte = nand_read_byte;
  146. chip->read_buf = nand_read_buf;
  147. chip->write_buf = nand_write_buf;
  148. chip->verify_buf = nand_verify_buf;
  149. if (fun->dev_ready)
  150. chip->dev_ready = nand_dev_ready;
  151. return 0;
  152. }