gdsys_fpga.h 3.4 KB

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  1. /*
  2. * (C) Copyright 2010
  3. * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __GDSYS_FPGA_H
  24. #define __GDSYS_FPGA_H
  25. int init_func_fpga(void);
  26. enum {
  27. FPGA_STATE_DONE_FAILED = 1 << 0,
  28. FPGA_STATE_REFLECTION_FAILED = 1 << 1,
  29. FPGA_STATE_PLATFORM = 1 << 2,
  30. };
  31. int get_fpga_state(unsigned dev);
  32. void print_fpga_state(unsigned dev);
  33. typedef struct ihs_gpio {
  34. u16 read;
  35. u16 clear;
  36. u16 set;
  37. } ihs_gpio_t;
  38. typedef struct ihs_i2c {
  39. u16 write_mailbox;
  40. u16 write_mailbox_ext;
  41. u16 read_mailbox;
  42. u16 read_mailbox_ext;
  43. } ihs_i2c_t;
  44. typedef struct ihs_osd {
  45. u16 version;
  46. u16 features;
  47. u16 control;
  48. u16 xy_size;
  49. u16 xy_scale;
  50. u16 x_pos;
  51. u16 y_pos;
  52. } ihs_osd_t;
  53. #ifdef CONFIG_IO
  54. typedef struct ihs_fpga {
  55. u16 reflection_low; /* 0x0000 */
  56. u16 versions; /* 0x0002 */
  57. u16 fpga_features; /* 0x0004 */
  58. u16 fpga_version; /* 0x0006 */
  59. u16 reserved_0[5]; /* 0x0008 */
  60. u16 quad_serdes_reset; /* 0x0012 */
  61. u16 reserved_1[8181]; /* 0x0014 */
  62. u16 reflection_high; /* 0x3ffe */
  63. } ihs_fpga_t;
  64. #endif
  65. #ifdef CONFIG_IO64
  66. typedef struct ihs_fpga {
  67. u16 reflection_low; /* 0x0000 */
  68. u16 versions; /* 0x0002 */
  69. u16 fpga_features; /* 0x0004 */
  70. u16 fpga_version; /* 0x0006 */
  71. u16 reserved_0[5]; /* 0x0008 */
  72. u16 quad_serdes_reset; /* 0x0012 */
  73. u16 reserved_1[502]; /* 0x0014 */
  74. u16 ch0_status_int; /* 0x0400 */
  75. u16 ch0_config_int; /* 0x0402 */
  76. u16 reserved_2[126]; /* 0x0404 */
  77. u16 ch0_hicb_status_int;/* 0x0500 */
  78. u16 ch0_hicb_config_int;/* 0x0502 */
  79. u16 reserved_3[7549]; /* 0x0504 */
  80. u16 reflection_high; /* 0x3ffe */
  81. } ihs_fpga_t;
  82. #endif
  83. #ifdef CONFIG_IOCON
  84. typedef struct ihs_fpga {
  85. u16 reflection_low; /* 0x0000 */
  86. u16 versions; /* 0x0002 */
  87. u16 fpga_version; /* 0x0004 */
  88. u16 fpga_features; /* 0x0006 */
  89. u16 reserved_0[6]; /* 0x0008 */
  90. ihs_gpio_t gpio; /* 0x0014 */
  91. u16 mpc3w_control; /* 0x001a */
  92. u16 reserved_1[19]; /* 0x001c */
  93. u16 videocontrol; /* 0x0042 */
  94. u16 reserved_2[93]; /* 0x0044 */
  95. u16 reflection_high; /* 0x00fe */
  96. ihs_osd_t osd; /* 0x0100 */
  97. u16 reserved_3[88]; /* 0x010e */
  98. u16 videomem; /* 0x0800 */
  99. } ihs_fpga_t;
  100. #endif
  101. #ifdef CONFIG_DLVISION_10G
  102. typedef struct ihs_fpga {
  103. u16 reflection_low; /* 0x0000 */
  104. u16 versions; /* 0x0002 */
  105. u16 fpga_version; /* 0x0004 */
  106. u16 fpga_features; /* 0x0006 */
  107. u16 reserved_0[10]; /* 0x0008 */
  108. u16 extended_interrupt; /* 0x001c */
  109. u16 reserved_1[9]; /* 0x001e */
  110. ihs_i2c_t i2c; /* 0x0030 */
  111. u16 reserved_2[16]; /* 0x0038 */
  112. u16 mpc3w_control; /* 0x0058 */
  113. u16 reserved_3[34]; /* 0x005a */
  114. u16 videocontrol; /* 0x009e */
  115. u16 reserved_4[176]; /* 0x00a0 */
  116. ihs_osd_t osd; /* 0x0200 */
  117. u16 reserved_5[761]; /* 0x020e */
  118. u16 videomem; /* 0x0800 */
  119. } ihs_fpga_t;
  120. #endif
  121. #endif