da830evm.c 8.4 KB

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  1. /*
  2. * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
  3. *
  4. * Base on code from TI. Original Notices follow:
  5. *
  6. * (C) Copyright 2008, Texas Instruments, Inc. http://www.ti.com/
  7. *
  8. * Modified for DA8xx EVM.
  9. *
  10. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  11. *
  12. * Parts are shamelessly stolen from various TI sources, original copyright
  13. * follows:
  14. * -----------------------------------------------------------------
  15. *
  16. * Copyright (C) 2004 Texas Instruments.
  17. *
  18. * ----------------------------------------------------------------------------
  19. * This program is free software; you can redistribute it and/or modify
  20. * it under the terms of the GNU General Public License as published by
  21. * the Free Software Foundation; either version 2 of the License, or
  22. * (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  32. * ----------------------------------------------------------------------------
  33. */
  34. #include <common.h>
  35. #include <i2c.h>
  36. #include <net.h>
  37. #include <netdev.h>
  38. #include <asm/arch/hardware.h>
  39. #include <asm/arch/emif_defs.h>
  40. #include <asm/arch/emac_defs.h>
  41. #include <asm/io.h>
  42. #include <nand.h>
  43. #include <asm/arch/nand_defs.h>
  44. #include <asm/arch/davinci_misc.h>
  45. #ifdef CONFIG_DAVINCI_MMC
  46. #include <mmc.h>
  47. #include <asm/arch/sdmmc_defs.h>
  48. #endif
  49. DECLARE_GLOBAL_DATA_PTR;
  50. /* SPI0 pin muxer settings */
  51. static const struct pinmux_config spi0_pins[] = {
  52. { pinmux(7), 1, 3 },
  53. { pinmux(7), 1, 4 },
  54. { pinmux(7), 1, 5 },
  55. { pinmux(7), 1, 6 },
  56. { pinmux(7), 1, 7 }
  57. };
  58. /* EMIF-A bus pins for 8-bit NAND support on CS3 */
  59. static const struct pinmux_config emifa_nand_pins[] = {
  60. { pinmux(13), 1, 6 },
  61. { pinmux(13), 1, 7 },
  62. { pinmux(14), 1, 0 },
  63. { pinmux(14), 1, 1 },
  64. { pinmux(14), 1, 2 },
  65. { pinmux(14), 1, 3 },
  66. { pinmux(14), 1, 4 },
  67. { pinmux(14), 1, 5 },
  68. { pinmux(15), 1, 7 },
  69. { pinmux(16), 1, 0 },
  70. { pinmux(18), 1, 1 },
  71. { pinmux(18), 1, 4 },
  72. { pinmux(18), 1, 5 },
  73. };
  74. /* EMAC PHY interface pins */
  75. static const struct pinmux_config emac_pins[] = {
  76. { pinmux(9), 0, 5 },
  77. { pinmux(10), 2, 1 },
  78. { pinmux(10), 2, 2 },
  79. { pinmux(10), 2, 3 },
  80. { pinmux(10), 2, 4 },
  81. { pinmux(10), 2, 5 },
  82. { pinmux(10), 2, 6 },
  83. { pinmux(10), 2, 7 },
  84. { pinmux(11), 2, 0 },
  85. { pinmux(11), 2, 1 },
  86. };
  87. /* UART pin muxer settings */
  88. static const struct pinmux_config uart_pins[] = {
  89. { pinmux(8), 2, 7 },
  90. { pinmux(9), 2, 0 }
  91. };
  92. /* I2C pin muxer settings */
  93. static const struct pinmux_config i2c_pins[] = {
  94. { pinmux(8), 2, 3 },
  95. { pinmux(8), 2, 4 }
  96. };
  97. #ifdef CONFIG_USE_NAND
  98. /* NAND pin muxer settings */
  99. const struct pinmux_config aemif_pins[] = {
  100. { pinmux(13), 1, 6 },
  101. { pinmux(13), 1, 7 },
  102. { pinmux(14), 1, 0 },
  103. { pinmux(14), 1, 1 },
  104. { pinmux(14), 1, 2 },
  105. { pinmux(14), 1, 3 },
  106. { pinmux(14), 1, 4 },
  107. { pinmux(14), 1, 5 },
  108. { pinmux(14), 1, 6 },
  109. { pinmux(14), 1, 7 },
  110. { pinmux(15), 1, 0 },
  111. { pinmux(15), 1, 1 },
  112. { pinmux(15), 1, 2 },
  113. { pinmux(15), 1, 3 },
  114. { pinmux(15), 1, 4 },
  115. { pinmux(15), 1, 5 },
  116. { pinmux(15), 1, 6 },
  117. { pinmux(15), 1, 7 },
  118. { pinmux(16), 1, 0 },
  119. { pinmux(16), 1, 1 },
  120. { pinmux(16), 1, 2 },
  121. { pinmux(16), 1, 3 },
  122. { pinmux(16), 1, 4 },
  123. { pinmux(16), 1, 5 },
  124. { pinmux(16), 1, 6 },
  125. { pinmux(16), 1, 7 },
  126. { pinmux(17), 1, 0 },
  127. { pinmux(17), 1, 1 },
  128. { pinmux(17), 1, 2 },
  129. { pinmux(17), 1, 3 },
  130. { pinmux(17), 1, 4 },
  131. { pinmux(17), 1, 5 },
  132. { pinmux(17), 1, 6 },
  133. { pinmux(17), 1, 7 },
  134. { pinmux(18), 1, 0 },
  135. { pinmux(18), 1, 1 },
  136. { pinmux(18), 1, 2 },
  137. { pinmux(18), 1, 3 },
  138. { pinmux(18), 1, 4 },
  139. { pinmux(18), 1, 5 },
  140. { pinmux(18), 1, 6 },
  141. { pinmux(18), 1, 7 },
  142. { pinmux(10), 1, 0 }
  143. };
  144. #endif
  145. /* USB0_DRVVBUS pin muxer settings */
  146. static const struct pinmux_config usb_pins[] = {
  147. { pinmux(9), 1, 1 }
  148. };
  149. #ifdef CONFIG_DAVINCI_MMC
  150. /* MMC0 pin muxer settings */
  151. const struct pinmux_config mmc0_pins[] = {
  152. { pinmux(15), 2, 7 }, /* MMCSD0_CLK */
  153. { pinmux(16), 2, 0 }, /* MMCSD0_CMD */
  154. { pinmux(13), 2, 6 }, /* MMCSD0_DAT_0 */
  155. { pinmux(13), 2, 7 }, /* MMCSD0_DAT_1 */
  156. { pinmux(14), 2, 0 }, /* MMCSD0_DAT_2 */
  157. { pinmux(14), 2, 1 }, /* MMCSD0_DAT_3 */
  158. { pinmux(14), 2, 2 }, /* MMCSD0_DAT_4 */
  159. { pinmux(14), 2, 3 }, /* MMCSD0_DAT_5 */
  160. { pinmux(14), 2, 4 }, /* MMCSD0_DAT_6 */
  161. { pinmux(14), 2, 5 }, /* MMCSD0_DAT_7 */
  162. /* DA830 supports 8-bit mode */
  163. };
  164. #endif
  165. static const struct pinmux_resource pinmuxes[] = {
  166. #ifdef CONFIG_SPI_FLASH
  167. PINMUX_ITEM(spi0_pins),
  168. #endif
  169. PINMUX_ITEM(uart_pins),
  170. PINMUX_ITEM(i2c_pins),
  171. #ifdef CONFIG_USB_DA8XX
  172. PINMUX_ITEM(usb_pins),
  173. #endif
  174. #ifdef CONFIG_USE_NAND
  175. PINMUX_ITEM(emifa_nand_pins),
  176. PINMUX_ITEM(aemif_pins),
  177. #endif
  178. #if defined(CONFIG_DRIVER_TI_EMAC)
  179. PINMUX_ITEM(emac_pins),
  180. #endif
  181. #ifdef CONFIG_DAVINCI_MMC
  182. PINMUX_ITEM(mmc0_pins),
  183. #endif
  184. };
  185. static const struct lpsc_resource lpsc[] = {
  186. { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
  187. { DAVINCI_LPSC_SPI0 }, /* Serial Flash */
  188. { DAVINCI_LPSC_EMAC }, /* image download */
  189. { DAVINCI_LPSC_UART2 }, /* console */
  190. { DAVINCI_LPSC_GPIO },
  191. #ifdef CONFIG_DAVINCI_MMC
  192. { DAVINCI_LPSC_MMC_SD },
  193. #endif
  194. };
  195. #ifdef CONFIG_DAVINCI_MMC
  196. static struct davinci_mmc mmc_sd0 = {
  197. .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
  198. .host_caps = MMC_MODE_8BIT,
  199. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  200. .version = MMC_CTLR_VERSION_2,
  201. };
  202. int board_mmc_init(bd_t *bis)
  203. {
  204. mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
  205. printf("%x\n", mmc_sd0.input_clk);
  206. /* Add slot-0 to mmc subsystem */
  207. return davinci_mmc_init(bis, &mmc_sd0);
  208. }
  209. #endif
  210. int board_init(void)
  211. {
  212. #ifndef CONFIG_USE_IRQ
  213. irq_init();
  214. #endif
  215. #ifdef CONFIG_NAND_DAVINCI
  216. /* EMIFA 100MHz clock select */
  217. writel(readl(&davinci_syscfg_regs->cfgchip3) & ~2,
  218. &davinci_syscfg_regs->cfgchip3);
  219. /* NAND CS setup */
  220. writel((DAVINCI_ABCR_WSETUP(0) |
  221. DAVINCI_ABCR_WSTROBE(2) |
  222. DAVINCI_ABCR_WHOLD(0) |
  223. DAVINCI_ABCR_RSETUP(0) |
  224. DAVINCI_ABCR_RSTROBE(2) |
  225. DAVINCI_ABCR_RHOLD(0) |
  226. DAVINCI_ABCR_TA(2) |
  227. DAVINCI_ABCR_ASIZE_8BIT),
  228. &davinci_emif_regs->ab2cr);
  229. #endif
  230. /* arch number of the board */
  231. gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA830_EVM;
  232. /* address of boot parameters */
  233. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  234. /*
  235. * Power on required peripherals
  236. * ARM does not have access by default to PSC0 and PSC1
  237. * assuming here that the DSP bootloader has set the IOPU
  238. * such that PSC access is available to ARM
  239. */
  240. if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
  241. return 1;
  242. /* setup the SUSPSRC for ARM to control emulation suspend */
  243. writel(readl(&davinci_syscfg_regs->suspsrc) &
  244. ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
  245. DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
  246. DAVINCI_SYSCFG_SUSPSRC_UART2),
  247. &davinci_syscfg_regs->suspsrc);
  248. /* configure pinmux settings */
  249. if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
  250. return 1;
  251. /* enable the console UART */
  252. writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
  253. DAVINCI_UART_PWREMU_MGMT_UTRST),
  254. &davinci_uart2_ctrl_regs->pwremu_mgmt);
  255. return(0);
  256. }
  257. #ifdef CONFIG_NAND_DAVINCI
  258. int board_nand_init(struct nand_chip *nand)
  259. {
  260. davinci_nand_init(nand);
  261. return 0;
  262. }
  263. #endif
  264. #if defined(CONFIG_DRIVER_TI_EMAC)
  265. #define PHY_SW_I2C_ADDR 0x5f /* Address of PHY on i2c bus */
  266. /*
  267. * Initializes on-board ethernet controllers.
  268. */
  269. int board_eth_init(bd_t *bis)
  270. {
  271. u_int8_t mac_addr[6];
  272. u_int8_t switch_start_cmd[2] = { 0x01, 0x23 };
  273. struct eth_device *dev;
  274. /* Read Ethernet MAC address from EEPROM */
  275. if (dvevm_read_mac_address(mac_addr))
  276. /* set address env if not already set */
  277. davinci_sync_env_enetaddr(mac_addr);
  278. /* read the address back from env */
  279. if (!eth_getenv_enetaddr("ethaddr", mac_addr))
  280. return -1;
  281. /* enable the Ethernet switch in the 3 port PHY */
  282. if (i2c_write(PHY_SW_I2C_ADDR, 0, 0,
  283. switch_start_cmd, sizeof(switch_start_cmd))) {
  284. printf("Ethernet switch start failed!\n");
  285. return -1;
  286. }
  287. /* finally, initialise the driver */
  288. if (!davinci_emac_initialize()) {
  289. printf("Error: Ethernet init failed!\n");
  290. return -1;
  291. }
  292. dev = eth_get_dev();
  293. /* provide the resulting addr to the driver */
  294. memcpy(dev->enetaddr, mac_addr, 6);
  295. dev->write_hwaddr(dev);
  296. return 0;
  297. }
  298. #endif /* CONFIG_DRIVER_TI_EMAC */