spd_sdram.c 26 KB

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  1. /*
  2. * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
  3. *
  4. * (C) Copyright 2006
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  8. * (C) Copyright 2003 Motorola Inc.
  9. * Xianghua Xiao (X.Xiao@motorola.com)
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #include <common.h>
  30. #include <asm/processor.h>
  31. #include <i2c.h>
  32. #include <spd.h>
  33. #include <asm/mmu.h>
  34. #include <spd_sdram.h>
  35. DECLARE_GLOBAL_DATA_PTR;
  36. void board_add_ram_info(int use_default)
  37. {
  38. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  39. volatile ddr83xx_t *ddr = &immap->ddr;
  40. char buf[32];
  41. printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
  42. >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
  43. if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
  44. puts(", 32-bit");
  45. else
  46. puts(", 64-bit");
  47. if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
  48. puts(", ECC on");
  49. else
  50. puts(", ECC off");
  51. printf(", %s MHz)", strmhz(buf, gd->mem_clk));
  52. #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
  53. puts("\nSDRAM: ");
  54. print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
  55. #endif
  56. }
  57. #ifdef CONFIG_SPD_EEPROM
  58. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
  59. extern void dma_init(void);
  60. extern uint dma_check(void);
  61. extern int dma_xfer(void *dest, uint count, void *src);
  62. #endif
  63. #ifndef CONFIG_SYS_READ_SPD
  64. #define CONFIG_SYS_READ_SPD i2c_read
  65. #endif
  66. /*
  67. * Convert picoseconds into clock cycles (rounding up if needed).
  68. */
  69. int
  70. picos_to_clk(int picos)
  71. {
  72. unsigned int mem_bus_clk;
  73. int clks;
  74. mem_bus_clk = gd->mem_clk >> 1;
  75. clks = picos / (1000000000 / (mem_bus_clk / 1000));
  76. if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
  77. clks++;
  78. return clks;
  79. }
  80. unsigned int banksize(unsigned char row_dens)
  81. {
  82. return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
  83. }
  84. int read_spd(uint addr)
  85. {
  86. return ((int) addr);
  87. }
  88. #undef SPD_DEBUG
  89. #ifdef SPD_DEBUG
  90. static void spd_debug(spd_eeprom_t *spd)
  91. {
  92. printf ("\nDIMM type: %-18.18s\n", spd->mpart);
  93. printf ("SPD size: %d\n", spd->info_size);
  94. printf ("EEPROM size: %d\n", 1 << spd->chip_size);
  95. printf ("Memory type: %d\n", spd->mem_type);
  96. printf ("Row addr: %d\n", spd->nrow_addr);
  97. printf ("Column addr: %d\n", spd->ncol_addr);
  98. printf ("# of rows: %d\n", spd->nrows);
  99. printf ("Row density: %d\n", spd->row_dens);
  100. printf ("# of banks: %d\n", spd->nbanks);
  101. printf ("Data width: %d\n",
  102. 256 * spd->dataw_msb + spd->dataw_lsb);
  103. printf ("Chip width: %d\n", spd->primw);
  104. printf ("Refresh rate: %02X\n", spd->refresh);
  105. printf ("CAS latencies: %02X\n", spd->cas_lat);
  106. printf ("Write latencies: %02X\n", spd->write_lat);
  107. printf ("tRP: %d\n", spd->trp);
  108. printf ("tRCD: %d\n", spd->trcd);
  109. printf ("\n");
  110. }
  111. #endif /* SPD_DEBUG */
  112. long int spd_sdram()
  113. {
  114. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  115. volatile ddr83xx_t *ddr = &immap->ddr;
  116. volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
  117. spd_eeprom_t spd;
  118. unsigned int n_ranks;
  119. unsigned int odt_rd_cfg, odt_wr_cfg;
  120. unsigned char twr_clk, twtr_clk;
  121. unsigned int sdram_type;
  122. unsigned int memsize;
  123. unsigned int law_size;
  124. unsigned char caslat, caslat_ctrl;
  125. unsigned int trfc, trfc_clk, trfc_low, trfc_high;
  126. unsigned int trcd_clk, trtp_clk;
  127. unsigned char cke_min_clk;
  128. unsigned char add_lat, wr_lat;
  129. unsigned char wr_data_delay;
  130. unsigned char four_act;
  131. unsigned char cpo;
  132. unsigned char burstlen;
  133. unsigned char odt_cfg, mode_odt_enable;
  134. unsigned int max_bus_clk;
  135. unsigned int max_data_rate, effective_data_rate;
  136. unsigned int ddrc_clk;
  137. unsigned int refresh_clk;
  138. unsigned int sdram_cfg;
  139. unsigned int ddrc_ecc_enable;
  140. unsigned int pvr = get_pvr();
  141. /* Read SPD parameters with I2C */
  142. CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
  143. #ifdef SPD_DEBUG
  144. spd_debug(&spd);
  145. #endif
  146. /* Check the memory type */
  147. if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
  148. debug("DDR: Module mem type is %02X\n", spd.mem_type);
  149. return 0;
  150. }
  151. /* Check the number of physical bank */
  152. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  153. n_ranks = spd.nrows;
  154. } else {
  155. n_ranks = (spd.nrows & 0x7) + 1;
  156. }
  157. if (n_ranks > 2) {
  158. printf("DDR: The number of physical bank is %02X\n", n_ranks);
  159. return 0;
  160. }
  161. /* Check if the number of row of the module is in the range of DDRC */
  162. if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
  163. printf("DDR: Row number is out of range of DDRC, row=%02X\n",
  164. spd.nrow_addr);
  165. return 0;
  166. }
  167. /* Check if the number of col of the module is in the range of DDRC */
  168. if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
  169. printf("DDR: Col number is out of range of DDRC, col=%02X\n",
  170. spd.ncol_addr);
  171. return 0;
  172. }
  173. #ifdef CONFIG_SYS_DDRCDR_VALUE
  174. /*
  175. * Adjust DDR II IO voltage biasing. It just makes it work.
  176. */
  177. if(spd.mem_type == SPD_MEMTYPE_DDR2) {
  178. immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  179. }
  180. udelay(50000);
  181. #endif
  182. /*
  183. * ODT configuration recommendation from DDR Controller Chapter.
  184. */
  185. odt_rd_cfg = 0; /* Never assert ODT */
  186. odt_wr_cfg = 0; /* Never assert ODT */
  187. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  188. odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
  189. }
  190. /* Setup DDR chip select register */
  191. #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
  192. ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  193. ddr->cs_config[0] = ( 1 << 31
  194. | (odt_rd_cfg << 20)
  195. | (odt_wr_cfg << 16)
  196. | (spd.nrow_addr - 12) << 8
  197. | (spd.ncol_addr - 8) );
  198. debug("\n");
  199. debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
  200. debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
  201. if (n_ranks == 2) {
  202. ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
  203. | ((banksize(spd.row_dens) >> 23) - 1) );
  204. ddr->cs_config[1] = ( 1<<31
  205. | (odt_rd_cfg << 20)
  206. | (odt_wr_cfg << 16)
  207. | (spd.nrow_addr-12) << 8
  208. | (spd.ncol_addr-8) );
  209. debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
  210. debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
  211. }
  212. #else
  213. ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  214. ddr->cs_config[2] = ( 1 << 31
  215. | (odt_rd_cfg << 20)
  216. | (odt_wr_cfg << 16)
  217. | (spd.nrow_addr - 12) << 8
  218. | (spd.ncol_addr - 8) );
  219. debug("\n");
  220. debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
  221. debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
  222. if (n_ranks == 2) {
  223. ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
  224. | ((banksize(spd.row_dens) >> 23) - 1) );
  225. ddr->cs_config[3] = ( 1<<31
  226. | (odt_rd_cfg << 20)
  227. | (odt_wr_cfg << 16)
  228. | (spd.nrow_addr-12) << 8
  229. | (spd.ncol_addr-8) );
  230. debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
  231. debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
  232. }
  233. #endif
  234. /*
  235. * Figure out memory size in Megabytes.
  236. */
  237. memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
  238. /*
  239. * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
  240. */
  241. law_size = 19 + __ilog2(memsize);
  242. /*
  243. * Set up LAWBAR for all of DDR.
  244. */
  245. ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
  246. ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
  247. debug("DDR:bar=0x%08x\n", ecm->bar);
  248. debug("DDR:ar=0x%08x\n", ecm->ar);
  249. /*
  250. * Find the largest CAS by locating the highest 1 bit
  251. * in the spd.cas_lat field. Translate it to a DDR
  252. * controller field value:
  253. *
  254. * CAS Lat DDR I DDR II Ctrl
  255. * Clocks SPD Bit SPD Bit Value
  256. * ------- ------- ------- -----
  257. * 1.0 0 0001
  258. * 1.5 1 0010
  259. * 2.0 2 2 0011
  260. * 2.5 3 0100
  261. * 3.0 4 3 0101
  262. * 3.5 5 0110
  263. * 4.0 6 4 0111
  264. * 4.5 1000
  265. * 5.0 5 1001
  266. */
  267. caslat = __ilog2(spd.cas_lat);
  268. if ((spd.mem_type == SPD_MEMTYPE_DDR)
  269. && (caslat > 6)) {
  270. printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
  271. return 0;
  272. } else if (spd.mem_type == SPD_MEMTYPE_DDR2
  273. && (caslat < 2 || caslat > 5)) {
  274. printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
  275. spd.cas_lat);
  276. return 0;
  277. }
  278. debug("DDR: caslat SPD bit is %d\n", caslat);
  279. max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
  280. + (spd.clk_cycle & 0x0f));
  281. max_data_rate = max_bus_clk * 2;
  282. debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
  283. ddrc_clk = gd->mem_clk / 1000000;
  284. effective_data_rate = 0;
  285. if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
  286. if (spd.cas_lat & 0x08)
  287. caslat = 3;
  288. else
  289. caslat = 4;
  290. if (ddrc_clk <= 460 && ddrc_clk > 350)
  291. effective_data_rate = 400;
  292. else if (ddrc_clk <=350 && ddrc_clk > 280)
  293. effective_data_rate = 333;
  294. else if (ddrc_clk <= 280 && ddrc_clk > 230)
  295. effective_data_rate = 266;
  296. else
  297. effective_data_rate = 200;
  298. } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
  299. if (ddrc_clk <= 460 && ddrc_clk > 350) {
  300. /* DDR controller clk at 350~460 */
  301. effective_data_rate = 400; /* 5ns */
  302. caslat = caslat;
  303. } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
  304. /* DDR controller clk at 280~350 */
  305. effective_data_rate = 333; /* 6ns */
  306. if (spd.clk_cycle2 == 0x60)
  307. caslat = caslat - 1;
  308. else
  309. caslat = caslat;
  310. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  311. /* DDR controller clk at 230~280 */
  312. effective_data_rate = 266; /* 7.5ns */
  313. if (spd.clk_cycle3 == 0x75)
  314. caslat = caslat - 2;
  315. else if (spd.clk_cycle2 == 0x75)
  316. caslat = caslat - 1;
  317. else
  318. caslat = caslat;
  319. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  320. /* DDR controller clk at 90~230 */
  321. effective_data_rate = 200; /* 10ns */
  322. if (spd.clk_cycle3 == 0xa0)
  323. caslat = caslat - 2;
  324. else if (spd.clk_cycle2 == 0xa0)
  325. caslat = caslat - 1;
  326. else
  327. caslat = caslat;
  328. }
  329. } else if (max_data_rate >= 323) { /* it is DDR 333 */
  330. if (ddrc_clk <= 350 && ddrc_clk > 280) {
  331. /* DDR controller clk at 280~350 */
  332. effective_data_rate = 333; /* 6ns */
  333. caslat = caslat;
  334. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  335. /* DDR controller clk at 230~280 */
  336. effective_data_rate = 266; /* 7.5ns */
  337. if (spd.clk_cycle2 == 0x75)
  338. caslat = caslat - 1;
  339. else
  340. caslat = caslat;
  341. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  342. /* DDR controller clk at 90~230 */
  343. effective_data_rate = 200; /* 10ns */
  344. if (spd.clk_cycle3 == 0xa0)
  345. caslat = caslat - 2;
  346. else if (spd.clk_cycle2 == 0xa0)
  347. caslat = caslat - 1;
  348. else
  349. caslat = caslat;
  350. }
  351. } else if (max_data_rate >= 256) { /* it is DDR 266 */
  352. if (ddrc_clk <= 350 && ddrc_clk > 280) {
  353. /* DDR controller clk at 280~350 */
  354. printf("DDR: DDR controller freq is more than "
  355. "max data rate of the module\n");
  356. return 0;
  357. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  358. /* DDR controller clk at 230~280 */
  359. effective_data_rate = 266; /* 7.5ns */
  360. caslat = caslat;
  361. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  362. /* DDR controller clk at 90~230 */
  363. effective_data_rate = 200; /* 10ns */
  364. if (spd.clk_cycle2 == 0xa0)
  365. caslat = caslat - 1;
  366. }
  367. } else if (max_data_rate >= 190) { /* it is DDR 200 */
  368. if (ddrc_clk <= 350 && ddrc_clk > 230) {
  369. /* DDR controller clk at 230~350 */
  370. printf("DDR: DDR controller freq is more than "
  371. "max data rate of the module\n");
  372. return 0;
  373. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  374. /* DDR controller clk at 90~230 */
  375. effective_data_rate = 200; /* 10ns */
  376. caslat = caslat;
  377. }
  378. }
  379. debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
  380. debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
  381. /*
  382. * Errata DDR6 work around: input enable 2 cycles earlier.
  383. * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
  384. */
  385. if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
  386. if (caslat == 2)
  387. ddr->debug_reg = 0x201c0000; /* CL=2 */
  388. else if (caslat == 3)
  389. ddr->debug_reg = 0x202c0000; /* CL=2.5 */
  390. else if (caslat == 4)
  391. ddr->debug_reg = 0x202c0000; /* CL=3.0 */
  392. __asm__ __volatile__ ("sync");
  393. debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
  394. }
  395. /*
  396. * Convert caslat clocks to DDR controller value.
  397. * Force caslat_ctrl to be DDR Controller field-sized.
  398. */
  399. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  400. caslat_ctrl = (caslat + 1) & 0x07;
  401. } else {
  402. caslat_ctrl = (2 * caslat - 1) & 0x0f;
  403. }
  404. debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
  405. debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
  406. caslat, caslat_ctrl);
  407. /*
  408. * Timing Config 0.
  409. * Avoid writing for DDR I.
  410. */
  411. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  412. unsigned char taxpd_clk = 8; /* By the book. */
  413. unsigned char tmrd_clk = 2; /* By the book. */
  414. unsigned char act_pd_exit = 2; /* Empirical? */
  415. unsigned char pre_pd_exit = 6; /* Empirical? */
  416. ddr->timing_cfg_0 = (0
  417. | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
  418. | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
  419. | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
  420. | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
  421. );
  422. debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
  423. }
  424. /*
  425. * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
  426. * use conservative value.
  427. * For DDR II, they are bytes 36 and 37, in quarter nanos.
  428. */
  429. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  430. twr_clk = 3; /* Clocks */
  431. twtr_clk = 1; /* Clocks */
  432. } else {
  433. twr_clk = picos_to_clk(spd.twr * 250);
  434. twtr_clk = picos_to_clk(spd.twtr * 250);
  435. if (twtr_clk < 2)
  436. twtr_clk = 2;
  437. }
  438. /*
  439. * Calculate Trfc, in picos.
  440. * DDR I: Byte 42 straight up in ns.
  441. * DDR II: Byte 40 and 42 swizzled some, in ns.
  442. */
  443. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  444. trfc = spd.trfc * 1000; /* up to ps */
  445. } else {
  446. unsigned int byte40_table_ps[8] = {
  447. 0,
  448. 250,
  449. 330,
  450. 500,
  451. 660,
  452. 750,
  453. 0,
  454. 0
  455. };
  456. trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
  457. + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
  458. }
  459. trfc_clk = picos_to_clk(trfc);
  460. /*
  461. * Trcd, Byte 29, from quarter nanos to ps and clocks.
  462. */
  463. trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
  464. /*
  465. * Convert trfc_clk to DDR controller fields. DDR I should
  466. * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
  467. * 83xx controller has an extended REFREC field of three bits.
  468. * The controller automatically adds 8 clocks to this value,
  469. * so preadjust it down 8 first before splitting it up.
  470. */
  471. trfc_low = (trfc_clk - 8) & 0xf;
  472. trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
  473. ddr->timing_cfg_1 =
  474. (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
  475. ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
  476. (trcd_clk << 20 ) | /* ACTTORW */
  477. (caslat_ctrl << 16 ) | /* CASLAT */
  478. (trfc_low << 12 ) | /* REFEC */
  479. ((twr_clk & 0x07) << 8) | /* WRRREC */
  480. ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
  481. ((twtr_clk & 0x07) << 0) /* WRTORD */
  482. );
  483. /*
  484. * Additive Latency
  485. * For DDR I, 0.
  486. * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
  487. * which comes from Trcd, and also note that:
  488. * add_lat + caslat must be >= 4
  489. */
  490. add_lat = 0;
  491. if (spd.mem_type == SPD_MEMTYPE_DDR2
  492. && (odt_wr_cfg || odt_rd_cfg)
  493. && (caslat < 4)) {
  494. add_lat = 4 - caslat;
  495. if ((add_lat + caslat) < 4) {
  496. add_lat = 0;
  497. }
  498. }
  499. /*
  500. * Write Data Delay
  501. * Historically 0x2 == 4/8 clock delay.
  502. * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
  503. */
  504. wr_data_delay = 2;
  505. /*
  506. * Write Latency
  507. * Read to Precharge
  508. * Minimum CKE Pulse Width.
  509. * Four Activate Window
  510. */
  511. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  512. /*
  513. * This is a lie. It should really be 1, but if it is
  514. * set to 1, bits overlap into the old controller's
  515. * otherwise unused ACSM field. If we leave it 0, then
  516. * the HW will magically treat it as 1 for DDR 1. Oh Yea.
  517. */
  518. wr_lat = 0;
  519. trtp_clk = 2; /* By the book. */
  520. cke_min_clk = 1; /* By the book. */
  521. four_act = 1; /* By the book. */
  522. } else {
  523. wr_lat = caslat - 1;
  524. /* Convert SPD value from quarter nanos to picos. */
  525. trtp_clk = picos_to_clk(spd.trtp * 250);
  526. if (trtp_clk < 2)
  527. trtp_clk = 2;
  528. trtp_clk += add_lat;
  529. cke_min_clk = 3; /* By the book. */
  530. four_act = picos_to_clk(37500); /* By the book. 1k pages? */
  531. }
  532. /*
  533. * Empirically set ~MCAS-to-preamble override for DDR 2.
  534. * Your milage will vary.
  535. */
  536. cpo = 0;
  537. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  538. if (effective_data_rate == 266) {
  539. cpo = 0x4; /* READ_LAT + 1/2 */
  540. } else if (effective_data_rate == 333) {
  541. cpo = 0x6; /* READ_LAT + 1 */
  542. } else if (effective_data_rate == 400) {
  543. cpo = 0x7; /* READ_LAT + 5/4 */
  544. } else {
  545. /* Automatic calibration */
  546. cpo = 0x1f;
  547. }
  548. }
  549. ddr->timing_cfg_2 = (0
  550. | ((add_lat & 0x7) << 28) /* ADD_LAT */
  551. | ((cpo & 0x1f) << 23) /* CPO */
  552. | ((wr_lat & 0x7) << 19) /* WR_LAT */
  553. | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
  554. | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
  555. | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
  556. | ((four_act & 0x1f) << 0) /* FOUR_ACT */
  557. );
  558. debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
  559. debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
  560. /* Check DIMM data bus width */
  561. if (spd.dataw_lsb < 64) {
  562. if (spd.mem_type == SPD_MEMTYPE_DDR)
  563. burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
  564. else
  565. burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
  566. debug("\n DDR DIMM: data bus width is 32 bit");
  567. } else {
  568. burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
  569. debug("\n DDR DIMM: data bus width is 64 bit");
  570. }
  571. /* Is this an ECC DDR chip? */
  572. if (spd.config == 0x02)
  573. debug(" with ECC\n");
  574. else
  575. debug(" without ECC\n");
  576. /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
  577. Burst type is sequential
  578. */
  579. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  580. switch (caslat) {
  581. case 1:
  582. ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
  583. break;
  584. case 2:
  585. ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
  586. break;
  587. case 3:
  588. ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
  589. break;
  590. case 4:
  591. ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
  592. break;
  593. default:
  594. printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
  595. return 0;
  596. }
  597. } else {
  598. mode_odt_enable = 0x0; /* Default disabled */
  599. if (odt_wr_cfg || odt_rd_cfg) {
  600. /*
  601. * Bits 6 and 2 in Extended MRS(1)
  602. * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
  603. * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
  604. */
  605. mode_odt_enable = 0x40; /* 150 Ohm */
  606. }
  607. ddr->sdram_mode =
  608. (0
  609. | (1 << (16 + 10)) /* DQS Differential disable */
  610. | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
  611. | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
  612. | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
  613. | (caslat << 4) /* caslat */
  614. | (burstlen << 0) /* Burst length */
  615. );
  616. }
  617. debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
  618. /*
  619. * Clear EMRS2 and EMRS3.
  620. */
  621. ddr->sdram_mode2 = 0;
  622. debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
  623. switch (spd.refresh) {
  624. case 0x00:
  625. case 0x80:
  626. refresh_clk = picos_to_clk(15625000);
  627. break;
  628. case 0x01:
  629. case 0x81:
  630. refresh_clk = picos_to_clk(3900000);
  631. break;
  632. case 0x02:
  633. case 0x82:
  634. refresh_clk = picos_to_clk(7800000);
  635. break;
  636. case 0x03:
  637. case 0x83:
  638. refresh_clk = picos_to_clk(31300000);
  639. break;
  640. case 0x04:
  641. case 0x84:
  642. refresh_clk = picos_to_clk(62500000);
  643. break;
  644. case 0x05:
  645. case 0x85:
  646. refresh_clk = picos_to_clk(125000000);
  647. break;
  648. default:
  649. refresh_clk = 0x512;
  650. break;
  651. }
  652. /*
  653. * Set BSTOPRE to 0x100 for page mode
  654. * If auto-charge is used, set BSTOPRE = 0
  655. */
  656. ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
  657. debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
  658. /*
  659. * SDRAM Cfg 2
  660. */
  661. odt_cfg = 0;
  662. #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
  663. if (odt_rd_cfg | odt_wr_cfg) {
  664. odt_cfg = 0x2; /* ODT to IOs during reads */
  665. }
  666. #endif
  667. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  668. ddr->sdram_cfg2 = (0
  669. | (0 << 26) /* True DQS */
  670. | (odt_cfg << 21) /* ODT only read */
  671. | (1 << 12) /* 1 refresh at a time */
  672. );
  673. debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
  674. }
  675. #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
  676. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  677. #endif
  678. debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
  679. asm("sync;isync");
  680. udelay(600);
  681. /*
  682. * Figure out the settings for the sdram_cfg register. Build up
  683. * the value in 'sdram_cfg' before writing since the write into
  684. * the register will actually enable the memory controller, and all
  685. * settings must be done before enabling.
  686. *
  687. * sdram_cfg[0] = 1 (ddr sdram logic enable)
  688. * sdram_cfg[1] = 1 (self-refresh-enable)
  689. * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
  690. * 010 DDR 1 SDRAM
  691. * 011 DDR 2 SDRAM
  692. * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
  693. * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
  694. */
  695. if (spd.mem_type == SPD_MEMTYPE_DDR)
  696. sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
  697. else
  698. sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
  699. sdram_cfg = (0
  700. | SDRAM_CFG_MEM_EN /* DDR enable */
  701. | SDRAM_CFG_SREN /* Self refresh */
  702. | sdram_type /* SDRAM type */
  703. );
  704. /* sdram_cfg[3] = RD_EN - registered DIMM enable */
  705. if (spd.mod_attr & 0x02)
  706. sdram_cfg |= SDRAM_CFG_RD_EN;
  707. /* The DIMM is 32bit width */
  708. if (spd.dataw_lsb < 64) {
  709. if (spd.mem_type == SPD_MEMTYPE_DDR)
  710. sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
  711. if (spd.mem_type == SPD_MEMTYPE_DDR2)
  712. sdram_cfg |= SDRAM_CFG_32_BE;
  713. }
  714. ddrc_ecc_enable = 0;
  715. #if defined(CONFIG_DDR_ECC)
  716. /* Enable ECC with sdram_cfg[2] */
  717. if (spd.config == 0x02) {
  718. sdram_cfg |= 0x20000000;
  719. ddrc_ecc_enable = 1;
  720. /* disable error detection */
  721. ddr->err_disable = ~ECC_ERROR_ENABLE;
  722. /* set single bit error threshold to maximum value,
  723. * reset counter to zero */
  724. ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
  725. (0 << ECC_ERROR_MAN_SBEC_SHIFT);
  726. }
  727. debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
  728. debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
  729. #endif
  730. debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
  731. #if defined(CONFIG_DDR_2T_TIMING)
  732. /*
  733. * Enable 2T timing by setting sdram_cfg[16].
  734. */
  735. sdram_cfg |= SDRAM_CFG_2T_EN;
  736. #endif
  737. /* Enable controller, and GO! */
  738. ddr->sdram_cfg = sdram_cfg;
  739. asm("sync;isync");
  740. udelay(500);
  741. debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
  742. return memsize; /*in MBytes*/
  743. }
  744. #endif /* CONFIG_SPD_EEPROM */
  745. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
  746. /*
  747. * Use timebase counter, get_timer() is not availabe
  748. * at this point of initialization yet.
  749. */
  750. static __inline__ unsigned long get_tbms (void)
  751. {
  752. unsigned long tbl;
  753. unsigned long tbu1, tbu2;
  754. unsigned long ms;
  755. unsigned long long tmp;
  756. ulong tbclk = get_tbclk();
  757. /* get the timebase ticks */
  758. do {
  759. asm volatile ("mftbu %0":"=r" (tbu1):);
  760. asm volatile ("mftb %0":"=r" (tbl):);
  761. asm volatile ("mftbu %0":"=r" (tbu2):);
  762. } while (tbu1 != tbu2);
  763. /* convert ticks to ms */
  764. tmp = (unsigned long long)(tbu1);
  765. tmp = (tmp << 32);
  766. tmp += (unsigned long long)(tbl);
  767. ms = tmp/(tbclk/1000);
  768. return ms;
  769. }
  770. /*
  771. * Initialize all of memory for ECC, then enable errors.
  772. */
  773. /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
  774. void ddr_enable_ecc(unsigned int dram_size)
  775. {
  776. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  777. volatile ddr83xx_t *ddr= &immap->ddr;
  778. unsigned long t_start, t_end;
  779. register u64 *p;
  780. register uint size;
  781. unsigned int pattern[2];
  782. #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
  783. uint i;
  784. #endif
  785. icache_enable();
  786. t_start = get_tbms();
  787. pattern[0] = 0xdeadbeef;
  788. pattern[1] = 0xdeadbeef;
  789. #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
  790. debug("ddr init: CPU FP write method\n");
  791. size = dram_size;
  792. for (p = 0; p < (u64*)(size); p++) {
  793. ppcDWstore((u32*)p, pattern);
  794. }
  795. __asm__ __volatile__ ("sync");
  796. #else
  797. debug("ddr init: DMA method\n");
  798. size = 0x2000;
  799. for (p = 0; p < (u64*)(size); p++) {
  800. ppcDWstore((u32*)p, pattern);
  801. }
  802. __asm__ __volatile__ ("sync");
  803. /* Initialise DMA for direct transfer */
  804. dma_init();
  805. /* Start DMA to transfer */
  806. dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
  807. dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
  808. dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
  809. dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
  810. dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
  811. dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
  812. dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
  813. dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
  814. dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
  815. dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
  816. for (i = 1; i < dram_size / 0x800000; i++) {
  817. dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
  818. }
  819. #endif
  820. t_end = get_tbms();
  821. icache_disable();
  822. debug("\nREADY!!\n");
  823. debug("ddr init duration: %ld ms\n", t_end - t_start);
  824. /* Clear All ECC Errors */
  825. if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
  826. ddr->err_detect |= ECC_ERROR_DETECT_MME;
  827. if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
  828. ddr->err_detect |= ECC_ERROR_DETECT_MBE;
  829. if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
  830. ddr->err_detect |= ECC_ERROR_DETECT_SBE;
  831. if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
  832. ddr->err_detect |= ECC_ERROR_DETECT_MSE;
  833. /* Disable ECC-Interrupts */
  834. ddr->err_int_en &= ECC_ERR_INT_DISABLE;
  835. /* Enable errors for ECC */
  836. ddr->err_disable &= ECC_ERROR_ENABLE;
  837. __asm__ __volatile__ ("sync");
  838. __asm__ __volatile__ ("isync");
  839. }
  840. #endif /* CONFIG_DDR_ECC */