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  1. /*
  2. * armboot - Startup Code for ARM920 CPU-core
  3. *
  4. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  5. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  6. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <asm-offsets.h>
  27. #include <common.h>
  28. #include <config.h>
  29. /*
  30. *************************************************************************
  31. *
  32. * Jump vector table as in table 3.1 in [1]
  33. *
  34. *************************************************************************
  35. */
  36. .globl _start
  37. _start: b start_code
  38. ldr pc, _undefined_instruction
  39. ldr pc, _software_interrupt
  40. ldr pc, _prefetch_abort
  41. ldr pc, _data_abort
  42. ldr pc, _not_used
  43. ldr pc, _irq
  44. ldr pc, _fiq
  45. _undefined_instruction: .word undefined_instruction
  46. _software_interrupt: .word software_interrupt
  47. _prefetch_abort: .word prefetch_abort
  48. _data_abort: .word data_abort
  49. _not_used: .word not_used
  50. _irq: .word irq
  51. _fiq: .word fiq
  52. .balignl 16,0xdeadbeef
  53. /*
  54. *************************************************************************
  55. *
  56. * Startup Code (called from the ARM reset exception vector)
  57. *
  58. * do important init only if we don't start from memory!
  59. * relocate armboot to ram
  60. * setup stack
  61. * jump to second stage
  62. *
  63. *************************************************************************
  64. */
  65. .globl _TEXT_BASE
  66. _TEXT_BASE:
  67. .word CONFIG_SYS_TEXT_BASE
  68. /*
  69. * These are defined in the board-specific linker script.
  70. * Subtracting _start from them lets the linker put their
  71. * relative position in the executable instead of leaving
  72. * them null.
  73. */
  74. .globl _bss_start_ofs
  75. _bss_start_ofs:
  76. .word __bss_start - _start
  77. .globl _bss_end_ofs
  78. _bss_end_ofs:
  79. .word _end - _start
  80. #ifdef CONFIG_USE_IRQ
  81. /* IRQ stack memory (calculated at run-time) */
  82. .globl IRQ_STACK_START
  83. IRQ_STACK_START:
  84. .word 0x0badc0de
  85. /* IRQ stack memory (calculated at run-time) */
  86. .globl FIQ_STACK_START
  87. FIQ_STACK_START:
  88. .word 0x0badc0de
  89. #endif
  90. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  91. .globl IRQ_STACK_START_IN
  92. IRQ_STACK_START_IN:
  93. .word 0x0badc0de
  94. /*
  95. * the actual start code
  96. */
  97. start_code:
  98. /*
  99. * set the cpu to SVC32 mode
  100. */
  101. mrs r0, cpsr
  102. bic r0, r0, #0x1f
  103. orr r0, r0, #0xd3
  104. msr cpsr, r0
  105. #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
  106. /*
  107. * relocate exception table
  108. */
  109. ldr r0, =_start
  110. ldr r1, =0x0
  111. mov r2, #16
  112. copyex:
  113. subs r2, r2, #1
  114. ldr r3, [r0], #4
  115. str r3, [r1], #4
  116. bne copyex
  117. #endif
  118. #ifdef CONFIG_S3C24X0
  119. /* turn off the watchdog */
  120. # if defined(CONFIG_S3C2400)
  121. # define pWTCON 0x15300000
  122. # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
  123. # define CLKDIVN 0x14800014 /* clock divisor register */
  124. #else
  125. # define pWTCON 0x53000000
  126. # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
  127. # define INTSUBMSK 0x4A00001C
  128. # define CLKDIVN 0x4C000014 /* clock divisor register */
  129. # endif
  130. ldr r0, =pWTCON
  131. mov r1, #0x0
  132. str r1, [r0]
  133. /*
  134. * mask all IRQs by setting all bits in the INTMR - default
  135. */
  136. mov r1, #0xffffffff
  137. ldr r0, =INTMSK
  138. str r1, [r0]
  139. # if defined(CONFIG_S3C2410)
  140. ldr r1, =0x3ff
  141. ldr r0, =INTSUBMSK
  142. str r1, [r0]
  143. # endif
  144. /* FCLK:HCLK:PCLK = 1:2:4 */
  145. /* default FCLK is 120 MHz ! */
  146. ldr r0, =CLKDIVN
  147. mov r1, #3
  148. str r1, [r0]
  149. #endif /* CONFIG_S3C24X0 */
  150. /*
  151. * we do sys-critical inits only at reboot,
  152. * not when booting from ram!
  153. */
  154. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  155. bl cpu_init_crit
  156. #endif
  157. /* Set stackpointer in internal RAM to call board_init_f */
  158. call_board_init_f:
  159. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  160. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  161. ldr r0,=0x00000000
  162. bl board_init_f
  163. /*------------------------------------------------------------------------------*/
  164. /*
  165. * void relocate_code (addr_sp, gd, addr_moni)
  166. *
  167. * This "function" does not return, instead it continues in RAM
  168. * after relocating the monitor code.
  169. *
  170. */
  171. .globl relocate_code
  172. relocate_code:
  173. mov r4, r0 /* save addr_sp */
  174. mov r5, r1 /* save addr of gd */
  175. mov r6, r2 /* save addr of destination */
  176. /* Set up the stack */
  177. stack_setup:
  178. mov sp, r4
  179. adr r0, _start
  180. cmp r0, r6
  181. beq clear_bss /* skip relocation */
  182. mov r1, r6 /* r1 <- scratch for copy_loop */
  183. ldr r3, _bss_start_ofs
  184. add r2, r0, r3 /* r2 <- source end address */
  185. copy_loop:
  186. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  187. stmia r1!, {r9-r10} /* copy to target address [r1] */
  188. cmp r0, r2 /* until source end address [r2] */
  189. blo copy_loop
  190. #ifndef CONFIG_PRELOADER
  191. /*
  192. * fix .rel.dyn relocations
  193. */
  194. ldr r0, _TEXT_BASE /* r0 <- Text base */
  195. sub r9, r6, r0 /* r9 <- relocation offset */
  196. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  197. add r10, r10, r0 /* r10 <- sym table in FLASH */
  198. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  199. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  200. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  201. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  202. fixloop:
  203. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  204. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  205. ldr r1, [r2, #4]
  206. and r7, r1, #0xff
  207. cmp r7, #23 /* relative fixup? */
  208. beq fixrel
  209. cmp r7, #2 /* absolute fixup? */
  210. beq fixabs
  211. /* ignore unknown type of fixup */
  212. b fixnext
  213. fixabs:
  214. /* absolute fix: set location to (offset) symbol value */
  215. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  216. add r1, r10, r1 /* r1 <- address of symbol in table */
  217. ldr r1, [r1, #4] /* r1 <- symbol value */
  218. add r1, r1, r9 /* r1 <- relocated sym addr */
  219. b fixnext
  220. fixrel:
  221. /* relative fix: increase location by offset */
  222. ldr r1, [r0]
  223. add r1, r1, r9
  224. fixnext:
  225. str r1, [r0]
  226. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  227. cmp r2, r3
  228. blo fixloop
  229. #endif
  230. clear_bss:
  231. #ifndef CONFIG_PRELOADER
  232. ldr r0, _bss_start_ofs
  233. ldr r1, _bss_end_ofs
  234. mov r4, r6 /* reloc addr */
  235. add r0, r0, r4
  236. add r1, r1, r4
  237. mov r2, #0x00000000 /* clear */
  238. clbss_l:str r2, [r0] /* clear loop... */
  239. add r0, r0, #4
  240. cmp r0, r1
  241. bne clbss_l
  242. bl coloured_LED_init
  243. bl red_LED_on
  244. #endif
  245. /*
  246. * We are done. Do not return, instead branch to second part of board
  247. * initialization, now running from RAM.
  248. */
  249. #ifdef CONFIG_NAND_SPL
  250. ldr r0, _nand_boot_ofs
  251. mov pc, r0
  252. _nand_boot_ofs:
  253. .word nand_boot
  254. #else
  255. ldr r0, _board_init_r_ofs
  256. adr r1, _start
  257. add lr, r0, r1
  258. add lr, lr, r9
  259. /* setup parameters for board_init_r */
  260. mov r0, r5 /* gd_t */
  261. mov r1, r6 /* dest_addr */
  262. /* jump to it ... */
  263. mov pc, lr
  264. _board_init_r_ofs:
  265. .word board_init_r - _start
  266. #endif
  267. _rel_dyn_start_ofs:
  268. .word __rel_dyn_start - _start
  269. _rel_dyn_end_ofs:
  270. .word __rel_dyn_end - _start
  271. _dynsym_start_ofs:
  272. .word __dynsym_start - _start
  273. /*
  274. *************************************************************************
  275. *
  276. * CPU_init_critical registers
  277. *
  278. * setup important registers
  279. * setup memory timing
  280. *
  281. *************************************************************************
  282. */
  283. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  284. cpu_init_crit:
  285. /*
  286. * flush v4 I/D caches
  287. */
  288. mov r0, #0
  289. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  290. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  291. /*
  292. * disable MMU stuff and caches
  293. */
  294. mrc p15, 0, r0, c1, c0, 0
  295. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  296. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  297. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  298. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  299. mcr p15, 0, r0, c1, c0, 0
  300. /*
  301. * before relocating, we have to setup RAM timing
  302. * because memory timing is board-dependend, you will
  303. * find a lowlevel_init.S in your board directory.
  304. */
  305. mov ip, lr
  306. bl lowlevel_init
  307. mov lr, ip
  308. mov pc, lr
  309. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  310. /*
  311. *************************************************************************
  312. *
  313. * Interrupt handling
  314. *
  315. *************************************************************************
  316. */
  317. @
  318. @ IRQ stack frame.
  319. @
  320. #define S_FRAME_SIZE 72
  321. #define S_OLD_R0 68
  322. #define S_PSR 64
  323. #define S_PC 60
  324. #define S_LR 56
  325. #define S_SP 52
  326. #define S_IP 48
  327. #define S_FP 44
  328. #define S_R10 40
  329. #define S_R9 36
  330. #define S_R8 32
  331. #define S_R7 28
  332. #define S_R6 24
  333. #define S_R5 20
  334. #define S_R4 16
  335. #define S_R3 12
  336. #define S_R2 8
  337. #define S_R1 4
  338. #define S_R0 0
  339. #define MODE_SVC 0x13
  340. #define I_BIT 0x80
  341. /*
  342. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  343. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  344. */
  345. .macro bad_save_user_regs
  346. sub sp, sp, #S_FRAME_SIZE
  347. stmia sp, {r0 - r12} @ Calling r0-r12
  348. ldr r2, IRQ_STACK_START_IN
  349. ldmia r2, {r2 - r3} @ get pc, cpsr
  350. add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
  351. add r5, sp, #S_SP
  352. mov r1, lr
  353. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  354. mov r0, sp
  355. .endm
  356. .macro irq_save_user_regs
  357. sub sp, sp, #S_FRAME_SIZE
  358. stmia sp, {r0 - r12} @ Calling r0-r12
  359. add r7, sp, #S_PC
  360. stmdb r7, {sp, lr}^ @ Calling SP, LR
  361. str lr, [r7, #0] @ Save calling PC
  362. mrs r6, spsr
  363. str r6, [r7, #4] @ Save CPSR
  364. str r0, [r7, #8] @ Save OLD_R0
  365. mov r0, sp
  366. .endm
  367. .macro irq_restore_user_regs
  368. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  369. mov r0, r0
  370. ldr lr, [sp, #S_PC] @ Get PC
  371. add sp, sp, #S_FRAME_SIZE
  372. /* return & move spsr_svc into cpsr */
  373. subs pc, lr, #4
  374. .endm
  375. .macro get_bad_stack
  376. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  377. str lr, [r13] @ save caller lr / spsr
  378. mrs lr, spsr
  379. str lr, [r13, #4]
  380. mov r13, #MODE_SVC @ prepare SVC-Mode
  381. @ msr spsr_c, r13
  382. msr spsr, r13
  383. mov lr, pc
  384. movs pc, lr
  385. .endm
  386. .macro get_irq_stack @ setup IRQ stack
  387. ldr sp, IRQ_STACK_START
  388. .endm
  389. .macro get_fiq_stack @ setup FIQ stack
  390. ldr sp, FIQ_STACK_START
  391. .endm
  392. /*
  393. * exception handlers
  394. */
  395. .align 5
  396. undefined_instruction:
  397. get_bad_stack
  398. bad_save_user_regs
  399. bl do_undefined_instruction
  400. .align 5
  401. software_interrupt:
  402. get_bad_stack
  403. bad_save_user_regs
  404. bl do_software_interrupt
  405. .align 5
  406. prefetch_abort:
  407. get_bad_stack
  408. bad_save_user_regs
  409. bl do_prefetch_abort
  410. .align 5
  411. data_abort:
  412. get_bad_stack
  413. bad_save_user_regs
  414. bl do_data_abort
  415. .align 5
  416. not_used:
  417. get_bad_stack
  418. bad_save_user_regs
  419. bl do_not_used
  420. #ifdef CONFIG_USE_IRQ
  421. .align 5
  422. irq:
  423. get_irq_stack
  424. irq_save_user_regs
  425. bl do_irq
  426. irq_restore_user_regs
  427. .align 5
  428. fiq:
  429. get_fiq_stack
  430. /* someone ought to write a more effiction fiq_save_user_regs */
  431. irq_save_user_regs
  432. bl do_fiq
  433. irq_restore_user_regs
  434. #else
  435. .align 5
  436. irq:
  437. get_bad_stack
  438. bad_save_user_regs
  439. bl do_irq
  440. .align 5
  441. fiq:
  442. get_bad_stack
  443. bad_save_user_regs
  444. bl do_fiq
  445. #endif