 Dave Liu
|
ec145e87b8
fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
|
15 years ago |
|
Dave Liu
|
3e731aaba3
fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave
|
15 years ago |
|
Dave Liu
|
1aa3d08a02
fsl-ddr: add override for the Rtt_Wr
|
15 years ago |
|
Dave Liu
|
bdc9f7b5ea
fsl-ddr: add the override for write leveling
|
15 years ago |
|
Dave Liu
|
0a71c92c7e
fsl-ddr: Fix power-down timing settings
|
15 years ago |
 Kumar Gala
|
6d8565a1ed
ppc/8xxx: Misc DDR related fixes
|
16 years ago |
|
Kumar Gala
|
2abbd31da6
ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist
|
16 years ago |
|
Kumar Gala
|
e7563aff17
fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT
|
16 years ago |
|
Dave Liu
|
c360ceac02
fsl-ddr: add the DDR3 SPD infrastructure
|
16 years ago |
|
Dave Liu
|
6a81978367
fsl-ddr: Fix two bugs in the ddr infrastructure
|
16 years ago |
|
Dave Liu
|
22cca7e1cd
fsl-ddr: make the self refresh idle threshold configurable
|
16 years ago |
|
Dave Liu
|
22ff3d0134
fsl-ddr: clean up the ddr code for DDR3 controller
|
16 years ago |
|
Dave Liu
|
80ee3ce6d7
fsl-ddr: update the bit mask for DDR3 controller
|
16 years ago |
 Haiying Wang
|
1f293b417a
Add debug information for DDR controller registers
|
17 years ago |
|
Haiying Wang
|
dbbbb3abef
Make DDR interleaving mode work correctly
|
17 years ago |
|
Kumar Gala
|
302e52e0b1
Fix compiler warning in mpc8xxx ddr code
|
17 years ago |
|
Kumar Gala
|
58e5e9aff1
FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
|
17 years ago |
