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+Freescale MPC837xEMDS Board
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+-----------------------------------------
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+1. Board Switches and Jumpers
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+1.0 There are four Dual-In-Line Packages(DIP) Switches on MPC837xEMDS board
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+ For some reason, the HW designers describe the switch settings
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+ in terms of 0 and 1, and then map that to physical switches where
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+ the label "On" refers to logic 0 and "Off" is logic 1.
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+
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+ Switch bits are numbered 1 through, like, 4 6 8 or 10, but the
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+ bits may contribute to signals that are numbered based at 0,
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+ and some of those signals may be high-bit-number-0 too. Heed
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+ well the names and labels and do not get confused.
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+
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+ "Off" == 1
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+ "On" == 0
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+
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+ SW4[8] is the bit labled 8 on Switch 4.
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+ SW2[1:6] refers to bits labeled 1 through 6 in order on switch 2.
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+ SW2[1:8]= 0000_0001 refers to bits labeled 1 through 7 is set as "On"
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+ and bits labeled 8 is set as "Off".
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+
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+1.1 For the MPC837xEMDS Processor Board
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+
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+ First, make sure the board default setting is consistent with the
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+ document shipped with your board. Then apply the following setting:
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+ SW3[1-8]= 0011_0000 (BOOTSEQ, ROMLOC setting)
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+ SW4[1-8]= 0000_0110 (core PLL setting)
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+ SW5[1-8]= 1001_1000 (system PLL, boot up from low end of flash)
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+ SW6[1-8]= 0000_1000 (HRCW is read from NOR FLASH)
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+ SW7[1-8]= 0110_1101 (TSEC1/2 interface setting - RGMII)
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+ J3 2-3, TSEC1 LVDD1 with 2.5V
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+ J6 2-3, TSEC2 LVDD2 with 2.5V
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+ J9 2-3, CLKIN from osc on board
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+ J10 removed, CS0 connect to NOR flash; when mounted, CS0 connect to NAND
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+ J11 removed, Hardware Reset Configuration Word load from FLASH(NOR or NAND)
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+ mounted, HRCW load from BCSR.
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+
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+ on board Oscillator: 66M
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+
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+2. Memory Map
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+
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+2.1. The memory map should look pretty much like this:
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+
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+ 0x0000_0000 0x7fff_ffff DDR 2G
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+ 0x8000_0000 0x8fff_ffff PCI MEM prefetch 256M
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+ 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
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+ 0xc000_0000 0xdfff_ffff Empty 512M
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+ 0xe000_0000 0xe00f_ffff Int Mem Reg Space 1M
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+ 0xe010_0000 0xe02f_ffff Empty 2M
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+ 0xe030_0000 0xe03f_ffff PCI IO 1M
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+ 0xe040_0000 0xe05f_ffff Empty 2M
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+ 0xe060_0000 0xe060_8000 NAND Flash 32K
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+ 0xf400_0000 0xf7ff_ffff Empty 64M
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+ 0xf800_0000 0xf800_7fff BCSR on CS1 32K
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+ 0xfe00_0000 0xffff_ffff NOR Flash on CS0 32M
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+
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+3. Definitions
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+
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+3.1 Explanation of NEW definitions in:
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+
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+ include/configs/MPC837XEMDS.h
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+
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+ CONFIG_MPC83XX MPC83xx family for both MPC837x and MPC8360
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+ CONFIG_MPC837X MPC837x specific
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+ CONFIG_MPC837XEMDS MPC837XEMDS board specific
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+
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+4. Compilation
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+
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+ Assuming you're using BASH shell:
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+
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+ export CROSS_COMPILE=your-cross-compile-prefix
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+ cd u-boot
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+ make distclean
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+ make MPC837XEMDS_config
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+ make
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+
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+5. Downloading and Flashing Images
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+
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+5.0 Download over serial line using Kermit:
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+
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+ loadb
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+ [Drop to kermit:
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+ ^\c
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+ send <u-boot-bin-image>
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+ c
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+ ]
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+
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+
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+ Or via tftp:
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+
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+ tftp 40000 u-boot.bin
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+
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+5.1 Reflash U-boot Image using U-boot
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+
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+ tftp 40000 u-boot.bin
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+ protect off fe000000 fe1fffff
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+ erase fe000000 fe1fffff
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+
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+ cp.b 40000 fe000000 xxxx
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+
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+You have to supply the correct byte count with 'xxxx' from the TFTP result log.
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+
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+6. Notes
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+ 1) The console baudrate for MPC837XEMDS is 115200bps.
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Dave Liu