* Patch by Paul Ruhland, 10 Jun 2004:

  fix support for Logic SDK-LH7A404 board and clean up the
  LH7A404 register macros.

* Patch by Matthew McClintock, 10 Jun 2004:
  Modify code to select correct serial clock on Sandpoint8245

CHANGELOG

@@ -2,6 +2,13 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Patch by Paul Ruhland, 10 Jun 2004:
+  fix support for Logic SDK-LH7A404 board and clean up the 
+  LH7A404 register macros.
+
+* Patch by Matthew McClintock, 10 Jun 2004:
+  Modify code to select correct serial clock on Sandpoint8245
+
 * Patch by Robert Schwebel, 10 Jun 2004:
   Add support for Intel K3 strata flash.
 

Makefile

@@ -1062,7 +1062,8 @@ integratorcp_config :	unconfig
 integratorap_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorap
 
-lpd7a400_config:	unconfig
+lpd7a400_config \
+lpd7a404_config:	unconfig
 	@./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
 
 omap1510inn_config :	unconfig

board/lpd7a40x/lpd7a40x.c

@@ -28,13 +28,14 @@
 #include <common.h>
 #if defined(CONFIG_LH7A400)
 #include <lh7a400.h>
-#include <lpd7a400_cpld.h>
 #elif defined(CONFIG_LH7A404)
 #include <lh7a404.h>
-#include <lpd7a404_cpld.h>
 #else
 #error "No CPU defined!"
 #endif
+#include <asm/mach-types.h>
+
+#include <lpd7a400_cpld.h>
 
 /*
  * Miscellaneous platform dependent initialisations
@@ -46,8 +47,6 @@ int board_init (void)
 
 	/* set up the I/O ports */
 
-#if defined(CONFIG_LH7A400)
-
 	/* enable flash programming */
 	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_FLASH_REG)) |= FLASH_FPEN;
 
@@ -59,10 +58,12 @@ int board_init (void)
 	*(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_EXTGPIO_REG)) =
 		(EXTGPIO_STATUS1|EXTGPIO_GPIO1) & ~(EXTGPIO_STATUS2);
 
+#if defined(CONFIG_LH7A400)
 	/* arch number of Logic-Board - MACH_TYPE_LPD7A400 */
 	gd->bd->bi_arch_number = MACH_TYPE_LPD7A400;
-
 #elif defined(CONFIG_LH7A404)
+	/* arch number of Logic-Board - MACH_TYPE_LPD7A400 */
+	gd->bd->bi_arch_number = MACH_TYPE_LPD7A404;
 #endif
 
 	/* adress of boot parameters */

cpu/lh7a40x/interrupts.c

@@ -41,7 +41,7 @@ static ulong timer_load_val = 0;
 /* macro to read the 16 bit timer */
 static inline ulong READ_TIMER(void)
 {
-	LH7A40X_TIMERS_PTR(timers);
+	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
 	lh7a40x_timer_t* timer = &timers->timer1;
 
 	return (timer->value & 0x0000ffff);
@@ -185,7 +185,7 @@ static ulong lastdec;
 
 int interrupt_init (void)
 {
-	LH7A40X_TIMERS_PTR(timers);
+	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
 	lh7a40x_timer_t* timer = &timers->timer1;
 
 	/* a periodic timer using the 508kHz source */

cpu/lh7a40x/serial.c

@@ -34,7 +34,7 @@
 void serial_setbrg (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	LH7A40X_UART_PTR(uart,UART_CONSOLE);
+	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
 	int i;
 	unsigned int reg = 0;
 
@@ -62,7 +62,7 @@ void serial_setbrg (void)
  */
 int serial_init (void)
 {
-	LH7A40X_UART_PTR(uart,UART_CONSOLE);
+	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
 
 	/* UART must be enabled before writing to any config registers */
 	uart->con |= (UART_EN);
@@ -96,7 +96,7 @@ int serial_init (void)
  */
 int serial_getc (void)
 {
-	LH7A40X_UART_PTR(uart,UART_CONSOLE);
+	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
 
 	/* wait for character to arrive */
 	while (uart->status & UART_RXFE);
@@ -142,7 +142,7 @@ void enable_putc(void)
  */
 void serial_putc (const char c)
 {
-	LH7A40X_UART_PTR(uart,UART_CONSOLE);
+	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
 
 #ifdef CONFIG_MODEM_SUPPORT
 	if (be_quiet)
@@ -169,7 +169,7 @@ void serial_putc (const char c)
  */
 int serial_tstc (void)
 {
-	LH7A40X_UART_PTR(uart,UART_CONSOLE);
+	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
 
 	return(!(uart->status & UART_RXFE));
 }

cpu/lh7a40x/speed.c

@@ -46,7 +46,7 @@ ulong get_PLLCLK (void)
 /* return FCLK frequency */
 ulong get_FCLK (void)
 {
-	LH7A40X_CSC_PTR (csc);
+	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
 	ulong maindiv1, maindiv2, prediv, ps;
 
 	/*
@@ -68,7 +68,7 @@ ulong get_FCLK (void)
 /* return HCLK frequency */
 ulong get_HCLK (void)
 {
-	LH7A40X_CSC_PTR (csc);
+	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
 
 	return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1));
 }
@@ -76,7 +76,7 @@ ulong get_HCLK (void)
 /* return PCLK frequency */
 ulong get_PCLK (void)
 {
-	LH7A40X_CSC_PTR (csc);
+	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
 
 	return (get_HCLK () /
 		(1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1)));

include/asm-arm/mach-types.h

@@ -357,6 +357,8 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_LOOX600              342
 #define MACH_TYPE_NIOP                 343
 #define MACH_TYPE_DM310                344
+#define MACH_TYPE_LPD7A400             389
+#define MACH_TYPE_LPD7A404             390
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -4474,6 +4476,30 @@ extern unsigned int __machine_arch_type;
 # define machine_is_dm310()	(0)
 #endif
 
+#ifdef CONFIG_ARCH_LPD7A400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPD7A400
+# endif
+# define machine_is_lpd7a400()	(machine_arch_type == MACH_TYPE_LPD7A400)
+#else
+# define machine_is_lpd7a400()	(0)
+#endif
+
+#ifdef CONFIG_ARCH_LPD7A404
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LPD7A404
+# endif
+# define machine_is_lpd7a404()	(machine_arch_type == MACH_TYPE_LPD7A404)
+#else
+# define machine_is_lpd7a404()	(0)
+#endif
+
 /*
  * These have not yet been registered
  */

include/configs/Sandpoint8245.h

@@ -224,8 +224,12 @@
 
 #define CFG_NS16550_REG_SIZE	1
 
-#define CFG_NS16550_CLK		1843200
-
+#if (CONFIG_CONS_INDEX > 2)
+#define CFG_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
+#else
+#define CFG_NS16550_CLK         1843200
+#endif
+                                                                                
 #define CFG_NS16550_COM1	(CFG_ISA_IO + CFG_NS87308_UART1_BASE)
 #define CFG_NS16550_COM2	(CFG_ISA_IO + CFG_NS87308_UART2_BASE)
 #define CFG_NS16550_COM3	(CFG_EUMB_ADDR + 0x4500)

include/configs/lpd7a400-10.h

@@ -27,8 +27,8 @@
 
 
 #define CONFIG_ARM920T		1	/* arm920t core */
-#define CONFIG_LH7A40X		1	/* Sharp LH7A400 SoC */
-#define CONFIG_LH7A400		1
+#define CONFIG_LH7A40X		1	/* Sharp LH7A40x SoC family */
+#define CONFIG_LH7A400		1   /* Sharp LH7A400 S0C */
 
 /* The system clock PLL input frequency */
 #define CONFIG_SYS_CLK_FREQ		14745600   /* System Clock PLL Input (Hz) */

include/configs/lpd7a400.h

@@ -21,6 +21,8 @@
 #ifndef __LPD7A400_H_
 #define __LPD7A400_H_
 
+#define CONFIG_LPD7A400		/* Logic LH7A400 SDK */
+
 /*
  * If we are developing, we might want to start armboot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
@@ -29,15 +31,11 @@
 
 #undef CONFIG_USE_IRQ
 
-#define MACH_TYPE_LPD7A400	389
-
 /*
  * This board uses the logic LH7A400-10 card engine
  */
 #include <configs/lpd7a400-10.h>
 
-#define CONFIG_LPD7A400		/* Logic LH7A400 SDK */
-
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs	*/
 #define CONFIG_SETUP_MEMORY_TAGS	1
 #define CONFIG_INITRD_TAG		1

include/configs/lpd7a404-10.h

@@ -0,0 +1,80 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Logic LH7A400-10 card engine
+ */
+
+#ifndef __LPD7A404_10_H
+#define __LPD7A404_10_H
+
+
+#define CONFIG_ARM920T		1	/* arm920t core */
+#define CONFIG_LH7A40X		1	/* Sharp LH7A40x SoC family */
+#define CONFIG_LH7A404		1   /* Sharp LH7A404 SoC */
+
+/* The system clock PLL input frequency */
+#define CONFIG_SYS_CLK_FREQ		14745600   /* System Clock PLL Input (Hz) */
+
+/* ticks per second */
+#define CFG_HZ	(508469)
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1		0xc0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
+
+#define CFG_FLASH_BASE		0x00000000 /* Flash Bank #1 */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	(64)	/* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(5*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(5*CFG_HZ) /* Timeout for Flash Write */
+
+/*----------------------------------------------------------------------
+ * Using SMC91C111 LAN chip
+ *
+ * Default IO base of chip is 0x300, Card Engine has this address lines
+ * (LAN chip) tied to Vcc, so we just care about the chip select
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE	(0x70000000)
+#undef CONFIG_SMC_USE_32_BIT
+#define CONFIG_SMC_USE_IOFUNCS
+
+#endif  /* __LPD7A404_10_H */

include/configs/lpd7a404.h

@@ -0,0 +1,112 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __LPD7A404_H_
+#define __LPD7A404_H_
+
+#define CONFIG_LPD7A404		/* Logic LH7A400 SDK */
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#define CONFIG_INIT_CRITICAL	/* undef for developing */
+
+#undef CONFIG_USE_IRQ
+
+/*
+ * This board uses the logic LH7A404-10 card engine
+ */
+#include <configs/lpd7a404-10.h>
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONSOLE_UART2	/* UART2 LH7A40x for console */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_IPADDR		192.168.1.100
+#define CONFIG_NETMASK		255.255.1.0
+#define CONFIG_SERVERIP		192.168.1.1
+
+#define	CONFIG_TIMESTAMP	1	/* Print timestamp info for images */
+
+#ifndef USE_920T_MMU
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE))
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE)
+#endif
+
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_BOOTDELAY	3
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
+/* what's this ? it's not used anywhere */
+#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP				/* undef to save memory		*/
+#define	CFG_PROMPT		"LPD7A404> "	/* Monitor Command Prompt	*/
+#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0xc0300000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0xc0500000	/* 2 MB in DRAM	*/
+
+#undef  CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define	CFG_LOAD_ADDR		0xc0f00000	/* default load address	*/
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* size and location of u-boot in flash */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define CFG_MONITOR_LEN		(256<<10)
+
+#define	CFG_ENV_IS_IN_FLASH	1
+
+/* Address and size of Primary Environment Sector	*/
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0xFC0000)
+#define CFG_ENV_SIZE		0x40000
+
+#endif  /* __LPD7A404_H_ */

include/lh7a400.h

@@ -38,35 +38,17 @@ typedef struct {
 	volatile u32  rsvd3;
 } /*__attribute__((__packed__))*/ lh7a400_interrupt_t;
 #define LH7A400_INTERRUPT_BASE    (0x80000500)
-#define LH7A400_INTERRUPT_PTR(name)  lh7a400_interrupt_t* name = (lh7a400_interrupt_t*) LH7A400_INTERRUPT_BASE
+#define LH7A400_INTERRUPT_PTR     ((lh7a400_interrupt_t*) LH7A400_INTERRUPT_BASE)
 
 /* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
 typedef struct {
-	volatile u32  maxcnt;
-	volatile u32  base;
-	volatile u32  current;
-	volatile u32  rsvd1;
-} lh7a400_dmabuf_t;
-
-typedef struct {
-	volatile u32      control;
-	volatile u32      interrupt;
-	volatile u32      rsvd1;
-	volatile u32      status;
-	volatile u32      rsvd2;
-	volatile u32      remain;
-	volatile u32      rsvd3;
-	volatile u32      rsvd4;
-	lh7a400_dmabuf_t  buf[2];
-} /*__attribute__((__packed__))*/ lh7a400_dmachan_t;
-
-typedef struct {
-	lh7a400_dmachan_t  chan[15];
+	lh7a40x_dmachan_t  chan[15];
 	volatile u32       glblint;
 	volatile u32       rsvd1;
 	volatile u32       rsvd2;
 	volatile u32       rsvd3;
 } /*__attribute__((__packed__))*/ lh7a400_dma_t;
+
 #define LH7A400_DMA_BASE      (0x80002800)
 #define DMA_USBTX_OFFSET      (0x000)
 #define DMA_USBRX_OFFSET      (0x040)
@@ -74,20 +56,20 @@ typedef struct {
 #define DMA_MMCRX_OFFSET      (0x0C0)
 #define DMA_AC97_BASE         (0x80002A00)
 
-#define LH7A400_DMA_PTR(name)    lh7a400_dma_t* name = (lh7a400_dma_t*) LH7A400_DMA_BASE
-#define LH7A400_DMA_USBTX(name) \
-	lh7a400_dmachan_t* name = (lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBTX_OFFSET)
-#define LH7A400_DMA_USBRX(name) \
-	lh7a400_dmachan_t* name = (lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBRX_OFFSET)
-#define LH7A400_DMA_MMCTX(name) \
-	lh7a400_dmachan_t* name = (lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCTX_OFFSET)
-#define LH7A400_DMA_MMCRX(name) \
-	lh7a400_dmachan_t* name = (lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCRX_OFFSET)
-#define LH7A400_AC97RX(name,n) \
-	lh7a400_dmachan_t* name = (lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
-	((2*n) * sizeof(lh7a400_dmachan_t)))
-#define LH7A400_AC97TX(name,n) \
-	lh7a400_dmachan_t* name = (lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
-	(((2*n)+1) * sizeof(lh7a400_dmachan_t)))
+#define LH7A400_DMA_PTR    ((lh7a400_dma_t*) LH7A400_DMA_BASE)
+#define LH7A400_DMA_USBTX \
+	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBTX_OFFSET))
+#define LH7A400_DMA_USBRX \
+	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBRX_OFFSET))
+#define LH7A400_DMA_MMCTX \
+	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCTX_OFFSET))
+#define LH7A400_DMA_MMCRX \
+	((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCRX_OFFSET))
+#define LH7A400_AC97RX(n) \
+	((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
+	((2*n) * sizeof(lh7a400_dmachan_t))))
+#define LH7A400_AC97TX(n) \
+	((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
+	(((2*n)+1) * sizeof(lh7a400_dmachan_t))))
 
 #endif  /* __LH7A400_H__ */

include/lh7a404.h

@@ -0,0 +1,83 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * lh7a404 SoC interface
+ */
+
+#ifndef __LH7A404_H__
+#define __LH7A404_H__
+
+#include "lh7a40x.h"
+
+/* Interrupt Controller (userguide 8.2.1) */
+typedef struct {
+	volatile u32  irqstatus;
+	volatile u32  fiqstatus;
+	volatile u32  rawintr;
+	volatile u32  intsel;
+	volatile u32  inten;
+	volatile u32  intenclr;
+	volatile u32  softint;
+	volatile u32  softintclr;
+	volatile u32  protect;
+	volatile u32  unused1;
+	volatile u32  unused2;
+	volatile u32  vectaddr;
+	volatile u32  nvaddr;
+	volatile u32  unused3[32];
+	volatile u32  vad[16];
+	volatile u32  unused4[44];
+	volatile u32  vectcntl[16];
+	volatile u32  unused5[44];
+	volatile u32  itcr;
+	volatile u32  itip1;
+	volatile u32  itip2;
+	volatile u32  itop1;
+	volatile u32  itop2;
+	volatile u32  unused6[333];
+	volatile u32  periphid[4];
+	volatile u32  pcellid[4];
+} /*__attribute__((__packed__))*/ lh7a404_vic_t;
+#define LH7A404_VIC_BASE	(0x80008000)
+#define LH7A400_VIC_PTR(x)  ((lh7a404_vic_t*)(LH7A400_VIC_BASE + (x*0x2000)))
+
+
+typedef struct {
+	lh7a40x_dmachan_t  m2p0_tx;
+	lh7a40x_dmachan_t  m2p1_rx;
+	lh7a40x_dmachan_t  m2p2_tx;
+	lh7a40x_dmachan_t  m2p3_rx;
+	lh7a40x_dmachan_t  m2m0;
+	lh7a40x_dmachan_t  m2m1;
+	lh7a40x_dmachan_t  unused1;
+	lh7a40x_dmachan_t  unused2;
+	lh7a40x_dmachan_t  m2p5_rx;
+	lh7a40x_dmachan_t  m2p4_tx;
+	lh7a40x_dmachan_t  m2p7_rx;
+	lh7a40x_dmachan_t  m2p6_tx;
+	lh7a40x_dmachan_t  m2p9_rx;
+	lh7a40x_dmachan_t  m2p8_tx;
+	volatile u32       chanarb;
+	volatile u32       glblint;
+} /*__attribute__((__packed__))*/ lh7a400_dma_t;
+
+
+#endif  /* __LH7A404_H__ */

include/lh7a40x.h

@@ -38,8 +38,8 @@ typedef struct {
 	lh7a40x_pccard_t  pccard[2];
 	volatile u32	  pcmciacon;
 } /*__attribute__((__packed__))*/ lh7a40x_smc_t;
-#define LH7A40X_SMC_BASE    (0x80002000)
-#define LH7A40X_SMC_PTR(name)  lh7a40x_smc_t* name = (lh7a40x_smc_t*) LH7A40X_SMC_BASE
+#define LH7A40X_SMC_BASE  (0x80002000)
+#define LH7A40X_SMC_PTR   ((lh7a40x_smc_t*) LH7A40X_SMC_BASE)
 
 /* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */
 typedef struct {
@@ -49,8 +49,8 @@ typedef struct {
 	volatile u32  bootstat;
 	volatile u32  sdcsc[4];
 } /*__attribute__((__packed__))*/ lh7a40x_sdmc_t;
-#define LH7A40X_SDMC_BASE    (0x80002400)
-#define LH7A40X_SDMC_PTR(name)  lh7a40x_sdmc_t* name = (lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE
+#define LH7A40X_SDMC_BASE  (0x80002400)
+#define LH7A40X_SDMC_PTR   ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE)
 
 /* (CSC) Clock and State Controller (userguide 6.2.1) */
 typedef struct {
@@ -68,7 +68,7 @@ typedef struct {
 	volatile u32  usbreset;
 } /*__attribute__((__packed__))*/ lh7a40x_csc_t;
 #define LH7A40X_STPWR_BASE  (0x80000400)
-#define LH7A40X_CSC_PTR(name)  lh7a40x_csc_t* name = (lh7a40x_csc_t*) LH7A40X_STPWR_BASE
+#define LH7A40X_CSC_PTR     ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE)
 
 #define CLKSET_SMCROM		(0x01000000)
 #define CLKSET_PS		(0x000C0000)
@@ -85,6 +85,27 @@ typedef struct {
 #define CLKSET_PREDIV		(0x0000007C)
 #define CLKSET_HCLKDIV		(0x00000003)
 
+/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
+typedef struct {
+	volatile u32  maxcnt;
+	volatile u32  base;
+	volatile u32  current;
+	volatile u32  rsvd1;
+} lh7a40x_dmabuf_t;
+
+typedef struct {
+	volatile u32      control;
+	volatile u32      interrupt;
+	volatile u32      rsvd1;
+	volatile u32      status;
+	volatile u32      rsvd2;
+	volatile u32      remain;
+	volatile u32      rsvd3;
+	volatile u32      rsvd4;
+	lh7a40x_dmabuf_t  buf[2];
+} /*__attribute__((__packed__))*/ lh7a40x_dmachan_t;
+
+
 /* (WDT) Watchdog Timer (userguide 11.2.1) */
 typedef struct {
 	volatile u32  ctl;
@@ -93,7 +114,7 @@ typedef struct {
 	volatile u32  count[4];
 } /*__attribute__((__packed__))*/ lh7a40x_wdt_t;
 #define LH7A40X_WDT_BASE    (0x80001400)
-#define LH7A40X_WDT_PTR(name)  lh7a40x_wdt_t* name = (lh7a40x_wdt_t*) LH7A40X_WDT_BASE
+#define LH7A40X_WDT_PTR     ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE)
 
 /* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */
 typedef struct {
@@ -106,7 +127,7 @@ typedef struct {
 	volatile u32  rsvd1[58];
 } /*__attribute__((__packed__))*/ lh7a40x_rtc_t;
 #define LH7A40X_RTC_BASE    (0x80000D00)
-#define LH7A40X_RTC_PTR(name)  lh7a40x_rtc_t* name = (lh7a40x_rtc_t*) LH7A40X_RTC_BASE
+#define LH7A40X_RTC_PTR     ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE)
 
 /* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */
 typedef struct {
@@ -127,7 +148,7 @@ typedef struct {
 	/*volatile u32     rsvd2;*/
 } /*__attribute__((__packed__))*/ lh7a40x_timers_t;
 #define LH7A40X_TIMERS_BASE    (0x80000C00)
-#define LH7A40X_TIMERS_PTR(name)  lh7a40x_timers_t* name = (lh7a40x_timers_t*) LH7A40X_TIMERS_BASE
+#define LH7A40X_TIMERS_PTR     ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE)
 
 #define TIMER_EN	(0x00000080)
 #define TIMER_PER	(0x00000040)
@@ -146,7 +167,7 @@ typedef struct {
 	/*volatile u32  rsvd1[58];*/
 } /*__attribute__((__packed__))*/ lh7a40x_ssp_t;
 #define LH7A40X_SSP_BASE    (0x80000B00)
-#define LH7A40X_SSP_PTR(name)  lh7a40x_ssp_t* name = (lh7a40x_ssp_t*) LH7A40X_SSP_BASE
+#define LH7A40X_SSP_PTR     ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE)
 
 /* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */
 typedef struct {
@@ -160,9 +181,9 @@ typedef struct {
 	volatile u32  isr;
 	volatile u32  rsvd1[56];
 } /*__attribute__((__packed__))*/ lh7a40x_uart_t;
-#define LH7A40X_UART_BASE      (0x80000600)
-#define LH7A40X_UART_PTR(name,n) \
-	lh7a40x_uart_t* name = (lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t)))
+#define LH7A40X_UART_BASE    (0x80000600)
+#define LH7A40X_UART_PTR(n) \
+	((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t))))
 
 #define UART_BE		(0x00000800)      /* the rx error bits */
 #define UART_OE		(0x00000400)
@@ -249,7 +270,7 @@ typedef struct {
 	volatile u32  phpd;
 } /*__attribute__((__packed__))*/ lh7a40x_gpioint_t;
 #define LH7A40X_GPIOINT_BASE    (0x80000E00)
-#define LH7A40X_GPIOINT_PTR(name)  lh7a40x_gpioint_t* name = (lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE
+#define LH7A40X_GPIOINT_PTR     ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE)
 
 /* Embedded SRAM */
 #define CFG_SRAM_BASE	(0xB0000000)