Prepare v2012.04-rc2; minor Coding Style cleanup

Signed-off-by: Wolfgang Denk <wd@denx.de>

Makefile

@@ -24,7 +24,7 @@
 VERSION = 2012
 PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc2
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else

arch/sh/include/asm/mmc.h

@@ -15,4 +15,3 @@
 int mmcif_mmc_init(void);
 
 #endif /* _SH_MMC_H_ */
-

board/freescale/mx6qsabrelite/mx6qsabrelite.c

@@ -11,7 +11,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -34,16 +34,16 @@
 #include <netdev.h>
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
-       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
        PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
 #define SPI_PAD_CTRL (PAD_CTL_HYS |				\
@@ -176,11 +176,11 @@ int board_mmc_getcd(struct mmc *mmc)
        int ret;
 
        if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
-               gpio_direction_input(192); /*GPIO7_0*/
-               ret = !gpio_get_value(192);
+	       gpio_direction_input(192); /*GPIO7_0*/
+	       ret = !gpio_get_value(192);
        } else {
-               gpio_direction_input(38); /*GPIO2_6*/
-               ret = !gpio_get_value(38);
+	       gpio_direction_input(38); /*GPIO2_6*/
+	       ret = !gpio_get_value(38);
        }
 
        return ret;
@@ -192,23 +192,23 @@ int board_mmc_init(bd_t *bis)
        u32 index = 0;
 
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
-               switch (index) {
-               case 0:
-                       imx_iomux_v3_setup_multiple_pads(
-                               usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
-                       break;
-               case 1:
-                       imx_iomux_v3_setup_multiple_pads(
-                               usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
-                       break;
-               default:
-                       printf("Warning: you configured more USDHC controllers"
-                               "(%d) then supported by the board (%d)\n",
-                               index + 1, CONFIG_SYS_FSL_USDHC_NUM);
-                       return status;
-               }
-
-               status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+	       switch (index) {
+	       case 0:
+		       imx_iomux_v3_setup_multiple_pads(
+			       usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		       break;
+	       case 1:
+		       imx_iomux_v3_setup_multiple_pads(
+			       usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+		       break;
+	       default:
+		       printf("Warning: you configured more USDHC controllers"
+			       "(%d) then supported by the board (%d)\n",
+			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+		       return status;
+	       }
+
+	       status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
        }
 
        return status;
@@ -250,7 +250,7 @@ int board_phy_config(struct phy_device *phydev)
 			MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
- 
+
 	return 0;
 }
 

doc/README.sbc8548

@@ -23,7 +23,7 @@ of each choice are listed below.
 
 Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot
 will be left empty (M66EN high), and so the board will operate with
-a base clock of 66MHz.  Note that you need both PCI enabled in u-boot
+a base clock of 66MHz.	Note that you need both PCI enabled in u-boot
 and linux in order to have functional PCI under linux.
 
 The second enables PCI support and builds for a 33MHz clock rate.  Note
@@ -37,29 +37,29 @@ card. [The above discussion assumes that the SW2[1-4] has not been changed
 to reflect a different CCB:SYSCLK ratio]
 
 The third option builds PCI support in, and leaves the clocking at the
-default 66MHz.  Options four and five are just repeats of option two
+default 66MHz.	Options four and five are just repeats of option two
 and three, but with PCI-e support enabled as well.
 
 PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx
-is shown below for sbc8548_PCI_66_PCIE_config.  (Note that PCI-e with
+is shown below for sbc8548_PCI_66_PCIE_config.	(Note that PCI-e with
 a 33MHz PCI configuration is currently untested.)
 
     => pci 0
     Scanning PCI devices on bus 0
-    BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
+    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
     _____________________________________________________________
-    00.00.00   0x1057     0x0012     Processor               0x20
-    00.01.00   0x8086     0x1026     Network controller      0x00
+    00.00.00   0x1057	  0x0012     Processor		     0x20
+    00.01.00   0x8086	  0x1026     Network controller	     0x00
     => pci 1
     Scanning PCI devices on bus 1
-    BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
+    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
     _____________________________________________________________
-    01.00.00   0x1957     0x0012     Processor               0x20
+    01.00.00   0x1957	  0x0012     Processor		     0x20
     => pci 2
     Scanning PCI devices on bus 2
-    BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
+    BusDevFun  VendorId	  DeviceId   Device Class	Sub-Class
     _____________________________________________________________
-    02.00.00   0x1148     0x9e00     Network controller      0x00
+    02.00.00   0x1148	  0x9e00     Network controller	     0x00
     =>
 
 Memory Size and using SPD:
@@ -80,10 +80,10 @@ You can also visually inspect the board to see if this hardware
 fix has been applied:
 
       1) Remove R314 (RES-R0174-033, 1K, 0603). R314 is located on
-         the back of the PCB behind the DDR SDRAM SODIMM connector.
+	 the back of the PCB behind the DDR SDRAM SODIMM connector.
       2) Solder RES-R0174-033 (1K, 0603) resistor from R314 pin 2 pad
-         to R313 pin 2.  Pin 2 for each resistor is the end of the
-         resistor closest to the CPU.
+	 to R313 pin 2.	 Pin 2 for each resistor is the end of the
+	 resistor closest to the CPU.
 
 Boards without the mod will have R314 and R313 in parallel, like "||".
 After the mod, they will be touching and form an "L" shape.
@@ -155,7 +155,7 @@ Hardware Reference:
 ===================
 
 The following contains some summary information on hardware settings
-that are relevant to u-boot, based on the board manual.  For the
+that are relevant to u-boot, based on the board manual.	 For the
 most up to date and complete details of the board, please request the
 reference manual ERG-00327-001.pdf from www.windriver.com
 

doc/device-tree-bindings/i2c/tegra20-i2c.txt

@@ -4,10 +4,10 @@ Added in U-Boot:
 
 Required properties:
  - clocks : Two clocks must be given, each as a phandle to the Tegra's
-            CAR node and the clock number as a parameter:
+	    CAR node and the clock number as a parameter:
      - the I2C clock to use for the peripheral
      - the pll_p_out3 clock, which can be used for fast operation. This
-          does not change and is the same for all I2C nodes.
+	  does not change and is the same for all I2C nodes.
 
 Example:
 (TODO: merge with existing example):

drivers/usb/host/ehci-hcd.c

@@ -912,4 +912,3 @@ submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 	      dev, pipe, buffer, length, interval);
 	return ehci_submit_async(dev, pipe, buffer, length, NULL);
 }
-

include/configs/mx6qsabrelite.h

@@ -10,7 +10,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.		See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -23,8 +23,8 @@
 #define __CONFIG_H
 
 #define CONFIG_MX6Q
-#define CONFIG_SYS_MX6_HCLK            24000000
-#define CONFIG_SYS_MX6_CLK32           32768
+#define CONFIG_SYS_MX6_HCLK	       24000000
+#define CONFIG_SYS_MX6_CLK32	       32768
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
@@ -38,14 +38,14 @@
 #define CONFIG_REVISION_TAG
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	       (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
 
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE           UART2_BASE
+#define CONFIG_MXC_UART_BASE	       UART2_BASE
 
 #define CONFIG_CMD_SF
 #ifdef CONFIG_CMD_SF
@@ -75,10 +75,10 @@
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
-#define	CONFIG_FEC_MXC
-#define	CONFIG_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
 #define IMX_FEC_BASE			ENET_BASE_ADDR
-#define	CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_XCV_TYPE		RGMII
 #define CONFIG_ETHPRIME			"FEC"
 #define CONFIG_FEC_MXC_PHYADDR		6
 #define CONFIG_PHYLIB
@@ -99,8 +99,8 @@
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX              1
-#define CONFIG_BAUDRATE                        115200
+#define CONFIG_CONS_INDEX	       1
+#define CONFIG_BAUDRATE			       115200
 #define CONFIG_SYS_BAUDRATE_TABLE      {9600, 19200, 38400, 57600, 115200}
 
 /* Command definition */
@@ -108,10 +108,10 @@
 
 #undef CONFIG_CMD_IMLS
 
-#define CONFIG_BOOTDELAY               3
+#define CONFIG_BOOTDELAY	       3
 
-#define CONFIG_LOADADDR                        0x10800000
-#define CONFIG_SYS_TEXT_BASE           0x17800000
+#define CONFIG_LOADADDR			       0x10800000
+#define CONFIG_SYS_TEXT_BASE	       0x17800000
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "script=boot.scr\0" \
@@ -123,33 +123,33 @@
        "mmcpart=2\0" \
        "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
        "mmcargs=setenv bootargs console=${console},${baudrate} " \
-               "root=${mmcroot}\0" \
+	       "root=${mmcroot}\0" \
        "loadbootscript=" \
-               "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	       "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
        "bootscript=echo Running bootscript from mmc ...; " \
-               "source\0" \
+	       "source\0" \
        "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
        "mmcboot=echo Booting from mmc ...; " \
-               "run mmcargs; " \
-               "bootm\0" \
+	       "run mmcargs; " \
+	       "bootm\0" \
        "netargs=setenv bootargs console=${console},${baudrate} " \
-               "root=/dev/nfs " \
-               "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	       "root=/dev/nfs " \
+	       "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
        "netboot=echo Booting from net ...; " \
-               "run netargs; " \
-               "dhcp ${uimage}; bootm\0" \
+	       "run netargs; " \
+	       "dhcp ${uimage}; bootm\0" \
 
 #define CONFIG_BOOTCOMMAND \
        "mmc dev ${mmcdev};" \
        "if mmc rescan ${mmcdev}; then " \
-               "if run loadbootscript; then " \
-                       "run bootscript; " \
-               "else " \
-                       "if run loaduimage; then " \
-                               "run mmcboot; " \
-                       "else run netboot; " \
-                       "fi; " \
-               "fi; " \
+	       "if run loadbootscript; then " \
+		       "run bootscript; " \
+	       "else " \
+		       "if run loaduimage; then " \
+			       "run mmcboot; " \
+		       "else run netboot; " \
+		       "fi; " \
+	       "fi; " \
        "else run netboot; fi"
 
 #define CONFIG_ARP_TIMEOUT     200UL
@@ -158,30 +158,30 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
-#define CONFIG_SYS_PROMPT              "MX6QSABRELITE U-Boot > "
+#define CONFIG_SYS_PROMPT	       "MX6QSABRELITE U-Boot > "
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_CBSIZE	       256
 
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_MAXARGS	       16
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 
 #define CONFIG_SYS_MEMTEST_START       0x10000000
-#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_END	       0x10010000
 
-#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
-#define CONFIG_SYS_HZ                  1000
+#define CONFIG_SYS_LOAD_ADDR	       CONFIG_LOADADDR
+#define CONFIG_SYS_HZ		       1000
 
 #define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE               (128 * 1024)
+#define CONFIG_STACKSIZE	       (128 * 1024)
 
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS           1
-#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE                        (1u * 1024 * 1024 * 1024)
+#define CONFIG_NR_DRAM_BANKS	       1
+#define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			       (1u * 1024 * 1024 * 1024)
 
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
 
@@ -218,4 +218,4 @@
 #define CONFIG_CMD_CACHE
 #endif
 
-#endif                         /* __CONFIG_H */
+#endif			       /* __CONFIG_H */