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@@ -399,7 +399,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
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/* L3 */
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sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
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/* GFX */
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- sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
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+ sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
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/* RESET MGR */
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sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
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/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
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