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@@ -58,7 +58,12 @@
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/* CONFIG_PCI is defined at config time */
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+#ifdef CONFIG_ADS5121_REV2
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#define CFG_MPC512X_CLKIN 66000000 /* in Hz */
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+#else
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+#define CFG_MPC512X_CLKIN 33333333 /* in Hz */
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+#define CONFIG_PCI
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+#endif
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R
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@@ -72,7 +77,11 @@
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/*
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* DDR Setup - manually set all parameters as there's no SPD etc.
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*/
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+#ifdef CONFIG_ADS5121_REV2
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#define CFG_DDR_SIZE 256 /* MB */
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+#else
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+#define CFG_DDR_SIZE 512 /* MB */
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+#endif
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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@@ -120,14 +129,20 @@
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* [09:05] DRAM tRP:
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* [04:00] DRAM tRPA
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*/
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-
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+#ifdef CONFIG_ADS5121_REV2
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#define CFG_MDDRC_SYS_CFG 0xF8604A00
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#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
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+#define CFG_MDDRC_TIME_CFG1 0x54EC1168
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+#define CFG_MDDRC_TIME_CFG2 0x35210864
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+#else
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+#define CFG_MDDRC_SYS_CFG 0xFA804A00
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+#define CFG_MDDRC_SYS_CFG_RUN 0xEA804A00
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+#define CFG_MDDRC_TIME_CFG1 0x68EC1168
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+#define CFG_MDDRC_TIME_CFG2 0x34310864
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+#endif
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#define CFG_MDDRC_SYS_CFG_EN 0xF0000000
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#define CFG_MDDRC_TIME_CFG0 0x00003D2E
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#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
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-#define CFG_MDDRC_TIME_CFG1 0x54EC1168
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-#define CFG_MDDRC_TIME_CFG2 0x35210864
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#define CFG_MICRON_NOP 0x01380000
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#define CFG_MICRON_PCHG_ALL 0x01100400
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@@ -166,12 +181,17 @@
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/*
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* NOR FLASH on the Local Bus
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*/
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+#undef CONFIG_BKUP_FLASH
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#define CFG_FLASH_CFI /* use the Common Flash Interface */
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#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
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+#ifdef CONFIG_BKUP_FLASH
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+#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */
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+#define CFG_FLASH_SIZE 0x00800000 /* max flash size in bytes */
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+#else
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#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */
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#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */
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+#endif
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#define CFG_FLASH_USE_BUFFER_WRITE
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-
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
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#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
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@@ -287,14 +307,13 @@
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#define CONFIG_NET_MULTI
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#define CONFIG_PHY_ADDR 0x1
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#define CONFIG_MII 1 /* MII PHY management */
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+#define CONFIG_FEC_AN_TIMEOUT 1
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-#if 0
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/*
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* Configure on-board RTC
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*/
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-#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
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+#define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */
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#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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-#endif
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/*
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* Environment
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@@ -303,7 +322,11 @@
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/* This has to be a multiple of the Flash sector size */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_ENV_SIZE 0x2000
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+#ifdef CONFIG_BKUP_FLASH
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+#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (256K) for env */
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+#else
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#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
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+#endif
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
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@@ -322,6 +345,7 @@
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_EEPROM
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+#define CONFIG_CMD_DATE
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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