SPEAr: Correct SoC ID offset in misc configuration space

SoC Core ID offset is 0x30 in miscellaneous configuration address
space. It was wrongly mentioned as periph2 clk enable.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

arch/arm/include/asm/arch-spear/spr_misc.h

@@ -37,7 +37,7 @@ struct misc_regs {
 	u32 amba_clk_cfg;	/* 0x24 */
 	u32 periph_clk_cfg;	/* 0x28 */
 	u32 periph1_clken;	/* 0x2C */
-	u32 periph2_clken;	/* 0x30 */
+	u32 soc_core_id;	/* 0x30 */
 	u32 ras_clken;		/* 0x34 */
 	u32 periph1_rst;	/* 0x38 */
 	u32 periph2_rst;	/* 0x3C */