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@@ -44,13 +44,16 @@ typedef volatile unsigned int * dv_reg_p;
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/*
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* Base register addresses
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+ *
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+ * NOTE: some of these DM6446-specific addresses DO NOT WORK
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+ * on other DaVinci chips. Double check them before you try
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+ * using the addresses ... or PSC module identifiers, etc.
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*/
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#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
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#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
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#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
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#define DAVINCI_UART0_BASE (0x01c20000)
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#define DAVINCI_UART1_BASE (0x01c20400)
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-#define DAVINCI_UART2_BASE (0x01c20800)
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#define DAVINCI_I2C_BASE (0x01c21000)
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#define DAVINCI_TIMER0_BASE (0x01c21400)
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#define DAVINCI_TIMER1_BASE (0x01c21800)
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@@ -62,30 +65,41 @@ typedef volatile unsigned int * dv_reg_p;
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#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
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#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
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#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
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-#define DAVINCI_SYSTEM_DFT_BASE (0x01c42000)
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#define DAVINCI_ARM_INTC_BASE (0x01c48000)
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-#define DAVINCI_IEEE1394_BASE (0x01c60000)
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#define DAVINCI_USB_OTG_BASE (0x01c64000)
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#define DAVINCI_CFC_ATA_BASE (0x01c66000)
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#define DAVINCI_SPI_BASE (0x01c66800)
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#define DAVINCI_GPIO_BASE (0x01c67000)
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-#define DAVINCI_UHPI_BASE (0x01c67800)
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#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
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-#define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01c80000)
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-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01c81000)
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-#define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01c82000)
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-#define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01c84000)
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-#define DAVINCI_IMCOP_BASE (0x01cc0000)
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-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01e00000)
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-#define DAVINCI_VLYNQ_BASE (0x01e01000)
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-#define DAVINCI_MCBSP_BASE (0x01e02000)
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-#define DAVINCI_MMC_SD_BASE (0x01e10000)
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-#define DAVINCI_MS_BASE (0x01e20000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
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-#define DAVINCI_VLYNQ_REMOTE_BASE (0x0c000000)
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+
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+#ifdef CONFIG_SOC_DM644X
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+#define DAVINCI_UART2_BASE 0x01c20800
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+#define DAVINCI_UHPI_BASE 0x01c67800
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+#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
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+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
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+#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
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+#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
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+#define DAVINCI_IMCOP_BASE 0x01cc0000
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+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
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+#define DAVINCI_VLYNQ_BASE 0x01e01000
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+#define DAVINCI_ASP_BASE 0x01e02000
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+#define DAVINCI_MMC_SD_BASE 0x01e10000
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+#define DAVINCI_MS_BASE 0x01e20000
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+#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
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+
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+#elif defined(CONFIG_SOC_DM355)
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+#define DAVINCI_MMC_SD1_BASE 0x01e00000
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+#define DAVINCI_ASP0_BASE 0x01e02000
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+#define DAVINCI_ASP1_BASE 0x01e04000
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+#define DAVINCI_UART2_BASE 0x01e06000
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+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
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+#define DAVINCI_MMC_SD0_BASE 0x01e11000
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+
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+#endif
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/* Power and Sleep Controller (PSC) Domains */
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#define DAVINCI_GPSC_ARMDOMAIN 0
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@@ -168,7 +182,14 @@ void davinci_errata_workarounds(void);
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/* Miscellania... */
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#define VBPR (0x20000020)
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-#define PINMUX0 (0x01c40000)
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-#define PINMUX1 (0x01c40004)
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+
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+/* NOTE: system control modules are *highly* chip-specific, both
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+ * as to register content (e.g. for muxing) and which registers exist.
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+ */
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+#define PINMUX0 0x01c40000
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+#define PINMUX1 0x01c40004
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+#define PINMUX2 0x01c40008
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+#define PINMUX3 0x01c4000c
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+#define PINMUX4 0x01c40010
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#endif /* __ASM_ARCH_HARDWARE_H */
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