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@@ -2,7 +2,7 @@
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Andreas Heppel <aheppel@sysgo.de>
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* Andreas Heppel <aheppel@sysgo.de>
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*
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*
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- * (C) Copyright 2002
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+ * (C) Copyright 2002, 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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*
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* See file CREDITS for list of people who contributed to this
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* See file CREDITS for list of people who contributed to this
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@@ -48,12 +48,12 @@
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*
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*
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*/
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*/
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-#define PCI_HOSE_OP(rw, size, type) \
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-int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
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- pci_dev_t dev, \
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- int offset, type value) \
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-{ \
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- return hose->rw##_##size(hose, dev, offset, value); \
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+#define PCI_HOSE_OP(rw, size, type) \
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+int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
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+ pci_dev_t dev, \
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+ int offset, type value) \
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+{ \
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+ return hose->rw##_##size(hose, dev, offset, value); \
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}
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}
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PCI_HOSE_OP(read, byte, u8 *)
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PCI_HOSE_OP(read, byte, u8 *)
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@@ -63,18 +63,18 @@ PCI_HOSE_OP(write, byte, u8)
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PCI_HOSE_OP(write, word, u16)
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PCI_HOSE_OP(write, word, u16)
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PCI_HOSE_OP(write, dword, u32)
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PCI_HOSE_OP(write, dword, u32)
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-#define PCI_OP(rw, size, type, error_code) \
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-int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
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-{ \
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- struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
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- \
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- if (!hose) \
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- { \
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- error_code; \
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- return -1; \
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- } \
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- \
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- return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
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+#define PCI_OP(rw, size, type, error_code) \
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+int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
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+{ \
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+ struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
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+ \
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+ if (!hose) \
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+ { \
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+ error_code; \
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+ return -1; \
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+ } \
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+ \
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+ return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
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}
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}
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PCI_OP(read, byte, u8 *, *value = 0xff)
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PCI_OP(read, byte, u8 *, *value = 0xff)
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@@ -84,40 +84,40 @@ PCI_OP(write, byte, u8, )
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PCI_OP(write, word, u16, )
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PCI_OP(write, word, u16, )
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PCI_OP(write, dword, u32, )
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PCI_OP(write, dword, u32, )
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-#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
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-int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose, \
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- pci_dev_t dev, \
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- int offset, type val) \
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-{ \
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- u32 val32; \
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- \
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- if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) \
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- return -1; \
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- \
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- *val = (val32 >> ((offset & (int)off_mask) * 8)); \
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- \
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- return 0; \
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+#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
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+int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
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+ pci_dev_t dev, \
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+ int offset, type val) \
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+{ \
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+ u32 val32; \
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+ \
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+ if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
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+ return -1; \
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+ \
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+ *val = (val32 >> ((offset & (int)off_mask) * 8)); \
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+ \
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+ return 0; \
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}
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}
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-#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
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-int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose, \
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- pci_dev_t dev, \
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- int offset, type val) \
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-{ \
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- u32 val32, mask, ldata; \
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- \
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- if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) \
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- return -1; \
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- \
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- mask = val_mask; \
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+#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
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+int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
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+ pci_dev_t dev, \
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+ int offset, type val) \
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+{ \
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+ u32 val32, mask, ldata; \
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+ \
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+ if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
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+ return -1; \
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+ \
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+ mask = val_mask; \
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ldata = (((unsigned long)val) & mask) << ((offset & (int)off_mask) * 8);\
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ldata = (((unsigned long)val) & mask) << ((offset & (int)off_mask) * 8);\
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- mask <<= ((mask & (int)off_mask) * 8); \
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- val32 = (val32 & ~mask) | ldata; \
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- \
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- if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0) \
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- return -1; \
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- \
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- return 0; \
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+ mask <<= ((mask & (int)off_mask) * 8); \
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+ val32 = (val32 & ~mask) | ldata; \
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+ \
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+ if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
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+ return -1; \
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+ \
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+ return 0; \
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}
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}
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PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
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PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
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@@ -143,13 +143,12 @@ void pci_register_hose(struct pci_controller* hose)
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*phose = hose;
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*phose = hose;
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}
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}
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-struct pci_controller* pci_bus_to_hose(int bus)
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+struct pci_controller *pci_bus_to_hose (int bus)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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for (hose = hose_head; hose; hose = hose->next)
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for (hose = hose_head; hose; hose = hose->next)
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- if (bus >= hose->first_busno &&
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- bus <= hose->last_busno)
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+ if (bus >= hose->first_busno && bus <= hose->last_busno)
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return hose;
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return hose;
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return NULL;
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return NULL;
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@@ -178,16 +177,13 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
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#endif
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#endif
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bdf += PCI_BDF(0,0,1))
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bdf += PCI_BDF(0,0,1))
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{
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{
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- if (!PCI_FUNC(bdf))
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- {
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+ if (!PCI_FUNC(bdf)) {
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pci_read_config_byte(bdf,
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pci_read_config_byte(bdf,
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PCI_HEADER_TYPE,
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PCI_HEADER_TYPE,
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&header_type);
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&header_type);
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found_multi = header_type & 0x80;
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found_multi = header_type & 0x80;
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- }
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- else
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- {
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+ } else {
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if (!found_multi)
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if (!found_multi)
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continue;
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continue;
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}
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}
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@@ -228,22 +224,20 @@ pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
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*
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*
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*/
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*/
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-unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
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- unsigned long phys_addr,
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- unsigned long flags)
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+unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
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+ unsigned long phys_addr,
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+ unsigned long flags)
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{
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{
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struct pci_region *res;
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struct pci_region *res;
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unsigned long bus_addr;
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unsigned long bus_addr;
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int i;
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int i;
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- if (!hose)
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- {
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- printf("pci_hose_phys_to_bus: %s\n", "invalid hose");
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+ if (!hose) {
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+ printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
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goto Done;
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goto Done;
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}
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}
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- for (i=0; i<hose->region_count; i++)
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- {
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+ for (i = 0; i < hose->region_count; i++) {
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res = &hose->regions[i];
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res = &hose->regions[i];
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if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
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if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
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@@ -252,15 +246,14 @@ unsigned long pci_hose_phys_to_bus(struct pci_controller* hose,
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bus_addr = phys_addr - res->phys_start + res->bus_start;
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bus_addr = phys_addr - res->phys_start + res->bus_start;
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if (bus_addr >= res->bus_start &&
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if (bus_addr >= res->bus_start &&
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- bus_addr < res->bus_start + res->size)
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- {
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+ bus_addr < res->bus_start + res->size) {
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return bus_addr;
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return bus_addr;
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}
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}
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}
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}
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- printf("pci_hose_phys_to_bus: %s\n", "invalid physical address");
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+ printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
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- Done:
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+Done:
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return 0;
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return 0;
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}
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}
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@@ -271,29 +264,26 @@ unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
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struct pci_region *res;
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struct pci_region *res;
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int i;
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int i;
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- if (!hose)
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- {
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- printf("pci_hose_bus_to_phys: %s\n", "invalid hose");
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+ if (!hose) {
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+ printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
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goto Done;
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goto Done;
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}
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}
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- for (i=0; i<hose->region_count; i++)
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- {
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+ for (i = 0; i < hose->region_count; i++) {
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res = &hose->regions[i];
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res = &hose->regions[i];
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if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
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if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
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continue;
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continue;
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if (bus_addr >= res->bus_start &&
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if (bus_addr >= res->bus_start &&
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- bus_addr < res->bus_start + res->size)
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- {
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+ bus_addr < res->bus_start + res->size) {
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return bus_addr - res->bus_start + res->phys_start;
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return bus_addr - res->bus_start + res->phys_start;
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}
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}
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}
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}
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- printf("pci_hose_bus_to_phys: %s\n", "invalid physical address");
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+ printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
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- Done:
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+Done:
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return 0;
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return 0;
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}
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}
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@@ -311,14 +301,14 @@ int pci_hose_config_device(struct pci_controller *hose,
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unsigned char pin;
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unsigned char pin;
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int bar, found_mem64;
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int bar, found_mem64;
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- DEBUGF("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n", io, mem, command);
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+ DEBUGF ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
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+ io, mem, command);
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- pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
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+ pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
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- for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4)
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- {
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- pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
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- pci_hose_read_config_dword(hose, dev, bar, &bar_response);
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+ for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
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+ pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
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+ pci_hose_read_config_dword (hose, dev, bar, &bar_response);
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if (!bar_response)
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if (!bar_response)
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continue;
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continue;
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@@ -326,51 +316,51 @@ int pci_hose_config_device(struct pci_controller *hose,
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found_mem64 = 0;
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found_mem64 = 0;
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/* Check the BAR type and set our address mask */
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/* Check the BAR type and set our address mask */
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- if (bar_response & PCI_BASE_ADDRESS_SPACE)
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- {
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+ if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
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bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
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- bar_value = io;
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-
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+ /* round up region base address to a multiple of size */
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io = ((io - 1) | (bar_size - 1)) + 1;
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io = ((io - 1) | (bar_size - 1)) + 1;
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- }
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- else
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- {
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- if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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- PCI_BASE_ADDRESS_MEM_TYPE_64)
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+ bar_value = io;
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+ /* compute new region base address */
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+ io = io + bar_size;
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+ } else {
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+ if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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+ PCI_BASE_ADDRESS_MEM_TYPE_64)
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found_mem64 = 1;
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found_mem64 = 1;
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bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
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bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
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- bar_value = mem;
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+ /* round up region base address to multiple of size */
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mem = ((mem - 1) | (bar_size - 1)) + 1;
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mem = ((mem - 1) | (bar_size - 1)) + 1;
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+ bar_value = mem;
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+ /* compute new region base address */
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+ mem = mem + bar_size;
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}
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}
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/* Write it out and update our limit */
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/* Write it out and update our limit */
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- pci_hose_write_config_dword(hose, dev, bar, bar_value);
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+ pci_hose_write_config_dword (hose, dev, bar, bar_value);
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|
|
|
|
|
- if (found_mem64)
|
|
|
|
- {
|
|
|
|
|
|
+ if (found_mem64) {
|
|
bar += 4;
|
|
bar += 4;
|
|
- pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
|
|
|
|
|
|
+ pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/* Configure Cache Line Size Register */
|
|
/* Configure Cache Line Size Register */
|
|
- pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
|
|
|
|
|
|
+ pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
|
|
|
|
|
|
/* Configure Latency Timer */
|
|
/* Configure Latency Timer */
|
|
- pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
|
|
|
|
|
|
+ pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
|
|
|
|
|
|
/* Disable interrupt line, if device says it wants to use interrupts */
|
|
/* Disable interrupt line, if device says it wants to use interrupts */
|
|
- pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
|
|
|
|
- if (pin != 0)
|
|
|
|
- {
|
|
|
|
- pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
|
|
|
|
|
|
+ pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
|
|
|
|
+ if (pin != 0) {
|
|
|
|
+ pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
|
|
}
|
|
}
|
|
|
|
|
|
- pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
|
|
|
|
- pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
|
|
|
|
- (old_command & 0xffff0000) | command );
|
|
|
|
|
|
+ pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
|
|
|
|
+ pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
|
|
|
|
+ (old_command & 0xffff0000) | command);
|
|
|
|
|
|
return 0;
|
|
return 0;
|
|
}
|
|
}
|
|
@@ -389,15 +379,13 @@ struct pci_config_table *pci_find_config(struct pci_controller *hose,
|
|
{
|
|
{
|
|
struct pci_config_table *table;
|
|
struct pci_config_table *table;
|
|
|
|
|
|
- for (table = hose->config_table; table && table->vendor; table++)
|
|
|
|
- {
|
|
|
|
|
|
+ for (table = hose->config_table; table && table->vendor; table++) {
|
|
if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
|
|
if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
|
|
(table->device == PCI_ANY_ID || table->device == device) &&
|
|
(table->device == PCI_ANY_ID || table->device == device) &&
|
|
(table->class == PCI_ANY_ID || table->class == class) &&
|
|
(table->class == PCI_ANY_ID || table->class == class) &&
|
|
(table->bus == PCI_ANY_ID || table->bus == bus) &&
|
|
(table->bus == PCI_ANY_ID || table->bus == bus) &&
|
|
(table->dev == PCI_ANY_ID || table->dev == dev) &&
|
|
(table->dev == PCI_ANY_ID || table->dev == dev) &&
|
|
- (table->func == PCI_ANY_ID || table->func == func))
|
|
|
|
- {
|
|
|
|
|
|
+ (table->func == PCI_ANY_ID || table->func == func)) {
|
|
return table;
|
|
return table;
|
|
}
|
|
}
|
|
}
|
|
}
|