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@@ -20,3 +20,9 @@ i.MX5x SoCs.
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This option should be enabled for boards having a SYS_ON_OFF_CTL signal
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This option should be enabled for boards having a SYS_ON_OFF_CTL signal
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connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
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connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
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reference designs.
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reference designs.
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+
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+2. CONVENTIONS FOR FUSE ASSIGNMENTS
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+-----------------------------------
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+
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+2.1 MAC Address: It is stored in the words 9 to 14 of fuse bank 1, using the
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+ natural MAC byte order (i.e. MSB first).
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