sh: Add support for SH2A freestanding build

SH2A toolchains often only provide an fdpic version of libgcc. This
can't be used with bare-metal software like U-Boot, so this patch
provides the necessary functions extracted from libgcc.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

arch/sh/lib/Makefile

@@ -21,8 +21,15 @@
 include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(ARCH).o
+LIBGCC	= $(obj)libgcc.o
 
 SOBJS-y	+=
+GLSOBJS	+= ashiftrt.o
+GLSOBJS	+= ashiftlt.o
+GLSOBJS	+= lshiftrt.o
+GLSOBJS	+= ashldi3.o
+GLSOBJS	+= lshrdi3.o
+GLSOBJS	+= movmem.o
 
 COBJS-y	+= board.o
 COBJS-y	+= bootm.o
@@ -37,10 +44,25 @@ endif
 
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+LGOBJS	:= $(addprefix $(obj),$(GLSOBJS)) \
+	   $(addprefix $(obj),$(GLCOBJS))
+
+# Always build libsh.o
+TARGETS	:= $(LIB)
+
+# Build private libgcc only when asked for
+ifdef USE_PRIVATE_LIBGCC
+TARGETS	+= $(LIBGCC)
+endif
+
+all:	$(TARGETS)
 
 $(LIB):	$(obj).depend $(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+$(LIBGCC): $(obj).depend $(LGOBJS)
+	$(call cmd_link_o_target, $(LGOBJS))
+
 #########################################################################
 
 # defines $(obj).depend target

arch/sh/lib/ashiftlt.S

@@ -0,0 +1,192 @@
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file.  (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+!
+! GLOBAL(ashlsi3)
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+	.global	__ashlsi3
+	.align	2
+__ashlsi3:
+	mov	#31,r0
+	and	r0,r5
+	mova	__ashlsi3_table,r0
+	mov.b	@(r0,r5),r5
+#ifdef __sh1__
+	add	r5,r0
+	jmp	@r0
+#else
+	braf	r5
+#endif
+	mov	r4,r0
+
+	.align	2
+__ashlsi3_table:
+	.byte		__ashlsi3_0-__ashlsi3_table
+	.byte		__ashlsi3_1-__ashlsi3_table
+	.byte		__ashlsi3_2-__ashlsi3_table
+	.byte		__ashlsi3_3-__ashlsi3_table
+	.byte		__ashlsi3_4-__ashlsi3_table
+	.byte		__ashlsi3_5-__ashlsi3_table
+	.byte		__ashlsi3_6-__ashlsi3_table
+	.byte		__ashlsi3_7-__ashlsi3_table
+	.byte		__ashlsi3_8-__ashlsi3_table
+	.byte		__ashlsi3_9-__ashlsi3_table
+	.byte		__ashlsi3_10-__ashlsi3_table
+	.byte		__ashlsi3_11-__ashlsi3_table
+	.byte		__ashlsi3_12-__ashlsi3_table
+	.byte		__ashlsi3_13-__ashlsi3_table
+	.byte		__ashlsi3_14-__ashlsi3_table
+	.byte		__ashlsi3_15-__ashlsi3_table
+	.byte		__ashlsi3_16-__ashlsi3_table
+	.byte		__ashlsi3_17-__ashlsi3_table
+	.byte		__ashlsi3_18-__ashlsi3_table
+	.byte		__ashlsi3_19-__ashlsi3_table
+	.byte		__ashlsi3_20-__ashlsi3_table
+	.byte		__ashlsi3_21-__ashlsi3_table
+	.byte		__ashlsi3_22-__ashlsi3_table
+	.byte		__ashlsi3_23-__ashlsi3_table
+	.byte		__ashlsi3_24-__ashlsi3_table
+	.byte		__ashlsi3_25-__ashlsi3_table
+	.byte		__ashlsi3_26-__ashlsi3_table
+	.byte		__ashlsi3_27-__ashlsi3_table
+	.byte		__ashlsi3_28-__ashlsi3_table
+	.byte		__ashlsi3_29-__ashlsi3_table
+	.byte		__ashlsi3_30-__ashlsi3_table
+	.byte		__ashlsi3_31-__ashlsi3_table
+
+__ashlsi3_6:
+	shll2	r0
+__ashlsi3_4:
+	shll2	r0
+__ashlsi3_2:
+	rts
+	shll2	r0
+
+__ashlsi3_7:
+	shll2	r0
+__ashlsi3_5:
+	shll2	r0
+__ashlsi3_3:
+	shll2	r0
+__ashlsi3_1:
+	rts
+	shll	r0
+
+__ashlsi3_14:
+	shll2	r0
+__ashlsi3_12:
+	shll2	r0
+__ashlsi3_10:
+	shll2	r0
+__ashlsi3_8:
+	rts
+	shll8	r0
+
+__ashlsi3_15:
+	shll2	r0
+__ashlsi3_13:
+	shll2	r0
+__ashlsi3_11:
+	shll2	r0
+__ashlsi3_9:
+	shll8	r0
+	rts
+	shll	r0
+
+__ashlsi3_22:
+	shll2	r0
+__ashlsi3_20:
+	shll2	r0
+__ashlsi3_18:
+	shll2	r0
+__ashlsi3_16:
+	rts
+	shll16	r0
+
+__ashlsi3_23:
+	shll2	r0
+__ashlsi3_21:
+	shll2	r0
+__ashlsi3_19:
+	shll2	r0
+__ashlsi3_17:
+	shll16	r0
+	rts
+	shll	r0
+
+__ashlsi3_30:
+	shll2	r0
+__ashlsi3_28:
+	shll2	r0
+__ashlsi3_26:
+	shll2	r0
+__ashlsi3_24:
+	shll16	r0
+	rts
+	shll8	r0
+
+__ashlsi3_31:
+	shll2	r0
+__ashlsi3_29:
+	shll2	r0
+__ashlsi3_27:
+	shll2	r0
+__ashlsi3_25:
+	shll16	r0
+	shll8	r0
+	rts
+	shll	r0
+
+__ashlsi3_0:
+	rts
+	nop

arch/sh/lib/ashiftrt.S

@@ -0,0 +1,149 @@
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file.  (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+	.global	__ashiftrt_r4_0
+	.global	__ashiftrt_r4_1
+	.global	__ashiftrt_r4_2
+	.global	__ashiftrt_r4_3
+	.global	__ashiftrt_r4_4
+	.global	__ashiftrt_r4_5
+	.global	__ashiftrt_r4_6
+	.global	__ashiftrt_r4_7
+	.global	__ashiftrt_r4_8
+	.global	__ashiftrt_r4_9
+	.global	__ashiftrt_r4_10
+	.global	__ashiftrt_r4_11
+	.global	__ashiftrt_r4_12
+	.global	__ashiftrt_r4_13
+	.global	__ashiftrt_r4_14
+	.global	__ashiftrt_r4_15
+	.global	__ashiftrt_r4_16
+	.global	__ashiftrt_r4_17
+	.global	__ashiftrt_r4_18
+	.global	__ashiftrt_r4_19
+	.global	__ashiftrt_r4_20
+	.global	__ashiftrt_r4_21
+	.global	__ashiftrt_r4_22
+	.global	__ashiftrt_r4_23
+	.global	__ashiftrt_r4_24
+	.global	__ashiftrt_r4_25
+	.global	__ashiftrt_r4_26
+	.global	__ashiftrt_r4_27
+	.global	__ashiftrt_r4_28
+	.global	__ashiftrt_r4_29
+	.global	__ashiftrt_r4_30
+	.global	__ashiftrt_r4_31
+	.global	__ashiftrt_r4_32
+
+	.align	1
+__ashiftrt_r4_32:
+__ashiftrt_r4_31:
+	rotcl	r4
+	rts
+	subc	r4,r4
+__ashiftrt_r4_30:
+	shar	r4
+__ashiftrt_r4_29:
+	shar	r4
+__ashiftrt_r4_28:
+	shar	r4
+__ashiftrt_r4_27:
+	shar	r4
+__ashiftrt_r4_26:
+	shar	r4
+__ashiftrt_r4_25:
+	shar	r4
+__ashiftrt_r4_24:
+	shlr16	r4
+	shlr8	r4
+	rts
+	exts.b	r4,r4
+__ashiftrt_r4_23:
+	shar	r4
+__ashiftrt_r4_22:
+	shar	r4
+__ashiftrt_r4_21:
+	shar	r4
+__ashiftrt_r4_20:
+	shar	r4
+__ashiftrt_r4_19:
+	shar	r4
+__ashiftrt_r4_18:
+	shar	r4
+__ashiftrt_r4_17:
+	shar	r4
+__ashiftrt_r4_16:
+	shlr16	r4
+	rts
+	exts.w	r4,r4
+__ashiftrt_r4_15:
+	shar	r4
+__ashiftrt_r4_14:
+	shar	r4
+__ashiftrt_r4_13:
+	shar	r4
+__ashiftrt_r4_12:
+	shar	r4
+__ashiftrt_r4_11:
+	shar	r4
+__ashiftrt_r4_10:
+	shar	r4
+__ashiftrt_r4_9:
+	shar	r4
+__ashiftrt_r4_8:
+	shar	r4
+__ashiftrt_r4_7:
+	shar	r4
+__ashiftrt_r4_6:
+	shar	r4
+__ashiftrt_r4_5:
+	shar	r4
+__ashiftrt_r4_4:
+	shar	r4
+__ashiftrt_r4_3:
+	shar	r4
+__ashiftrt_r4_2:
+	shar	r4
+__ashiftrt_r4_1:
+	rts
+	shar	r4
+__ashiftrt_r4_0:
+	rts
+	nop

arch/sh/lib/ashldi3.c

@@ -0,0 +1,25 @@
+#include "libgcc.h"
+
+long long __ashldi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.low = 0;
+		w.s.high = (unsigned int) uu.s.low << -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.low >> bm;
+
+		w.s.low = (unsigned int) uu.s.low << b;
+		w.s.high = ((unsigned int) uu.s.high << b) | carries;
+	}
+
+	return w.ll;
+}

arch/sh/lib/libgcc.h

@@ -0,0 +1,25 @@
+#ifndef __ASM_LIBGCC_H
+#define __ASM_LIBGCC_H
+
+#include <asm/byteorder.h>
+
+typedef int word_type __attribute__ ((mode (__word__)));
+
+#ifdef __BIG_ENDIAN
+struct DWstruct {
+	int high, low;
+};
+#elif defined(__LITTLE_ENDIAN)
+struct DWstruct {
+	int low, high;
+};
+#else
+#error I feel sick.
+#endif
+
+typedef union {
+	struct DWstruct s;
+	long long ll;
+} DWunion;
+
+#endif /* __ASM_LIBGCC_H */

arch/sh/lib/lshiftrt.S

@@ -0,0 +1,192 @@
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file.  (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+!
+! __lshrsi3)
+!
+! Entry:
+!
+! r4: Value to shift
+! r5: Shifts
+!
+! Exit:
+!
+! r0: Result
+!
+! Destroys:
+!
+! (none)
+!
+	.global	__lshrsi3
+	.align	2
+__lshrsi3:
+	mov	#31,r0
+	and	r0,r5
+	mova	__lshrsi3_table,r0
+	mov.b	@(r0,r5),r5
+#ifdef __sh1__
+	add	r5,r0
+	jmp	@r0
+#else
+	braf	r5
+#endif
+	mov	r4,r0
+
+	.align	2
+__lshrsi3_table:
+	.byte		__lshrsi3_0-__lshrsi3_table
+	.byte		__lshrsi3_1-__lshrsi3_table
+	.byte		__lshrsi3_2-__lshrsi3_table
+	.byte		__lshrsi3_3-__lshrsi3_table
+	.byte		__lshrsi3_4-__lshrsi3_table
+	.byte		__lshrsi3_5-__lshrsi3_table
+	.byte		__lshrsi3_6-__lshrsi3_table
+	.byte		__lshrsi3_7-__lshrsi3_table
+	.byte		__lshrsi3_8-__lshrsi3_table
+	.byte		__lshrsi3_9-__lshrsi3_table
+	.byte		__lshrsi3_10-__lshrsi3_table
+	.byte		__lshrsi3_11-__lshrsi3_table
+	.byte		__lshrsi3_12-__lshrsi3_table
+	.byte		__lshrsi3_13-__lshrsi3_table
+	.byte		__lshrsi3_14-__lshrsi3_table
+	.byte		__lshrsi3_15-__lshrsi3_table
+	.byte		__lshrsi3_16-__lshrsi3_table
+	.byte		__lshrsi3_17-__lshrsi3_table
+	.byte		__lshrsi3_18-__lshrsi3_table
+	.byte		__lshrsi3_19-__lshrsi3_table
+	.byte		__lshrsi3_20-__lshrsi3_table
+	.byte		__lshrsi3_21-__lshrsi3_table
+	.byte		__lshrsi3_22-__lshrsi3_table
+	.byte		__lshrsi3_23-__lshrsi3_table
+	.byte		__lshrsi3_24-__lshrsi3_table
+	.byte		__lshrsi3_25-__lshrsi3_table
+	.byte		__lshrsi3_26-__lshrsi3_table
+	.byte		__lshrsi3_27-__lshrsi3_table
+	.byte		__lshrsi3_28-__lshrsi3_table
+	.byte		__lshrsi3_29-__lshrsi3_table
+	.byte		__lshrsi3_30-__lshrsi3_table
+	.byte		__lshrsi3_31-__lshrsi3_table
+
+__lshrsi3_6:
+	shlr2	r0
+__lshrsi3_4:
+	shlr2	r0
+__lshrsi3_2:
+	rts
+	shlr2	r0
+
+__lshrsi3_7:
+	shlr2	r0
+__lshrsi3_5:
+	shlr2	r0
+__lshrsi3_3:
+	shlr2	r0
+__lshrsi3_1:
+	rts
+	shlr	r0
+
+__lshrsi3_14:
+	shlr2	r0
+__lshrsi3_12:
+	shlr2	r0
+__lshrsi3_10:
+	shlr2	r0
+__lshrsi3_8:
+	rts
+	shlr8	r0
+
+__lshrsi3_15:
+	shlr2	r0
+__lshrsi3_13:
+	shlr2	r0
+__lshrsi3_11:
+	shlr2	r0
+__lshrsi3_9:
+	shlr8	r0
+	rts
+	shlr	r0
+
+__lshrsi3_22:
+	shlr2	r0
+__lshrsi3_20:
+	shlr2	r0
+__lshrsi3_18:
+	shlr2	r0
+__lshrsi3_16:
+	rts
+	shlr16	r0
+
+__lshrsi3_23:
+	shlr2	r0
+__lshrsi3_21:
+	shlr2	r0
+__lshrsi3_19:
+	shlr2	r0
+__lshrsi3_17:
+	shlr16	r0
+	rts
+	shlr	r0
+
+__lshrsi3_30:
+	shlr2	r0
+__lshrsi3_28:
+	shlr2	r0
+__lshrsi3_26:
+	shlr2	r0
+__lshrsi3_24:
+	shlr16	r0
+	rts
+	shlr8	r0
+
+__lshrsi3_31:
+	shlr2	r0
+__lshrsi3_29:
+	shlr2	r0
+__lshrsi3_27:
+	shlr2	r0
+__lshrsi3_25:
+	shlr16	r0
+	shlr8	r0
+	rts
+	shlr	r0
+
+__lshrsi3_0:
+	rts
+	nop

arch/sh/lib/lshrdi3.c

@@ -0,0 +1,25 @@
+#include "libgcc.h"
+
+long long __lshrdi3(long long u, word_type b)
+{
+	DWunion uu, w;
+	word_type bm;
+
+	if (b == 0)
+		return u;
+
+	uu.ll = u;
+	bm = 32 - b;
+
+	if (bm <= 0) {
+		w.s.high = 0;
+		w.s.low = (unsigned int) uu.s.high >> -bm;
+	} else {
+		const unsigned int carries = (unsigned int) uu.s.high << bm;
+
+		w.s.high = (unsigned int) uu.s.high >> b;
+		w.s.low = ((unsigned int) uu.s.low >> b) | carries;
+	}
+
+	return w.ll;
+}

arch/sh/lib/movmem.S

@@ -0,0 +1,238 @@
+/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006
+   Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file.  (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA.  */
+
+!! libgcc routines for the Renesas / SuperH SH CPUs.
+!! Contributed by Steve Chamberlain.
+!! sac@cygnus.com
+
+!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
+!! recoded in assembly by Toshiyasu Morita
+!! tm@netcom.com
+
+/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and
+   ELF local label prefixes by J"orn Rennecke
+   amylaar@cygnus.com  */
+
+	.text
+	.balign	4
+	.global	__movmem
+	.global __movstr
+	.set __movstr, __movmem
+	/* This would be a lot simpler if r6 contained the byte count
+	   minus 64, and we wouldn't be called here for a byte count of 64.  */
+__movmem:
+	sts.l	pr,@-r15
+	shll2	r6
+	bsr	__movmemSI52+2
+	mov.l	@(48,r5),r0
+	.balign	4
+movmem_loop: /* Reached with rts */
+	mov.l	@(60,r5),r0
+	add	#-64,r6
+	mov.l	r0,@(60,r4)
+	tst	r6,r6
+	mov.l	@(56,r5),r0
+	bt	movmem_done
+	mov.l	r0,@(56,r4)
+	cmp/pl	r6
+	mov.l	@(52,r5),r0
+	add	#64,r5
+	mov.l	r0,@(52,r4)
+	add	#64,r4
+	bt	__movmemSI52
+! done all the large groups, do the remainder
+! jump to movmem+
+	mova	__movmemSI4+4,r0
+	add	r6,r0
+	jmp	@r0
+movmem_done: ! share slot insn, works out aligned.
+	lds.l	@r15+,pr
+	mov.l	r0,@(56,r4)
+	mov.l	@(52,r5),r0
+	rts
+	mov.l	r0,@(52,r4)
+	.balign	4
+
+	.global	__movmemSI64
+	.global __movstrSI64
+	.set	__movstrSI64, __movmemSI64
+__movmemSI64:
+	mov.l	@(60,r5),r0
+	mov.l	r0,@(60,r4)
+	.global	__movmemSI60
+	.global __movstrSI60
+	.set	__movstrSI60, __movmemSI60
+__movmemSI60:
+	mov.l	@(56,r5),r0
+	mov.l	r0,@(56,r4)
+	.global	__movmemSI56
+	.global __movstrSI56
+	.set	__movstrSI56, __movmemSI56
+__movmemSI56:
+	mov.l	@(52,r5),r0
+	mov.l	r0,@(52,r4)
+	.global	__movmemSI52
+	.global __movstrSI52
+	.set	__movstrSI52, __movmemSI52
+__movmemSI52:
+	mov.l	@(48,r5),r0
+	mov.l	r0,@(48,r4)
+	.global	__movmemSI48
+	.global	__movstrSI48
+	.set	__movstrSI48, __movmemSI48
+__movmemSI48:
+	mov.l	@(44,r5),r0
+	mov.l	r0,@(44,r4)
+	.global	__movmemSI44
+	.global	__movstrSI44
+	.set	__movstrSI44, __movmemSI44
+__movmemSI44:
+	mov.l	@(40,r5),r0
+	mov.l	r0,@(40,r4)
+	.global	__movmemSI40
+	.global __movstrSI40
+	.set	__movstrSI40, __movmemSI40
+__movmemSI40:
+	mov.l	@(36,r5),r0
+	mov.l	r0,@(36,r4)
+	.global	__movmemSI36
+	.global	__movstrSI36
+	.set	__movstrSI36, __movmemSI36
+__movmemSI36:
+	mov.l	@(32,r5),r0
+	mov.l	r0,@(32,r4)
+	.global	__movmemSI32
+	.global	__movstrSI32
+	.set	__movstrSI32, __movmemSI32
+__movmemSI32:
+	mov.l	@(28,r5),r0
+	mov.l	r0,@(28,r4)
+	.global	__movmemSI28
+	.global	__movstrSI28
+	.set	__movstrSI28, __movmemSI28
+__movmemSI28:
+	mov.l	@(24,r5),r0
+	mov.l	r0,@(24,r4)
+	.global	__movmemSI24
+	.global	__movstrSI24
+	.set	__movstrSI24, __movmemSI24
+__movmemSI24:
+	mov.l	@(20,r5),r0
+	mov.l	r0,@(20,r4)
+	.global	__movmemSI20
+	.global	__movstrSI20
+	.set	__movstrSI20, __movmemSI20
+__movmemSI20:
+	mov.l	@(16,r5),r0
+	mov.l	r0,@(16,r4)
+	.global	__movmemSI16
+	.global	__movstrSI16
+	.set	__movstrSI16, __movmemSI16
+__movmemSI16:
+	mov.l	@(12,r5),r0
+	mov.l	r0,@(12,r4)
+	.global	__movmemSI12
+	.global	__movstrSI12
+	.set	__movstrSI12, __movmemSI12
+__movmemSI12:
+	mov.l	@(8,r5),r0
+	mov.l	r0,@(8,r4)
+	.global	__movmemSI8
+	.global	__movstrSI8
+	.set	__movstrSI8, __movmemSI8
+__movmemSI8:
+	mov.l	@(4,r5),r0
+	mov.l	r0,@(4,r4)
+	.global	__movmemSI4
+	.global	__movstrSI4
+	.set	__movstrSI4, __movmemSI4
+__movmemSI4:
+	mov.l	@(0,r5),r0
+	rts
+	mov.l	r0,@(0,r4)
+
+	.global	__movmem_i4_even
+	.global	__movstr_i4_even
+	.set	__movstr_i4_even, __movmem_i4_even
+
+	.global	__movmem_i4_odd
+	.global	__movstr_i4_odd
+	.set	__movstr_i4_odd, __movmem_i4_odd
+
+	.global	__movmemSI12_i4
+	.global	__movstrSI12_i4
+	.set	__movstrSI12_i4, __movmemSI12_i4
+
+	.p2align	5
+L_movmem_2mod4_end:
+	mov.l	r0,@(16,r4)
+	rts
+	mov.l	r1,@(20,r4)
+
+	.p2align	2
+
+__movmem_i4_even:
+	mov.l	@r5+,r0
+	bra	L_movmem_start_even
+	mov.l	@r5+,r1
+
+__movmem_i4_odd:
+	mov.l	@r5+,r1
+	add	#-4,r4
+	mov.l	@r5+,r2
+	mov.l	@r5+,r3
+	mov.l	r1,@(4,r4)
+	mov.l	r2,@(8,r4)
+
+L_movmem_loop:
+	mov.l	r3,@(12,r4)
+	dt	r6
+	mov.l	@r5+,r0
+	bt/s	L_movmem_2mod4_end
+	mov.l	@r5+,r1
+	add	#16,r4
+L_movmem_start_even:
+	mov.l	@r5+,r2
+	mov.l	@r5+,r3
+	mov.l	r0,@r4
+	dt	r6
+	mov.l	r1,@(4,r4)
+	bf/s	L_movmem_loop
+	mov.l	r2,@(8,r4)
+	rts
+	mov.l	r3,@(12,r4)
+
+	.p2align	4
+__movmemSI12_i4:
+	mov.l	@r5,r0
+	mov.l	@(4,r5),r1
+	mov.l	@(8,r5),r2
+	mov.l	r0,@r4
+	mov.l	r1,@(4,r4)
+	rts
+	mov.l	r2,@(8,r4)