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+/*
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+ * (C) Copyright 2003
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+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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+ *
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+ * (C) Copyright 2004
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+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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+ *
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+ * (C) Copyright 2005-2009
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+ * Modified for InterControl digsyMTC MPC5200 board by
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+ * Frank Bodammer, GCD Hard- & Software GmbH,
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+ * frank.bodammer@gcd-solutions.de
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+ *
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+ * (C) Copyright 2009
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+ * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+#include <common.h>
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+#include <mpc5xxx.h>
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+#include <net.h>
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+#include <pci.h>
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+#include <asm/processor.h>
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+#include <asm/io.h>
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+#include "eeprom.h"
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+#include "is42s16800a-7t.h"
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+extern int usb_cpu_init(void);
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+
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+#ifndef CONFIG_SYS_RAMBOOT
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+static void sdram_start(int hi_addr)
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+{
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+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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+ long control = SDRAM_CONTROL | hi_addr_bit;
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+
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+ /* unlock mode register */
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+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
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+
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+ /* precharge all banks */
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+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
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+
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+ /* auto refresh */
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+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
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+
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+ /* set mode register */
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+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
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+
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+ /* normal operation */
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+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
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+}
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+#endif
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+
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+/*
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+ * ATTENTION: Although partially referenced initdram does NOT make real use
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+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
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+ * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
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+ */
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+
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+phys_size_t initdram(int board_type)
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+{
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+ ulong dramsize = 0;
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+ ulong dramsize2 = 0;
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+ uint svr, pvr;
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+#ifndef CONFIG_SYS_RAMBOOT
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+ ulong test1, test2;
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+
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+ /* setup SDRAM chip selects */
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+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
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+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
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+
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+ /* setup config registers */
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+ out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
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+ out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
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+
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+ /* find RAM size using SDRAM CS0 only */
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+ sdram_start(0);
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+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
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+ sdram_start(1);
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+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
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+ if (test1 > test2) {
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+ sdram_start(0);
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+ dramsize = test1;
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+ } else {
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+ dramsize = test2;
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+ }
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+
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+ /* memory smaller than 1MB is impossible */
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+ if (dramsize < (1 << 20))
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+ dramsize = 0;
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+
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+ /* set SDRAM CS0 size according to the amount of RAM found */
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+ if (dramsize > 0) {
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+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
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+ (0x13 + __builtin_ffs(dramsize >> 20) - 1));
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+ } else {
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+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
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+ }
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+
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+ /* let SDRAM CS1 start right after CS0 */
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+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
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+
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+ /* find RAM size using SDRAM CS1 only */
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+ test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
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+ 0x08000000);
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+ dramsize2 = test1;
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+
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+ /* memory smaller than 1MB is impossible */
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+ if (dramsize2 < (1 << 20))
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+ dramsize2 = 0;
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+
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+ /* set SDRAM CS1 size according to the amount of RAM found */
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+ if (dramsize2 > 0) {
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+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
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+ (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
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+ } else {
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+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
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+ }
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+
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+#else /* CONFIG_SYS_RAMBOOT */
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+
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+ /* retrieve size of memory connected to SDRAM CS0 */
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+ dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
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+ if (dramsize >= 0x13)
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+ dramsize = (1 << (dramsize - 0x13)) << 20;
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+ else
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+ dramsize = 0;
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+
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+ /* retrieve size of memory connected to SDRAM CS1 */
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+ dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
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+ if (dramsize2 >= 0x13)
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+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
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+ else
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+ dramsize2 = 0;
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+
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+#endif /* CONFIG_SYS_RAMBOOT */
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+
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+ /*
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+ * On MPC5200B we need to set the special configuration delay in the
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+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
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+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
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+ *
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+ * "The SDelay should be written to a value of 0x00000004. It is
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+ * required to account for changes caused by normal wafer processing
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+ * parameters."
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+ */
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+ svr = get_svr();
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+ pvr = get_pvr();
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+ if ((SVR_MJREV(svr) >= 2) &&
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+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
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+ out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
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+
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+ return dramsize + dramsize2;
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+}
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+
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+int checkboard(void)
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+{
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+ char *s = getenv("serial#");
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+
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+ puts ("Board: InterControl digsyMTC");
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+ if (s != NULL) {
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+ puts(", ");
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+ puts(s);
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+ }
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+ putc('\n');
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+
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+ return 0;
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+}
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+
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+int board_early_init_r(void)
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+{
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+ /*
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+ * Now, when we are in RAM, enable flash write access for detection
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+ * process. Note that CS_BOOT cannot be cleared when executing in
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+ * flash.
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+ */
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+ /* disable CS_BOOT */
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+ clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
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+ /* enable CS1 */
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+ setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
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+ /* enable CS0 */
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+ setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
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+
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+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
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+ /* Low level USB init, required for proper kernel operation */
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+ usb_cpu_init();
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+#endif
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+ return (0);
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+}
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+
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+void board_get_enetaddr (uchar * enet)
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+{
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+ ushort read = 0;
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+ ushort addr_of_eth_addr = 0;
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+ ushort len_sys = 0;
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+ ushort len_sys_cfg = 0;
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+
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+ /* check identification word */
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+ eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
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+ if (read != EEPROM_IDENT)
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+ return;
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+
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+ /* calculate offset of config area */
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+ eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
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+ eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
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+ (uchar *)&len_sys_cfg, 2);
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+ addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
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+ if (addr_of_eth_addr >= EEPROM_LEN)
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+ return;
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+
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+ eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
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+}
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+
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+int misc_init_r(void)
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+{
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+ uchar enetaddr[6];
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+
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+ if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
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+ board_get_enetaddr(enetaddr);
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+ eth_setenv_enetaddr("ethaddr", enetaddr);
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+ }
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_PCI
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+static struct pci_controller hose;
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+
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+extern void pci_mpc5xxx_init(struct pci_controller *);
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+
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+void pci_init_board(void)
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+{
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+ pci_mpc5xxx_init(&hose);
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+}
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+#endif
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+
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+#ifdef CONFIG_CMD_IDE
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+
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+#ifdef CONFIG_IDE_RESET
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+
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+void init_ide_reset(void)
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+{
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+ debug ("init_ide_reset\n");
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+
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+ /* set gpio output value to 1 */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
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+ /* open drain output */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
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+ /* direction output */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
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+ /* enable gpio */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
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+
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+}
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+
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+void ide_set_reset(int idereset)
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+{
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+ debug ("ide_reset(%d)\n", idereset);
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+
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+ /* set gpio output value to 0 */
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+ clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
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+ /* open drain output */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
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+ /* direction output */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
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+ /* enable gpio */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
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+
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+ udelay(10000);
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+
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+ /* set gpio output value to 1 */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
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+ /* open drain output */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
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+ /* direction output */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
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+ /* enable gpio */
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+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
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+}
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+#endif /* CONFIG_IDE_RESET */
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+
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+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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+void ft_board_setup(void *blob, bd_t *bd)
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+{
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+ ft_cpu_setup(blob, bd);
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+}
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+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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+
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+#endif /* CONFIG_CMD_IDE */
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+
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