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+/*
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+ * (C) Copyright 2010
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+ * Graeme Russ <graeme.russ@gmail.com>.
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ */
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+
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+
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+#include <config.h>
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+#include <asm/processor-flags.h>
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+#include <asm/ic/sc520.h>
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+
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+.section .text
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+
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+.globl car_init
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+car_init:
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+ /*
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+ * How to enable Cache-As-RAM for the AMD Elan SC520:
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+ * 1. Turn off the CPU Cache (may not be strictly required)
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+ * 2. Set code execution PAR (usually the BOOTCS region) to be
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+ * non-cachable
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+ * 3. Create a Cachable PAR Region for an area of memory which is
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+ * a) NOT where the code is being executed
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+ * b) NOT SDRAM (Controller not initialised yet)
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+ * c) WILL response to read requests
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+ * The easiest way to do this is to create a second BOOTCS
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+ * PAR mappnig with an address != the PAR in step 2
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+ * 4. Issue a wbinvd to invalidate the CPU cache
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+ * 5. Turn on the CPU Cache
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+ * 6. Read 16kB from the cached PAR region setup in step 3
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+ * 7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
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+ *
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+ * The following code uses PAR2 as the cached PAR (PAR0 and PAR1
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+ * are avoided as these are the only two PARs which can be used
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+ * as PCI BUS Memory regions which the board might require)
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+ *
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+ * The configuration of PAR2 must be set in the board configuration
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+ * file as CONFIG_SYS_SC520_CAR_PAR
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+ */
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+
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+ /* Configure Cache-As-RAM PAR */
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+ movl $CONFIG_SYS_SC520_CAR_PAR, %eax
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+ movl $SC520_PAR2, %edi
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+ movl %eax, (%edi)
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+
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+ /* Trash the cache then turn it on */
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+ wbinvd
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+ movl %cr0, %eax
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+ andl $~(X86_CR0_NW | X86_CR0_CD), %eax
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+ movl %eax, %cr0
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+
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+ /*
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+ * The cache is now enabled and empty. Map a region of memory to
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+ * it by reading that region.
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+ */
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+ movl $CONFIG_SYS_CAR_ADDR, %esi
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+ movl $CONFIG_SYS_CAR_SIZE, %ecx
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+ shrl $2, %ecx /* we are reading longs */
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+ cld
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+ rep lodsl
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+
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+ /* Turn off the cache, but don't trash it */
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+ movl %cr0, %eax
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+ orl $(X86_CR0_NW | X86_CR0_CD), %eax
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+ movl %eax, %cr0
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+
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+ /* Clear the CAR region */
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+ xorl %eax, %eax
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+ movl $CONFIG_SYS_CAR_ADDR, %edi
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+ movl $CONFIG_SYS_CAR_SIZE, %ecx
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+ shrl $2, %ecx /* we are writing longs */
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+ rep stosl
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+
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+ /*
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+ * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
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+ * Cache-As-RAM
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+ */
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+ jmp car_init_ret
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Graeme Russ