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@@ -30,6 +30,13 @@
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.text
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.global _start
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_start:
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+ /*
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+ * reserve registers:
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+ * r10: Stores little/big endian offset for vectors
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+ * r2: Stores imm opcode
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+ * r3: Stores brai opcode
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+ */
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+
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mts rmsr, r0 /* disable cache */
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addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
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addi r1, r1, -4 /* Decrement SP to top of memory */
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@@ -44,52 +51,34 @@ _start:
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* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
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*/
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addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
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- swi r6, r0, 0
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- lbui r10, r0, 0
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- swi r6, r0, 0x40
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- swi r10, r0, 0x50
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-
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- /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
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- addi r6, r0, 0xb0000000 /* hex b000 opcode imm */
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- swi r6, r0, 0x0 /* reset address */
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- swi r6, r0, 0x8 /* user vector exception */
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- swi r6, r0, 0x10 /* interrupt */
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- swi r6, r0, 0x20 /* hardware exception */
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-
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- addi r6, r0, 0xb8080000 /* hew b808 opcode brai*/
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- swi r6, r0, 0x4 /* reset address */
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- swi r6, r0, 0xC /* user vector exception */
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- swi r6, r0, 0x14 /* interrupt */
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- swi r6, r0, 0x24 /* hardware exception */
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+ lwi r7, r0, 0x28
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+ swi r6, r0, 0x28 /* used first unused MB vector */
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+ lbui r10, r0, 0x28 /* used first unused MB vector */
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+ swi r7, r0, 0x28
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+
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+ /* add opcode instruction for 32bit jump - 2 instruction imm & brai */
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+ addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
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+ addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
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#ifdef CONFIG_SYS_RESET_ADDRESS
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/* reset address */
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+ swi r2, r0, 0x0 /* reset address - imm opcode */
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+ swi r3, r0, 0x4 /* reset address - brai opcode */
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+
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addik r6, r0, CONFIG_SYS_RESET_ADDRESS
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sw r6, r1, r0
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- lhu r7, r1, r0
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- shi r7, r0, 0x2
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- shi r6, r0, 0x6
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-/*
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- * Copy U-Boot code to CONFIG_SYS_TEXT_BASE
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- * solve problem with sbrk_base
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- */
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-#if (CONFIG_SYS_RESET_ADDRESS != CONFIG_SYS_TEXT_BASE)
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- addi r4, r0, __end
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- addi r5, r0, __text_start
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- rsub r4, r5, r4 /* size = __end - __text_start */
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- addi r6, r0, CONFIG_SYS_RESET_ADDRESS /* source address */
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- addi r7, r0, 0 /* counter */
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-4:
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- lw r8, r6, r7
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- sw r8, r5, r7
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- addi r7, r7, 0x4
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- cmp r8, r4, r7
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- blti r8, 4b
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-#endif
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+ lhu r7, r1, r10
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+ rsubi r8, r10, 0x2
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+ sh r7, r0, r8
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+ rsubi r8, r10, 0x6
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+ sh r6, r0, r8
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#endif
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#ifdef CONFIG_SYS_USR_EXCEP
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/* user_vector_exception */
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+ swi r2, r0, 0x8 /* user vector exception - imm opcode */
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+ swi r3, r0, 0xC /* user vector exception - brai opcode */
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+
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addik r6, r0, _exception_handler
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sw r6, r1, r0
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/*
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@@ -121,6 +110,9 @@ _start:
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#ifdef CONFIG_SYS_INTC_0
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/* interrupt_handler */
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+ swi r2, r0, 0x10 /* interrupt - imm opcode */
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+ swi r3, r0, 0x14 /* interrupt - brai opcode */
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+
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addik r6, r0, _interrupt_handler
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sw r6, r1, r0
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lhu r7, r1, r10
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@@ -131,6 +123,9 @@ _start:
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#endif
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/* hardware exception */
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+ swi r2, r0, 0x20 /* hardware exception - imm opcode */
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+ swi r3, r0, 0x24 /* hardware exception - brai opcode */
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+
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addik r6, r0, _hw_exception_handler
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sw r6, r1, r0
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lhu r7, r1, r10
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